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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 -mattr=+use-experimental-zeroing-pseudos < %s | FileCheck %s3 4;5; SQSHLU6;7 8define <vscale x 16 x i8> @sqshlu_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {9; CHECK-LABEL: sqshlu_i8:10; CHECK: // %bb.0:11; CHECK-NEXT: movprfx z0.b, p0/z, z0.b12; CHECK-NEXT: sqshlu z0.b, p0/m, z0.b, #213; CHECK-NEXT: ret14 %a_z = select <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer15 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqshlu.nxv16i8(<vscale x 16 x i1> %pg,16 <vscale x 16 x i8> %a_z,17 i32 2)18 ret <vscale x 16 x i8> %out19}20 21define <vscale x 8 x i16> @sqshlu_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {22; CHECK-LABEL: sqshlu_i16:23; CHECK: // %bb.0:24; CHECK-NEXT: movprfx z0.h, p0/z, z0.h25; CHECK-NEXT: sqshlu z0.h, p0/m, z0.h, #326; CHECK-NEXT: ret27 %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> zeroinitializer28 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqshlu.nxv8i16(<vscale x 8 x i1> %pg,29 <vscale x 8 x i16> %a_z,30 i32 3)31 ret <vscale x 8 x i16> %out32}33 34define <vscale x 4 x i32> @sqshlu_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {35; CHECK-LABEL: sqshlu_i32:36; CHECK: // %bb.0:37; CHECK-NEXT: movprfx z0.s, p0/z, z0.s38; CHECK-NEXT: sqshlu z0.s, p0/m, z0.s, #2939; CHECK-NEXT: ret40 %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> zeroinitializer41 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqshlu.nxv4i32(<vscale x 4 x i1> %pg,42 <vscale x 4 x i32> %a_z,43 i32 29)44 ret <vscale x 4 x i32> %out45}46 47define <vscale x 2 x i64> @sqshlu_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {48; CHECK-LABEL: sqshlu_i64:49; CHECK: // %bb.0:50; CHECK-NEXT: movprfx z0.d, p0/z, z0.d51; CHECK-NEXT: sqshlu z0.d, p0/m, z0.d, #6252; CHECK-NEXT: ret53 %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> zeroinitializer54 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqshlu.nxv2i64(<vscale x 2 x i1> %pg,55 <vscale x 2 x i64> %a_z,56 i32 62)57 ret <vscale x 2 x i64> %out58}59 60declare <vscale x 16 x i8> @llvm.aarch64.sve.sqshlu.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, i32)61declare <vscale x 8 x i16> @llvm.aarch64.sve.sqshlu.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, i32)62declare <vscale x 4 x i32> @llvm.aarch64.sve.sqshlu.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i32)63declare <vscale x 2 x i64> @llvm.aarch64.sve.sqshlu.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i32)64