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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s4; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s5 6;7; SADDLBT8;9 10define <vscale x 8 x i16> @saddlbt_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {11; CHECK-LABEL: saddlbt_b:12; CHECK: // %bb.0:13; CHECK-NEXT: saddlbt z0.h, z0.b, z1.b14; CHECK-NEXT: ret15 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.saddlbt.nxv8i16(<vscale x 16 x i8> %a,16 <vscale x 16 x i8> %b)17 ret <vscale x 8 x i16> %out18}19 20define <vscale x 4 x i32> @saddlbt_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {21; CHECK-LABEL: saddlbt_h:22; CHECK: // %bb.0:23; CHECK-NEXT: saddlbt z0.s, z0.h, z1.h24; CHECK-NEXT: ret25 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.saddlbt.nxv4i32(<vscale x 8 x i16> %a,26 <vscale x 8 x i16> %b)27 ret <vscale x 4 x i32> %out28}29 30define <vscale x 2 x i64> @saddlbt_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {31; CHECK-LABEL: saddlbt_s:32; CHECK: // %bb.0:33; CHECK-NEXT: saddlbt z0.d, z0.s, z1.s34; CHECK-NEXT: ret35 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.saddlbt.nxv2i64(<vscale x 4 x i32> %a,36 <vscale x 4 x i32> %b)37 ret <vscale x 2 x i64> %out38}39 40;41; SSUBLBT42;43 44define <vscale x 8 x i16> @ssublbt_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {45; CHECK-LABEL: ssublbt_b:46; CHECK: // %bb.0:47; CHECK-NEXT: ssublbt z0.h, z0.b, z1.b48; CHECK-NEXT: ret49 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.ssublbt.nxv8i16(<vscale x 16 x i8> %a,50 <vscale x 16 x i8> %b)51 ret <vscale x 8 x i16> %out52}53 54define <vscale x 4 x i32> @ssublbt_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {55; CHECK-LABEL: ssublbt_h:56; CHECK: // %bb.0:57; CHECK-NEXT: ssublbt z0.s, z0.h, z1.h58; CHECK-NEXT: ret59 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.ssublbt.nxv4i32(<vscale x 8 x i16> %a,60 <vscale x 8 x i16> %b)61 ret <vscale x 4 x i32> %out62}63 64define <vscale x 2 x i64> @ssublbt_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {65; CHECK-LABEL: ssublbt_s:66; CHECK: // %bb.0:67; CHECK-NEXT: ssublbt z0.d, z0.s, z1.s68; CHECK-NEXT: ret69 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.ssublbt.nxv2i64(<vscale x 4 x i32> %a,70 <vscale x 4 x i32> %b)71 ret <vscale x 2 x i64> %out72}73 74;75; SSUBLTB76;77 78define <vscale x 8 x i16> @ssubltb_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {79; CHECK-LABEL: ssubltb_b:80; CHECK: // %bb.0:81; CHECK-NEXT: ssubltb z0.h, z0.b, z1.b82; CHECK-NEXT: ret83 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.ssubltb.nxv8i16(<vscale x 16 x i8> %a,84 <vscale x 16 x i8> %b)85 ret <vscale x 8 x i16> %out86}87 88define <vscale x 4 x i32> @ssubltb_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {89; CHECK-LABEL: ssubltb_h:90; CHECK: // %bb.0:91; CHECK-NEXT: ssubltb z0.s, z0.h, z1.h92; CHECK-NEXT: ret93 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.ssubltb.nxv4i32(<vscale x 8 x i16> %a,94 <vscale x 8 x i16> %b)95 ret <vscale x 4 x i32> %out96}97 98define <vscale x 2 x i64> @ssubltb_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {99; CHECK-LABEL: ssubltb_s:100; CHECK: // %bb.0:101; CHECK-NEXT: ssubltb z0.d, z0.s, z1.s102; CHECK-NEXT: ret103 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.ssubltb.nxv2i64(<vscale x 4 x i32> %a,104 <vscale x 4 x i32> %b)105 ret <vscale x 2 x i64> %out106}107 108declare <vscale x 8 x i16> @llvm.aarch64.sve.saddlbt.nxv8i16(<vscale x 16 x i8>, <vscale x 16 x i8>)109declare <vscale x 4 x i32> @llvm.aarch64.sve.saddlbt.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>)110declare <vscale x 2 x i64> @llvm.aarch64.sve.saddlbt.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>)111 112declare <vscale x 8 x i16> @llvm.aarch64.sve.ssublbt.nxv8i16(<vscale x 16 x i8>, <vscale x 16 x i8>)113declare <vscale x 4 x i32> @llvm.aarch64.sve.ssublbt.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>)114declare <vscale x 2 x i64> @llvm.aarch64.sve.ssublbt.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>)115 116declare <vscale x 8 x i16> @llvm.aarch64.sve.ssubltb.nxv8i16(<vscale x 16 x i8>, <vscale x 16 x i8>)117declare <vscale x 4 x i32> @llvm.aarch64.sve.ssubltb.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>)118declare <vscale x 2 x i64> @llvm.aarch64.sve.ssubltb.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>)119