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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s4; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s5 6;7; SABALB8;9 10define <vscale x 8 x i16> @sabalb_b(<vscale x 8 x i16> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {11; CHECK-LABEL: sabalb_b:12; CHECK: // %bb.0:13; CHECK-NEXT: sabalb z0.h, z1.b, z2.b14; CHECK-NEXT: ret15 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sabalb.nxv8i16(<vscale x 8 x i16> %a,16 <vscale x 16 x i8> %b,17 <vscale x 16 x i8> %c)18 ret <vscale x 8 x i16> %out19}20 21define <vscale x 4 x i32> @sabalb_h(<vscale x 4 x i32> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {22; CHECK-LABEL: sabalb_h:23; CHECK: // %bb.0:24; CHECK-NEXT: sabalb z0.s, z1.h, z2.h25; CHECK-NEXT: ret26 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sabalb.nxv4i32(<vscale x 4 x i32> %a,27 <vscale x 8 x i16> %b,28 <vscale x 8 x i16> %c)29 ret <vscale x 4 x i32> %out30}31 32define <vscale x 2 x i64> @sabalb_s(<vscale x 2 x i64> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {33; CHECK-LABEL: sabalb_s:34; CHECK: // %bb.0:35; CHECK-NEXT: sabalb z0.d, z1.s, z2.s36; CHECK-NEXT: ret37 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sabalb.nxv2i64(<vscale x 2 x i64> %a,38 <vscale x 4 x i32> %b,39 <vscale x 4 x i32> %c)40 ret <vscale x 2 x i64> %out41}42 43;44; SABALT45;46 47define <vscale x 8 x i16> @sabalt_b(<vscale x 8 x i16> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {48; CHECK-LABEL: sabalt_b:49; CHECK: // %bb.0:50; CHECK-NEXT: sabalt z0.h, z1.b, z2.b51; CHECK-NEXT: ret52 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sabalt.nxv8i16(<vscale x 8 x i16> %a,53 <vscale x 16 x i8> %b,54 <vscale x 16 x i8> %c)55 ret <vscale x 8 x i16> %out56}57 58define <vscale x 4 x i32> @sabalt_h(<vscale x 4 x i32> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {59; CHECK-LABEL: sabalt_h:60; CHECK: // %bb.0:61; CHECK-NEXT: sabalt z0.s, z1.h, z2.h62; CHECK-NEXT: ret63 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sabalt.nxv4i32(<vscale x 4 x i32> %a,64 <vscale x 8 x i16> %b,65 <vscale x 8 x i16> %c)66 ret <vscale x 4 x i32> %out67}68 69define <vscale x 2 x i64> @sabalt_s(<vscale x 2 x i64> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {70; CHECK-LABEL: sabalt_s:71; CHECK: // %bb.0:72; CHECK-NEXT: sabalt z0.d, z1.s, z2.s73; CHECK-NEXT: ret74 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sabalt.nxv2i64(<vscale x 2 x i64> %a,75 <vscale x 4 x i32> %b,76 <vscale x 4 x i32> %c)77 ret <vscale x 2 x i64> %out78}79 80;81; SABDLB82;83 84define <vscale x 8 x i16> @sabdlb_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {85; CHECK-LABEL: sabdlb_b:86; CHECK: // %bb.0:87; CHECK-NEXT: sabdlb z0.h, z0.b, z1.b88; CHECK-NEXT: ret89 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sabdlb.nxv8i16(<vscale x 16 x i8> %a,90 <vscale x 16 x i8> %b)91 ret <vscale x 8 x i16> %out92}93 94define <vscale x 4 x i32> @sabdlb_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {95; CHECK-LABEL: sabdlb_h:96; CHECK: // %bb.0:97; CHECK-NEXT: sabdlb z0.s, z0.h, z1.h98; CHECK-NEXT: ret99 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sabdlb.nxv4i32(<vscale x 8 x i16> %a,100 <vscale x 8 x i16> %b)101 ret <vscale x 4 x i32> %out102}103 104define <vscale x 2 x i64> @sabdlb_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {105; CHECK-LABEL: sabdlb_s:106; CHECK: // %bb.0:107; CHECK-NEXT: sabdlb z0.d, z0.s, z1.s108; CHECK-NEXT: ret109 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sabdlb.nxv2i64(<vscale x 4 x i32> %a,110 <vscale x 4 x i32> %b)111 ret <vscale x 2 x i64> %out112}113 114;115; SABDLT116;117 118define <vscale x 8 x i16> @sabdlt_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {119; CHECK-LABEL: sabdlt_b:120; CHECK: // %bb.0:121; CHECK-NEXT: sabdlt z0.h, z0.b, z1.b122; CHECK-NEXT: ret123 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sabdlt.nxv8i16(<vscale x 16 x i8> %a,124 <vscale x 16 x i8> %b)125 ret <vscale x 8 x i16> %out126}127 128define <vscale x 4 x i32> @sabdlt_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {129; CHECK-LABEL: sabdlt_h:130; CHECK: // %bb.0:131; CHECK-NEXT: sabdlt z0.s, z0.h, z1.h132; CHECK-NEXT: ret133 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sabdlt.nxv4i32(<vscale x 8 x i16> %a,134 <vscale x 8 x i16> %b)135 ret <vscale x 4 x i32> %out136}137 138define <vscale x 2 x i64> @sabdlt_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {139; CHECK-LABEL: sabdlt_s:140; CHECK: // %bb.0:141; CHECK-NEXT: sabdlt z0.d, z0.s, z1.s142; CHECK-NEXT: ret143 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sabdlt.nxv2i64(<vscale x 4 x i32> %a,144 <vscale x 4 x i32> %b)145 ret <vscale x 2 x i64> %out146}147 148;149; SADDLB150;151 152define <vscale x 8 x i16> @saddlb_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {153; CHECK-LABEL: saddlb_b:154; CHECK: // %bb.0:155; CHECK-NEXT: saddlb z0.h, z0.b, z1.b156; CHECK-NEXT: ret157 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.saddlb.nxv8i16(<vscale x 16 x i8> %a,158 <vscale x 16 x i8> %b)159 ret <vscale x 8 x i16> %out160}161 162define <vscale x 4 x i32> @saddlb_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {163; CHECK-LABEL: saddlb_h:164; CHECK: // %bb.0:165; CHECK-NEXT: saddlb z0.s, z0.h, z1.h166; CHECK-NEXT: ret167 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.saddlb.nxv4i32(<vscale x 8 x i16> %a,168 <vscale x 8 x i16> %b)169 ret <vscale x 4 x i32> %out170}171 172define <vscale x 2 x i64> @saddlb_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {173; CHECK-LABEL: saddlb_s:174; CHECK: // %bb.0:175; CHECK-NEXT: saddlb z0.d, z0.s, z1.s176; CHECK-NEXT: ret177 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.saddlb.nxv2i64(<vscale x 4 x i32> %a,178 <vscale x 4 x i32> %b)179 ret <vscale x 2 x i64> %out180}181 182;183; SADDLT184;185 186define <vscale x 8 x i16> @saddlt_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {187; CHECK-LABEL: saddlt_b:188; CHECK: // %bb.0:189; CHECK-NEXT: saddlt z0.h, z0.b, z1.b190; CHECK-NEXT: ret191 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.saddlt.nxv8i16(<vscale x 16 x i8> %a,192 <vscale x 16 x i8> %b)193 ret <vscale x 8 x i16> %out194}195 196define <vscale x 4 x i32> @saddlt_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {197; CHECK-LABEL: saddlt_h:198; CHECK: // %bb.0:199; CHECK-NEXT: saddlt z0.s, z0.h, z1.h200; CHECK-NEXT: ret201 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.saddlt.nxv4i32(<vscale x 8 x i16> %a,202 <vscale x 8 x i16> %b)203 ret <vscale x 4 x i32> %out204}205 206define <vscale x 2 x i64> @saddlt_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {207; CHECK-LABEL: saddlt_s:208; CHECK: // %bb.0:209; CHECK-NEXT: saddlt z0.d, z0.s, z1.s210; CHECK-NEXT: ret211 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.saddlt.nxv2i64(<vscale x 4 x i32> %a,212 <vscale x 4 x i32> %b)213 ret <vscale x 2 x i64> %out214}215 216;217; SADDWB218;219 220define <vscale x 8 x i16> @saddwb_b(<vscale x 8 x i16> %a, <vscale x 16 x i8> %b) {221; CHECK-LABEL: saddwb_b:222; CHECK: // %bb.0:223; CHECK-NEXT: saddwb z0.h, z0.h, z1.b224; CHECK-NEXT: ret225 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.saddwb.nxv8i16(<vscale x 8 x i16> %a,226 <vscale x 16 x i8> %b)227 ret <vscale x 8 x i16> %out228}229 230define <vscale x 4 x i32> @saddwb_h(<vscale x 4 x i32> %a, <vscale x 8 x i16> %b) {231; CHECK-LABEL: saddwb_h:232; CHECK: // %bb.0:233; CHECK-NEXT: saddwb z0.s, z0.s, z1.h234; CHECK-NEXT: ret235 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.saddwb.nxv4i32(<vscale x 4 x i32> %a,236 <vscale x 8 x i16> %b)237 ret <vscale x 4 x i32> %out238}239 240define <vscale x 2 x i64> @saddwb_s(<vscale x 2 x i64> %a, <vscale x 4 x i32> %b) {241; CHECK-LABEL: saddwb_s:242; CHECK: // %bb.0:243; CHECK-NEXT: saddwb z0.d, z0.d, z1.s244; CHECK-NEXT: ret245 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.saddwb.nxv2i64(<vscale x 2 x i64> %a,246 <vscale x 4 x i32> %b)247 ret <vscale x 2 x i64> %out248}249 250;251; SADDWT252;253 254define <vscale x 8 x i16> @saddwt_b(<vscale x 8 x i16> %a, <vscale x 16 x i8> %b) {255; CHECK-LABEL: saddwt_b:256; CHECK: // %bb.0:257; CHECK-NEXT: saddwt z0.h, z0.h, z1.b258; CHECK-NEXT: ret259 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.saddwt.nxv8i16(<vscale x 8 x i16> %a,260 <vscale x 16 x i8> %b)261 ret <vscale x 8 x i16> %out262}263 264define <vscale x 4 x i32> @saddwt_h(<vscale x 4 x i32> %a, <vscale x 8 x i16> %b) {265; CHECK-LABEL: saddwt_h:266; CHECK: // %bb.0:267; CHECK-NEXT: saddwt z0.s, z0.s, z1.h268; CHECK-NEXT: ret269 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.saddwt.nxv4i32(<vscale x 4 x i32> %a,270 <vscale x 8 x i16> %b)271 ret <vscale x 4 x i32> %out272}273 274define <vscale x 2 x i64> @saddwt_s(<vscale x 2 x i64> %a, <vscale x 4 x i32> %b) {275; CHECK-LABEL: saddwt_s:276; CHECK: // %bb.0:277; CHECK-NEXT: saddwt z0.d, z0.d, z1.s278; CHECK-NEXT: ret279 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.saddwt.nxv2i64(<vscale x 2 x i64> %a,280 <vscale x 4 x i32> %b)281 ret <vscale x 2 x i64> %out282}283 284 285;286; SMULLB (Vectors)287;288 289define <vscale x 8 x i16> @smullb_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {290; CHECK-LABEL: smullb_b:291; CHECK: // %bb.0:292; CHECK-NEXT: smullb z0.h, z0.b, z1.b293; CHECK-NEXT: ret294 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.smullb.nxv8i16(<vscale x 16 x i8> %a,295 <vscale x 16 x i8> %b)296 ret <vscale x 8 x i16> %out297}298 299define <vscale x 4 x i32> @smullb_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {300; CHECK-LABEL: smullb_h:301; CHECK: // %bb.0:302; CHECK-NEXT: smullb z0.s, z0.h, z1.h303; CHECK-NEXT: ret304 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.smullb.nxv4i32(<vscale x 8 x i16> %a,305 <vscale x 8 x i16> %b)306 ret <vscale x 4 x i32> %out307}308 309define <vscale x 2 x i64> @smullb_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {310; CHECK-LABEL: smullb_s:311; CHECK: // %bb.0:312; CHECK-NEXT: smullb z0.d, z0.s, z1.s313; CHECK-NEXT: ret314 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.smullb.nxv2i64(<vscale x 4 x i32> %a,315 <vscale x 4 x i32> %b)316 ret <vscale x 2 x i64> %out317}318 319;320; SMULLB (Indexed)321;322 323define <vscale x 4 x i32> @smullb_lane_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {324; CHECK-LABEL: smullb_lane_h:325; CHECK: // %bb.0:326; CHECK-NEXT: smullb z0.s, z0.h, z1.h[4]327; CHECK-NEXT: ret328 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.smullb.lane.nxv4i32(<vscale x 8 x i16> %a,329 <vscale x 8 x i16> %b,330 i32 4)331 ret <vscale x 4 x i32> %out332}333 334define <vscale x 2 x i64> @smullb_lane_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {335; CHECK-LABEL: smullb_lane_s:336; CHECK: // %bb.0:337; CHECK-NEXT: smullb z0.d, z0.s, z1.s[3]338; CHECK-NEXT: ret339 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.smullb.lane.nxv2i64(<vscale x 4 x i32> %a,340 <vscale x 4 x i32> %b,341 i32 3)342 ret <vscale x 2 x i64> %out343}344 345;346; SMULLT (Vectors)347;348 349define <vscale x 8 x i16> @smullt_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {350; CHECK-LABEL: smullt_b:351; CHECK: // %bb.0:352; CHECK-NEXT: smullt z0.h, z0.b, z1.b353; CHECK-NEXT: ret354 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.smullt.nxv8i16(<vscale x 16 x i8> %a,355 <vscale x 16 x i8> %b)356 ret <vscale x 8 x i16> %out357}358 359define <vscale x 4 x i32> @smullt_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {360; CHECK-LABEL: smullt_h:361; CHECK: // %bb.0:362; CHECK-NEXT: smullt z0.s, z0.h, z1.h363; CHECK-NEXT: ret364 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.smullt.nxv4i32(<vscale x 8 x i16> %a,365 <vscale x 8 x i16> %b)366 ret <vscale x 4 x i32> %out367}368 369define <vscale x 2 x i64> @smullt_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {370; CHECK-LABEL: smullt_s:371; CHECK: // %bb.0:372; CHECK-NEXT: smullt z0.d, z0.s, z1.s373; CHECK-NEXT: ret374 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.smullt.nxv2i64(<vscale x 4 x i32> %a,375 <vscale x 4 x i32> %b)376 ret <vscale x 2 x i64> %out377}378 379;380; SMULLT (Indexed)381;382 383define <vscale x 4 x i32> @smullt_lane_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {384; CHECK-LABEL: smullt_lane_h:385; CHECK: // %bb.0:386; CHECK-NEXT: smullt z0.s, z0.h, z1.h[5]387; CHECK-NEXT: ret388 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.smullt.lane.nxv4i32(<vscale x 8 x i16> %a,389 <vscale x 8 x i16> %b,390 i32 5)391 ret <vscale x 4 x i32> %out392}393 394define <vscale x 2 x i64> @smullt_lane_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {395; CHECK-LABEL: smullt_lane_s:396; CHECK: // %bb.0:397; CHECK-NEXT: smullt z0.d, z0.s, z1.s[2]398; CHECK-NEXT: ret399 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.smullt.lane.nxv2i64(<vscale x 4 x i32> %a,400 <vscale x 4 x i32> %b,401 i32 2)402 ret <vscale x 2 x i64> %out403}404 405;406; SQDMULLB (Vectors)407;408 409define <vscale x 8 x i16> @sqdmullb_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {410; CHECK-LABEL: sqdmullb_b:411; CHECK: // %bb.0:412; CHECK-NEXT: sqdmullb z0.h, z0.b, z1.b413; CHECK-NEXT: ret414 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqdmullb.nxv8i16(<vscale x 16 x i8> %a,415 <vscale x 16 x i8> %b)416 ret <vscale x 8 x i16> %out417}418 419define <vscale x 4 x i32> @sqdmullb_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {420; CHECK-LABEL: sqdmullb_h:421; CHECK: // %bb.0:422; CHECK-NEXT: sqdmullb z0.s, z0.h, z1.h423; CHECK-NEXT: ret424 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdmullb.nxv4i32(<vscale x 8 x i16> %a,425 <vscale x 8 x i16> %b)426 ret <vscale x 4 x i32> %out427}428 429define <vscale x 2 x i64> @sqdmullb_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {430; CHECK-LABEL: sqdmullb_s:431; CHECK: // %bb.0:432; CHECK-NEXT: sqdmullb z0.d, z0.s, z1.s433; CHECK-NEXT: ret434 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdmullb.nxv2i64(<vscale x 4 x i32> %a,435 <vscale x 4 x i32> %b)436 ret <vscale x 2 x i64> %out437}438 439;440; SQDMULLB (Indexed)441;442 443define <vscale x 4 x i32> @sqdmullb_lane_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {444; CHECK-LABEL: sqdmullb_lane_h:445; CHECK: // %bb.0:446; CHECK-NEXT: sqdmullb z0.s, z0.h, z1.h[2]447; CHECK-NEXT: ret448 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdmullb.lane.nxv4i32(<vscale x 8 x i16> %a,449 <vscale x 8 x i16> %b,450 i32 2)451 ret <vscale x 4 x i32> %out452}453 454define <vscale x 2 x i64> @sqdmullb_lane_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {455; CHECK-LABEL: sqdmullb_lane_s:456; CHECK: // %bb.0:457; CHECK-NEXT: sqdmullb z0.d, z0.s, z1.s[1]458; CHECK-NEXT: ret459 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdmullb.lane.nxv2i64(<vscale x 4 x i32> %a,460 <vscale x 4 x i32> %b,461 i32 1)462 ret <vscale x 2 x i64> %out463}464 465;466; SQDMULLT (Vectors)467;468 469define <vscale x 8 x i16> @sqdmullt_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {470; CHECK-LABEL: sqdmullt_b:471; CHECK: // %bb.0:472; CHECK-NEXT: sqdmullt z0.h, z0.b, z1.b473; CHECK-NEXT: ret474 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqdmullt.nxv8i16(<vscale x 16 x i8> %a,475 <vscale x 16 x i8> %b)476 ret <vscale x 8 x i16> %out477}478 479define <vscale x 4 x i32> @sqdmullt_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {480; CHECK-LABEL: sqdmullt_h:481; CHECK: // %bb.0:482; CHECK-NEXT: sqdmullt z0.s, z0.h, z1.h483; CHECK-NEXT: ret484 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdmullt.nxv4i32(<vscale x 8 x i16> %a,485 <vscale x 8 x i16> %b)486 ret <vscale x 4 x i32> %out487}488 489define <vscale x 2 x i64> @sqdmullt_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {490; CHECK-LABEL: sqdmullt_s:491; CHECK: // %bb.0:492; CHECK-NEXT: sqdmullt z0.d, z0.s, z1.s493; CHECK-NEXT: ret494 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdmullt.nxv2i64(<vscale x 4 x i32> %a,495 <vscale x 4 x i32> %b)496 ret <vscale x 2 x i64> %out497}498 499;500; SQDMULLT (Indexed)501;502 503define <vscale x 4 x i32> @sqdmullt_lane_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {504; CHECK-LABEL: sqdmullt_lane_h:505; CHECK: // %bb.0:506; CHECK-NEXT: sqdmullt z0.s, z0.h, z1.h[3]507; CHECK-NEXT: ret508 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdmullt.lane.nxv4i32(<vscale x 8 x i16> %a,509 <vscale x 8 x i16> %b,510 i32 3)511 ret <vscale x 4 x i32> %out512}513 514define <vscale x 2 x i64> @sqdmullt_lane_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {515; CHECK-LABEL: sqdmullt_lane_s:516; CHECK: // %bb.0:517; CHECK-NEXT: sqdmullt z0.d, z0.s, z1.s[0]518; CHECK-NEXT: ret519 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdmullt.lane.nxv2i64(<vscale x 4 x i32> %a,520 <vscale x 4 x i32> %b,521 i32 0)522 ret <vscale x 2 x i64> %out523}524 525;526; SSUBLB527;528 529define <vscale x 8 x i16> @ssublb_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {530; CHECK-LABEL: ssublb_b:531; CHECK: // %bb.0:532; CHECK-NEXT: ssublb z0.h, z0.b, z1.b533; CHECK-NEXT: ret534 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.ssublb.nxv8i16(<vscale x 16 x i8> %a,535 <vscale x 16 x i8> %b)536 ret <vscale x 8 x i16> %out537}538 539define <vscale x 4 x i32> @ssublb_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {540; CHECK-LABEL: ssublb_h:541; CHECK: // %bb.0:542; CHECK-NEXT: ssublb z0.s, z0.h, z1.h543; CHECK-NEXT: ret544 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.ssublb.nxv4i32(<vscale x 8 x i16> %a,545 <vscale x 8 x i16> %b)546 ret <vscale x 4 x i32> %out547}548 549define <vscale x 2 x i64> @ssublb_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {550; CHECK-LABEL: ssublb_s:551; CHECK: // %bb.0:552; CHECK-NEXT: ssublb z0.d, z0.s, z1.s553; CHECK-NEXT: ret554 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.ssublb.nxv2i64(<vscale x 4 x i32> %a,555 <vscale x 4 x i32> %b)556 ret <vscale x 2 x i64> %out557}558 559;560; SSHLLB561;562 563define <vscale x 8 x i16> @sshllb_b(<vscale x 16 x i8> %a) {564; CHECK-LABEL: sshllb_b:565; CHECK: // %bb.0:566; CHECK-NEXT: sshllb z0.h, z0.b, #0567; CHECK-NEXT: ret568 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sshllb.nxv8i16(<vscale x 16 x i8> %a, i32 0)569 ret <vscale x 8 x i16> %out570}571 572define <vscale x 4 x i32> @sshllb_h(<vscale x 8 x i16> %a) {573; CHECK-LABEL: sshllb_h:574; CHECK: // %bb.0:575; CHECK-NEXT: sshllb z0.s, z0.h, #1576; CHECK-NEXT: ret577 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sshllb.nxv4i32(<vscale x 8 x i16> %a, i32 1)578 ret <vscale x 4 x i32> %out579}580 581define <vscale x 2 x i64> @sshllb_s(<vscale x 4 x i32> %a) {582; CHECK-LABEL: sshllb_s:583; CHECK: // %bb.0:584; CHECK-NEXT: sshllb z0.d, z0.s, #2585; CHECK-NEXT: ret586 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sshllb.nxv2i64(<vscale x 4 x i32> %a, i32 2)587 ret <vscale x 2 x i64> %out588}589 590;591; SSHLLT592;593 594define <vscale x 8 x i16> @sshllt_b(<vscale x 16 x i8> %a) {595; CHECK-LABEL: sshllt_b:596; CHECK: // %bb.0:597; CHECK-NEXT: sshllt z0.h, z0.b, #3598; CHECK-NEXT: ret599 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sshllt.nxv8i16(<vscale x 16 x i8> %a, i32 3)600 ret <vscale x 8 x i16> %out601}602 603define <vscale x 4 x i32> @sshllt_h(<vscale x 8 x i16> %a) {604; CHECK-LABEL: sshllt_h:605; CHECK: // %bb.0:606; CHECK-NEXT: sshllt z0.s, z0.h, #4607; CHECK-NEXT: ret608 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sshllt.nxv4i32(<vscale x 8 x i16> %a, i32 4)609 ret <vscale x 4 x i32> %out610}611 612define <vscale x 2 x i64> @sshllt_s(<vscale x 4 x i32> %a) {613; CHECK-LABEL: sshllt_s:614; CHECK: // %bb.0:615; CHECK-NEXT: sshllt z0.d, z0.s, #5616; CHECK-NEXT: ret617 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sshllt.nxv2i64(<vscale x 4 x i32> %a, i32 5)618 ret <vscale x 2 x i64> %out619}620 621;622; SSUBLT623;624 625define <vscale x 8 x i16> @ssublt_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {626; CHECK-LABEL: ssublt_b:627; CHECK: // %bb.0:628; CHECK-NEXT: ssublt z0.h, z0.b, z1.b629; CHECK-NEXT: ret630 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.ssublt.nxv8i16(<vscale x 16 x i8> %a,631 <vscale x 16 x i8> %b)632 ret <vscale x 8 x i16> %out633}634 635define <vscale x 4 x i32> @ssublt_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {636; CHECK-LABEL: ssublt_h:637; CHECK: // %bb.0:638; CHECK-NEXT: ssublt z0.s, z0.h, z1.h639; CHECK-NEXT: ret640 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.ssublt.nxv4i32(<vscale x 8 x i16> %a,641 <vscale x 8 x i16> %b)642 ret <vscale x 4 x i32> %out643}644 645define <vscale x 2 x i64> @ssublt_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {646; CHECK-LABEL: ssublt_s:647; CHECK: // %bb.0:648; CHECK-NEXT: ssublt z0.d, z0.s, z1.s649; CHECK-NEXT: ret650 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.ssublt.nxv2i64(<vscale x 4 x i32> %a,651 <vscale x 4 x i32> %b)652 ret <vscale x 2 x i64> %out653}654 655;656; SSUBWB657;658 659define <vscale x 8 x i16> @ssubwb_b(<vscale x 8 x i16> %a, <vscale x 16 x i8> %b) {660; CHECK-LABEL: ssubwb_b:661; CHECK: // %bb.0:662; CHECK-NEXT: ssubwb z0.h, z0.h, z1.b663; CHECK-NEXT: ret664 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.ssubwb.nxv8i16(<vscale x 8 x i16> %a,665 <vscale x 16 x i8> %b)666 ret <vscale x 8 x i16> %out667}668 669define <vscale x 4 x i32> @ssubwb_h(<vscale x 4 x i32> %a, <vscale x 8 x i16> %b) {670; CHECK-LABEL: ssubwb_h:671; CHECK: // %bb.0:672; CHECK-NEXT: ssubwb z0.s, z0.s, z1.h673; CHECK-NEXT: ret674 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.ssubwb.nxv4i32(<vscale x 4 x i32> %a,675 <vscale x 8 x i16> %b)676 ret <vscale x 4 x i32> %out677}678 679define <vscale x 2 x i64> @ssubwb_s(<vscale x 2 x i64> %a, <vscale x 4 x i32> %b) {680; CHECK-LABEL: ssubwb_s:681; CHECK: // %bb.0:682; CHECK-NEXT: ssubwb z0.d, z0.d, z1.s683; CHECK-NEXT: ret684 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.ssubwb.nxv2i64(<vscale x 2 x i64> %a,685 <vscale x 4 x i32> %b)686 ret <vscale x 2 x i64> %out687}688 689;690; SSUBWT691;692 693define <vscale x 8 x i16> @ssubwt_b(<vscale x 8 x i16> %a, <vscale x 16 x i8> %b) {694; CHECK-LABEL: ssubwt_b:695; CHECK: // %bb.0:696; CHECK-NEXT: ssubwt z0.h, z0.h, z1.b697; CHECK-NEXT: ret698 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.ssubwt.nxv8i16(<vscale x 8 x i16> %a,699 <vscale x 16 x i8> %b)700 ret <vscale x 8 x i16> %out701}702 703define <vscale x 4 x i32> @ssubwt_h(<vscale x 4 x i32> %a, <vscale x 8 x i16> %b) {704; CHECK-LABEL: ssubwt_h:705; CHECK: // %bb.0:706; CHECK-NEXT: ssubwt z0.s, z0.s, z1.h707; CHECK-NEXT: ret708 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.ssubwt.nxv4i32(<vscale x 4 x i32> %a,709 <vscale x 8 x i16> %b)710 ret <vscale x 4 x i32> %out711}712 713define <vscale x 2 x i64> @ssubwt_s(<vscale x 2 x i64> %a, <vscale x 4 x i32> %b) {714; CHECK-LABEL: ssubwt_s:715; CHECK: // %bb.0:716; CHECK-NEXT: ssubwt z0.d, z0.d, z1.s717; CHECK-NEXT: ret718 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.ssubwt.nxv2i64(<vscale x 2 x i64> %a,719 <vscale x 4 x i32> %b)720 ret <vscale x 2 x i64> %out721}722 723;724; UABALB725;726 727define <vscale x 8 x i16> @uabalb_b(<vscale x 8 x i16> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {728; CHECK-LABEL: uabalb_b:729; CHECK: // %bb.0:730; CHECK-NEXT: uabalb z0.h, z1.b, z2.b731; CHECK-NEXT: ret732 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uabalb.nxv8i16(<vscale x 8 x i16> %a,733 <vscale x 16 x i8> %b,734 <vscale x 16 x i8> %c)735 ret <vscale x 8 x i16> %out736}737 738define <vscale x 4 x i32> @uabalb_h(<vscale x 4 x i32> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {739; CHECK-LABEL: uabalb_h:740; CHECK: // %bb.0:741; CHECK-NEXT: uabalb z0.s, z1.h, z2.h742; CHECK-NEXT: ret743 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uabalb.nxv4i32(<vscale x 4 x i32> %a,744 <vscale x 8 x i16> %b,745 <vscale x 8 x i16> %c)746 ret <vscale x 4 x i32> %out747}748 749define <vscale x 2 x i64> @uabalb_s(<vscale x 2 x i64> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {750; CHECK-LABEL: uabalb_s:751; CHECK: // %bb.0:752; CHECK-NEXT: uabalb z0.d, z1.s, z2.s753; CHECK-NEXT: ret754 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uabalb.nxv2i64(<vscale x 2 x i64> %a,755 <vscale x 4 x i32> %b,756 <vscale x 4 x i32> %c)757 ret <vscale x 2 x i64> %out758}759 760;761; UABALT762;763 764define <vscale x 8 x i16> @uabalt_b(<vscale x 8 x i16> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {765; CHECK-LABEL: uabalt_b:766; CHECK: // %bb.0:767; CHECK-NEXT: uabalt z0.h, z1.b, z2.b768; CHECK-NEXT: ret769 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uabalt.nxv8i16(<vscale x 8 x i16> %a,770 <vscale x 16 x i8> %b,771 <vscale x 16 x i8> %c)772 ret <vscale x 8 x i16> %out773}774 775define <vscale x 4 x i32> @uabalt_h(<vscale x 4 x i32> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {776; CHECK-LABEL: uabalt_h:777; CHECK: // %bb.0:778; CHECK-NEXT: uabalt z0.s, z1.h, z2.h779; CHECK-NEXT: ret780 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uabalt.nxv4i32(<vscale x 4 x i32> %a,781 <vscale x 8 x i16> %b,782 <vscale x 8 x i16> %c)783 ret <vscale x 4 x i32> %out784}785 786define <vscale x 2 x i64> @uabalt_s(<vscale x 2 x i64> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {787; CHECK-LABEL: uabalt_s:788; CHECK: // %bb.0:789; CHECK-NEXT: uabalt z0.d, z1.s, z2.s790; CHECK-NEXT: ret791 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uabalt.nxv2i64(<vscale x 2 x i64> %a,792 <vscale x 4 x i32> %b,793 <vscale x 4 x i32> %c)794 ret <vscale x 2 x i64> %out795}796 797;798; UABDLB799;800 801define <vscale x 8 x i16> @uabdlb_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {802; CHECK-LABEL: uabdlb_b:803; CHECK: // %bb.0:804; CHECK-NEXT: uabdlb z0.h, z0.b, z1.b805; CHECK-NEXT: ret806 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uabdlb.nxv8i16(<vscale x 16 x i8> %a,807 <vscale x 16 x i8> %b)808 ret <vscale x 8 x i16> %out809}810 811define <vscale x 4 x i32> @uabdlb_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {812; CHECK-LABEL: uabdlb_h:813; CHECK: // %bb.0:814; CHECK-NEXT: uabdlb z0.s, z0.h, z1.h815; CHECK-NEXT: ret816 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uabdlb.nxv4i32(<vscale x 8 x i16> %a,817 <vscale x 8 x i16> %b)818 ret <vscale x 4 x i32> %out819}820 821define <vscale x 2 x i64> @uabdlb_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {822; CHECK-LABEL: uabdlb_s:823; CHECK: // %bb.0:824; CHECK-NEXT: uabdlb z0.d, z0.s, z1.s825; CHECK-NEXT: ret826 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uabdlb.nxv2i64(<vscale x 4 x i32> %a,827 <vscale x 4 x i32> %b)828 ret <vscale x 2 x i64> %out829}830 831;832; UABDLT833;834 835define <vscale x 8 x i16> @uabdlt_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {836; CHECK-LABEL: uabdlt_b:837; CHECK: // %bb.0:838; CHECK-NEXT: uabdlt z0.h, z0.b, z1.b839; CHECK-NEXT: ret840 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uabdlt.nxv8i16(<vscale x 16 x i8> %a,841 <vscale x 16 x i8> %b)842 ret <vscale x 8 x i16> %out843}844 845define <vscale x 4 x i32> @uabdlt_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {846; CHECK-LABEL: uabdlt_h:847; CHECK: // %bb.0:848; CHECK-NEXT: uabdlt z0.s, z0.h, z1.h849; CHECK-NEXT: ret850 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uabdlt.nxv4i32(<vscale x 8 x i16> %a,851 <vscale x 8 x i16> %b)852 ret <vscale x 4 x i32> %out853}854 855define <vscale x 2 x i64> @uabdlt_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {856; CHECK-LABEL: uabdlt_s:857; CHECK: // %bb.0:858; CHECK-NEXT: uabdlt z0.d, z0.s, z1.s859; CHECK-NEXT: ret860 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uabdlt.nxv2i64(<vscale x 4 x i32> %a,861 <vscale x 4 x i32> %b)862 ret <vscale x 2 x i64> %out863}864 865;866; UADDLB867;868 869define <vscale x 8 x i16> @uaddlb_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {870; CHECK-LABEL: uaddlb_b:871; CHECK: // %bb.0:872; CHECK-NEXT: uaddlb z0.h, z0.b, z1.b873; CHECK-NEXT: ret874 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uaddlb.nxv8i16(<vscale x 16 x i8> %a,875 <vscale x 16 x i8> %b)876 ret <vscale x 8 x i16> %out877}878 879define <vscale x 4 x i32> @uaddlb_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {880; CHECK-LABEL: uaddlb_h:881; CHECK: // %bb.0:882; CHECK-NEXT: uaddlb z0.s, z0.h, z1.h883; CHECK-NEXT: ret884 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uaddlb.nxv4i32(<vscale x 8 x i16> %a,885 <vscale x 8 x i16> %b)886 ret <vscale x 4 x i32> %out887}888 889define <vscale x 2 x i64> @uaddlb_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {890; CHECK-LABEL: uaddlb_s:891; CHECK: // %bb.0:892; CHECK-NEXT: uaddlb z0.d, z0.s, z1.s893; CHECK-NEXT: ret894 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uaddlb.nxv2i64(<vscale x 4 x i32> %a,895 <vscale x 4 x i32> %b)896 ret <vscale x 2 x i64> %out897}898 899;900; UADDLT901;902 903define <vscale x 8 x i16> @uaddlt_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {904; CHECK-LABEL: uaddlt_b:905; CHECK: // %bb.0:906; CHECK-NEXT: uaddlt z0.h, z0.b, z1.b907; CHECK-NEXT: ret908 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uaddlt.nxv8i16(<vscale x 16 x i8> %a,909 <vscale x 16 x i8> %b)910 ret <vscale x 8 x i16> %out911}912 913define <vscale x 4 x i32> @uaddlt_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {914; CHECK-LABEL: uaddlt_h:915; CHECK: // %bb.0:916; CHECK-NEXT: uaddlt z0.s, z0.h, z1.h917; CHECK-NEXT: ret918 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uaddlt.nxv4i32(<vscale x 8 x i16> %a,919 <vscale x 8 x i16> %b)920 ret <vscale x 4 x i32> %out921}922 923define <vscale x 2 x i64> @uaddlt_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {924; CHECK-LABEL: uaddlt_s:925; CHECK: // %bb.0:926; CHECK-NEXT: uaddlt z0.d, z0.s, z1.s927; CHECK-NEXT: ret928 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uaddlt.nxv2i64(<vscale x 4 x i32> %a,929 <vscale x 4 x i32> %b)930 ret <vscale x 2 x i64> %out931}932 933;934; UADDWB935;936 937define <vscale x 8 x i16> @uaddwb_b(<vscale x 8 x i16> %a, <vscale x 16 x i8> %b) {938; CHECK-LABEL: uaddwb_b:939; CHECK: // %bb.0:940; CHECK-NEXT: uaddwb z0.h, z0.h, z1.b941; CHECK-NEXT: ret942 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uaddwb.nxv8i16(<vscale x 8 x i16> %a,943 <vscale x 16 x i8> %b)944 ret <vscale x 8 x i16> %out945}946 947define <vscale x 4 x i32> @uaddwb_h(<vscale x 4 x i32> %a, <vscale x 8 x i16> %b) {948; CHECK-LABEL: uaddwb_h:949; CHECK: // %bb.0:950; CHECK-NEXT: uaddwb z0.s, z0.s, z1.h951; CHECK-NEXT: ret952 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uaddwb.nxv4i32(<vscale x 4 x i32> %a,953 <vscale x 8 x i16> %b)954 ret <vscale x 4 x i32> %out955}956 957define <vscale x 2 x i64> @uaddwb_s(<vscale x 2 x i64> %a, <vscale x 4 x i32> %b) {958; CHECK-LABEL: uaddwb_s:959; CHECK: // %bb.0:960; CHECK-NEXT: uaddwb z0.d, z0.d, z1.s961; CHECK-NEXT: ret962 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uaddwb.nxv2i64(<vscale x 2 x i64> %a,963 <vscale x 4 x i32> %b)964 ret <vscale x 2 x i64> %out965}966 967;968; UADDWT969;970 971define <vscale x 8 x i16> @uaddwt_b(<vscale x 8 x i16> %a, <vscale x 16 x i8> %b) {972; CHECK-LABEL: uaddwt_b:973; CHECK: // %bb.0:974; CHECK-NEXT: uaddwt z0.h, z0.h, z1.b975; CHECK-NEXT: ret976 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uaddwt.nxv8i16(<vscale x 8 x i16> %a,977 <vscale x 16 x i8> %b)978 ret <vscale x 8 x i16> %out979}980 981define <vscale x 4 x i32> @uaddwt_h(<vscale x 4 x i32> %a, <vscale x 8 x i16> %b) {982; CHECK-LABEL: uaddwt_h:983; CHECK: // %bb.0:984; CHECK-NEXT: uaddwt z0.s, z0.s, z1.h985; CHECK-NEXT: ret986 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uaddwt.nxv4i32(<vscale x 4 x i32> %a,987 <vscale x 8 x i16> %b)988 ret <vscale x 4 x i32> %out989}990 991define <vscale x 2 x i64> @uaddwt_s(<vscale x 2 x i64> %a, <vscale x 4 x i32> %b) {992; CHECK-LABEL: uaddwt_s:993; CHECK: // %bb.0:994; CHECK-NEXT: uaddwt z0.d, z0.d, z1.s995; CHECK-NEXT: ret996 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uaddwt.nxv2i64(<vscale x 2 x i64> %a,997 <vscale x 4 x i32> %b)998 ret <vscale x 2 x i64> %out999}1000 1001;1002; UMULLB (Vectors)1003;1004 1005define <vscale x 8 x i16> @umullb_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {1006; CHECK-LABEL: umullb_b:1007; CHECK: // %bb.0:1008; CHECK-NEXT: umullb z0.h, z0.b, z1.b1009; CHECK-NEXT: ret1010 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.umullb.nxv8i16(<vscale x 16 x i8> %a,1011 <vscale x 16 x i8> %b)1012 ret <vscale x 8 x i16> %out1013}1014 1015define <vscale x 4 x i32> @umullb_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {1016; CHECK-LABEL: umullb_h:1017; CHECK: // %bb.0:1018; CHECK-NEXT: umullb z0.s, z0.h, z1.h1019; CHECK-NEXT: ret1020 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.umullb.nxv4i32(<vscale x 8 x i16> %a,1021 <vscale x 8 x i16> %b)1022 ret <vscale x 4 x i32> %out1023}1024 1025define <vscale x 2 x i64> @umullb_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {1026; CHECK-LABEL: umullb_s:1027; CHECK: // %bb.0:1028; CHECK-NEXT: umullb z0.d, z0.s, z1.s1029; CHECK-NEXT: ret1030 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.umullb.nxv2i64(<vscale x 4 x i32> %a,1031 <vscale x 4 x i32> %b)1032 ret <vscale x 2 x i64> %out1033}1034 1035;1036; UMULLB (Indexed)1037;1038 1039define <vscale x 4 x i32> @umullb_lane_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {1040; CHECK-LABEL: umullb_lane_h:1041; CHECK: // %bb.0:1042; CHECK-NEXT: umullb z0.s, z0.h, z1.h[0]1043; CHECK-NEXT: ret1044 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.umullb.lane.nxv4i32(<vscale x 8 x i16> %a,1045 <vscale x 8 x i16> %b,1046 i32 0)1047 ret <vscale x 4 x i32> %out1048}1049 1050 1051define <vscale x 2 x i64> @umullb_lane_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {1052; CHECK-LABEL: umullb_lane_s:1053; CHECK: // %bb.0:1054; CHECK-NEXT: umullb z0.d, z0.s, z1.s[3]1055; CHECK-NEXT: ret1056 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.umullb.lane.nxv2i64(<vscale x 4 x i32> %a,1057 <vscale x 4 x i32> %b,1058 i32 3)1059 ret <vscale x 2 x i64> %out1060}1061 1062;1063; UMULLT (Vectors)1064;1065 1066define <vscale x 8 x i16> @umullt_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {1067; CHECK-LABEL: umullt_b:1068; CHECK: // %bb.0:1069; CHECK-NEXT: umullt z0.h, z0.b, z1.b1070; CHECK-NEXT: ret1071 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.umullt.nxv8i16(<vscale x 16 x i8> %a,1072 <vscale x 16 x i8> %b)1073 ret <vscale x 8 x i16> %out1074}1075 1076define <vscale x 4 x i32> @umullt_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {1077; CHECK-LABEL: umullt_h:1078; CHECK: // %bb.0:1079; CHECK-NEXT: umullt z0.s, z0.h, z1.h1080; CHECK-NEXT: ret1081 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.umullt.nxv4i32(<vscale x 8 x i16> %a,1082 <vscale x 8 x i16> %b)1083 ret <vscale x 4 x i32> %out1084}1085 1086define <vscale x 2 x i64> @umullt_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {1087; CHECK-LABEL: umullt_s:1088; CHECK: // %bb.0:1089; CHECK-NEXT: umullt z0.d, z0.s, z1.s1090; CHECK-NEXT: ret1091 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.umullt.nxv2i64(<vscale x 4 x i32> %a,1092 <vscale x 4 x i32> %b)1093 ret <vscale x 2 x i64> %out1094}1095 1096;1097; UMULLT (Indexed)1098;1099 1100define <vscale x 4 x i32> @umullt_lane_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {1101; CHECK-LABEL: umullt_lane_h:1102; CHECK: // %bb.0:1103; CHECK-NEXT: umullt z0.s, z0.h, z1.h[1]1104; CHECK-NEXT: ret1105 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.umullt.lane.nxv4i32(<vscale x 8 x i16> %a,1106 <vscale x 8 x i16> %b,1107 i32 1)1108 ret <vscale x 4 x i32> %out1109}1110 1111define <vscale x 2 x i64> @umullt_lane_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {1112; CHECK-LABEL: umullt_lane_s:1113; CHECK: // %bb.0:1114; CHECK-NEXT: umullt z0.d, z0.s, z1.s[2]1115; CHECK-NEXT: ret1116 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.umullt.lane.nxv2i64(<vscale x 4 x i32> %a,1117 <vscale x 4 x i32> %b,1118 i32 2)1119 ret <vscale x 2 x i64> %out1120}1121 1122;1123; USHLLB1124;1125 1126define <vscale x 8 x i16> @ushllb_b(<vscale x 16 x i8> %a) {1127; CHECK-LABEL: ushllb_b:1128; CHECK: // %bb.0:1129; CHECK-NEXT: ushllb z0.h, z0.b, #61130; CHECK-NEXT: ret1131 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.ushllb.nxv8i16(<vscale x 16 x i8> %a, i32 6)1132 ret <vscale x 8 x i16> %out1133}1134 1135define <vscale x 4 x i32> @ushllb_h(<vscale x 8 x i16> %a) {1136; CHECK-LABEL: ushllb_h:1137; CHECK: // %bb.0:1138; CHECK-NEXT: ushllb z0.s, z0.h, #71139; CHECK-NEXT: ret1140 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.ushllb.nxv4i32(<vscale x 8 x i16> %a, i32 7)1141 ret <vscale x 4 x i32> %out1142}1143 1144define <vscale x 2 x i64> @ushllb_s(<vscale x 4 x i32> %a) {1145; CHECK-LABEL: ushllb_s:1146; CHECK: // %bb.0:1147; CHECK-NEXT: ushllb z0.d, z0.s, #81148; CHECK-NEXT: ret1149 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.ushllb.nxv2i64(<vscale x 4 x i32> %a, i32 8)1150 ret <vscale x 2 x i64> %out1151}1152 1153;1154; USHLLT1155;1156 1157define <vscale x 8 x i16> @ushllt_b(<vscale x 16 x i8> %a) {1158; CHECK-LABEL: ushllt_b:1159; CHECK: // %bb.0:1160; CHECK-NEXT: ushllt z0.h, z0.b, #71161; CHECK-NEXT: ret1162 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.ushllt.nxv8i16(<vscale x 16 x i8> %a, i32 7)1163 ret <vscale x 8 x i16> %out1164}1165 1166define <vscale x 4 x i32> @ushllt_h(<vscale x 8 x i16> %a) {1167; CHECK-LABEL: ushllt_h:1168; CHECK: // %bb.0:1169; CHECK-NEXT: ushllt z0.s, z0.h, #151170; CHECK-NEXT: ret1171 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.ushllt.nxv4i32(<vscale x 8 x i16> %a, i32 15)1172 ret <vscale x 4 x i32> %out1173}1174 1175define <vscale x 2 x i64> @ushllt_s(<vscale x 4 x i32> %a) {1176; CHECK-LABEL: ushllt_s:1177; CHECK: // %bb.0:1178; CHECK-NEXT: ushllt z0.d, z0.s, #311179; CHECK-NEXT: ret1180 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.ushllt.nxv2i64(<vscale x 4 x i32> %a, i32 31)1181 ret <vscale x 2 x i64> %out1182}1183 1184;1185; USUBLB1186;1187 1188define <vscale x 8 x i16> @usublb_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {1189; CHECK-LABEL: usublb_b:1190; CHECK: // %bb.0:1191; CHECK-NEXT: usublb z0.h, z0.b, z1.b1192; CHECK-NEXT: ret1193 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.usublb.nxv8i16(<vscale x 16 x i8> %a,1194 <vscale x 16 x i8> %b)1195 ret <vscale x 8 x i16> %out1196}1197 1198define <vscale x 4 x i32> @usublb_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {1199; CHECK-LABEL: usublb_h:1200; CHECK: // %bb.0:1201; CHECK-NEXT: usublb z0.s, z0.h, z1.h1202; CHECK-NEXT: ret1203 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.usublb.nxv4i32(<vscale x 8 x i16> %a,1204 <vscale x 8 x i16> %b)1205 ret <vscale x 4 x i32> %out1206}1207 1208define <vscale x 2 x i64> @usublb_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {1209; CHECK-LABEL: usublb_s:1210; CHECK: // %bb.0:1211; CHECK-NEXT: usublb z0.d, z0.s, z1.s1212; CHECK-NEXT: ret1213 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.usublb.nxv2i64(<vscale x 4 x i32> %a,1214 <vscale x 4 x i32> %b)1215 ret <vscale x 2 x i64> %out1216}1217 1218;1219; USUBLT1220;1221 1222define <vscale x 8 x i16> @usublt_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {1223; CHECK-LABEL: usublt_b:1224; CHECK: // %bb.0:1225; CHECK-NEXT: usublt z0.h, z0.b, z1.b1226; CHECK-NEXT: ret1227 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.usublt.nxv8i16(<vscale x 16 x i8> %a,1228 <vscale x 16 x i8> %b)1229 ret <vscale x 8 x i16> %out1230}1231 1232define <vscale x 4 x i32> @usublt_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {1233; CHECK-LABEL: usublt_h:1234; CHECK: // %bb.0:1235; CHECK-NEXT: usublt z0.s, z0.h, z1.h1236; CHECK-NEXT: ret1237 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.usublt.nxv4i32(<vscale x 8 x i16> %a,1238 <vscale x 8 x i16> %b)1239 ret <vscale x 4 x i32> %out1240}1241 1242define <vscale x 2 x i64> @usublt_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {1243; CHECK-LABEL: usublt_s:1244; CHECK: // %bb.0:1245; CHECK-NEXT: usublt z0.d, z0.s, z1.s1246; CHECK-NEXT: ret1247 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.usublt.nxv2i64(<vscale x 4 x i32> %a,1248 <vscale x 4 x i32> %b)1249 ret <vscale x 2 x i64> %out1250}1251 1252;1253; USUBWB1254;1255 1256define <vscale x 8 x i16> @usubwb_b(<vscale x 8 x i16> %a, <vscale x 16 x i8> %b) {1257; CHECK-LABEL: usubwb_b:1258; CHECK: // %bb.0:1259; CHECK-NEXT: usubwb z0.h, z0.h, z1.b1260; CHECK-NEXT: ret1261 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.usubwb.nxv8i16(<vscale x 8 x i16> %a,1262 <vscale x 16 x i8> %b)1263 ret <vscale x 8 x i16> %out1264}1265 1266define <vscale x 4 x i32> @usubwb_h(<vscale x 4 x i32> %a, <vscale x 8 x i16> %b) {1267; CHECK-LABEL: usubwb_h:1268; CHECK: // %bb.0:1269; CHECK-NEXT: usubwb z0.s, z0.s, z1.h1270; CHECK-NEXT: ret1271 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.usubwb.nxv4i32(<vscale x 4 x i32> %a,1272 <vscale x 8 x i16> %b)1273 ret <vscale x 4 x i32> %out1274}1275 1276define <vscale x 2 x i64> @usubwb_s(<vscale x 2 x i64> %a, <vscale x 4 x i32> %b) {1277; CHECK-LABEL: usubwb_s:1278; CHECK: // %bb.0:1279; CHECK-NEXT: usubwb z0.d, z0.d, z1.s1280; CHECK-NEXT: ret1281 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.usubwb.nxv2i64(<vscale x 2 x i64> %a,1282 <vscale x 4 x i32> %b)1283 ret <vscale x 2 x i64> %out1284}1285 1286;1287; USUBWT1288;1289 1290define <vscale x 8 x i16> @usubwt_b(<vscale x 8 x i16> %a, <vscale x 16 x i8> %b) {1291; CHECK-LABEL: usubwt_b:1292; CHECK: // %bb.0:1293; CHECK-NEXT: usubwt z0.h, z0.h, z1.b1294; CHECK-NEXT: ret1295 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.usubwt.nxv8i16(<vscale x 8 x i16> %a,1296 <vscale x 16 x i8> %b)1297 ret <vscale x 8 x i16> %out1298}1299 1300define <vscale x 4 x i32> @usubwt_h(<vscale x 4 x i32> %a, <vscale x 8 x i16> %b) {1301; CHECK-LABEL: usubwt_h:1302; CHECK: // %bb.0:1303; CHECK-NEXT: usubwt z0.s, z0.s, z1.h1304; CHECK-NEXT: ret1305 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.usubwt.nxv4i32(<vscale x 4 x i32> %a,1306 <vscale x 8 x i16> %b)1307 ret <vscale x 4 x i32> %out1308}1309 1310define <vscale x 2 x i64> @usubwt_s(<vscale x 2 x i64> %a, <vscale x 4 x i32> %b) {1311; CHECK-LABEL: usubwt_s:1312; CHECK: // %bb.0:1313; CHECK-NEXT: usubwt z0.d, z0.d, z1.s1314; CHECK-NEXT: ret1315 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.usubwt.nxv2i64(<vscale x 2 x i64> %a,1316 <vscale x 4 x i32> %b)1317 ret <vscale x 2 x i64> %out1318}1319 1320declare <vscale x 8 x i16> @llvm.aarch64.sve.sabalb.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>)1321declare <vscale x 4 x i32> @llvm.aarch64.sve.sabalb.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>)1322declare <vscale x 2 x i64> @llvm.aarch64.sve.sabalb.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>)1323 1324declare <vscale x 8 x i16> @llvm.aarch64.sve.sabalt.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>)1325declare <vscale x 4 x i32> @llvm.aarch64.sve.sabalt.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>)1326declare <vscale x 2 x i64> @llvm.aarch64.sve.sabalt.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>)1327 1328declare <vscale x 8 x i16> @llvm.aarch64.sve.sabdlb.nxv8i16(<vscale x 16 x i8>, <vscale x 16 x i8>)1329declare <vscale x 4 x i32> @llvm.aarch64.sve.sabdlb.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>)1330declare <vscale x 2 x i64> @llvm.aarch64.sve.sabdlb.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>)1331 1332declare <vscale x 8 x i16> @llvm.aarch64.sve.sabdlt.nxv8i16(<vscale x 16 x i8>, <vscale x 16 x i8>)1333declare <vscale x 4 x i32> @llvm.aarch64.sve.sabdlt.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>)1334declare <vscale x 2 x i64> @llvm.aarch64.sve.sabdlt.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>)1335 1336declare <vscale x 8 x i16> @llvm.aarch64.sve.saddlb.nxv8i16(<vscale x 16 x i8>, <vscale x 16 x i8>)1337declare <vscale x 4 x i32> @llvm.aarch64.sve.saddlb.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>)1338declare <vscale x 2 x i64> @llvm.aarch64.sve.saddlb.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>)1339 1340declare <vscale x 8 x i16> @llvm.aarch64.sve.saddlt.nxv8i16(<vscale x 16 x i8>, <vscale x 16 x i8>)1341declare <vscale x 4 x i32> @llvm.aarch64.sve.saddlt.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>)1342declare <vscale x 2 x i64> @llvm.aarch64.sve.saddlt.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>)1343 1344declare <vscale x 8 x i16> @llvm.aarch64.sve.saddwb.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>)1345declare <vscale x 4 x i32> @llvm.aarch64.sve.saddwb.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>)1346declare <vscale x 2 x i64> @llvm.aarch64.sve.saddwb.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>)1347 1348declare <vscale x 8 x i16> @llvm.aarch64.sve.saddwt.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>)1349declare <vscale x 4 x i32> @llvm.aarch64.sve.saddwt.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>)1350declare <vscale x 2 x i64> @llvm.aarch64.sve.saddwt.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>)1351 1352declare <vscale x 8 x i16> @llvm.aarch64.sve.smullb.nxv8i16(<vscale x 16 x i8>, <vscale x 16 x i8>)1353declare <vscale x 4 x i32> @llvm.aarch64.sve.smullb.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>)1354declare <vscale x 2 x i64> @llvm.aarch64.sve.smullb.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>)1355 1356declare <vscale x 4 x i32> @llvm.aarch64.sve.smullb.lane.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>, i32)1357declare <vscale x 2 x i64> @llvm.aarch64.sve.smullb.lane.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32)1358 1359declare <vscale x 8 x i16> @llvm.aarch64.sve.smullt.nxv8i16(<vscale x 16 x i8>, <vscale x 16 x i8>)1360declare <vscale x 4 x i32> @llvm.aarch64.sve.smullt.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>)1361declare <vscale x 2 x i64> @llvm.aarch64.sve.smullt.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>)1362 1363declare <vscale x 4 x i32> @llvm.aarch64.sve.smullt.lane.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>, i32)1364declare <vscale x 2 x i64> @llvm.aarch64.sve.smullt.lane.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32)1365 1366declare <vscale x 8 x i16> @llvm.aarch64.sve.sqdmullb.nxv8i16(<vscale x 16 x i8>, <vscale x 16 x i8>)1367declare <vscale x 4 x i32> @llvm.aarch64.sve.sqdmullb.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>)1368declare <vscale x 2 x i64> @llvm.aarch64.sve.sqdmullb.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>)1369 1370declare <vscale x 4 x i32> @llvm.aarch64.sve.sqdmullb.lane.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>, i32)1371declare <vscale x 2 x i64> @llvm.aarch64.sve.sqdmullb.lane.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32)1372 1373declare <vscale x 8 x i16> @llvm.aarch64.sve.sqdmullt.nxv8i16(<vscale x 16 x i8>, <vscale x 16 x i8>)1374declare <vscale x 4 x i32> @llvm.aarch64.sve.sqdmullt.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>)1375declare <vscale x 2 x i64> @llvm.aarch64.sve.sqdmullt.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>)1376 1377declare <vscale x 4 x i32> @llvm.aarch64.sve.sqdmullt.lane.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>, i32)1378declare <vscale x 2 x i64> @llvm.aarch64.sve.sqdmullt.lane.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32)1379 1380declare <vscale x 8 x i16> @llvm.aarch64.sve.sshllb.nxv8i16(<vscale x 16 x i8>, i32)1381declare <vscale x 4 x i32> @llvm.aarch64.sve.sshllb.nxv4i32(<vscale x 8 x i16>, i32)1382declare <vscale x 2 x i64> @llvm.aarch64.sve.sshllb.nxv2i64(<vscale x 4 x i32>, i32)1383 1384declare <vscale x 8 x i16> @llvm.aarch64.sve.sshllt.nxv8i16(<vscale x 16 x i8>, i32)1385declare <vscale x 4 x i32> @llvm.aarch64.sve.sshllt.nxv4i32(<vscale x 8 x i16>, i32)1386declare <vscale x 2 x i64> @llvm.aarch64.sve.sshllt.nxv2i64(<vscale x 4 x i32>, i32)1387 1388declare <vscale x 8 x i16> @llvm.aarch64.sve.ssublb.nxv8i16(<vscale x 16 x i8>, <vscale x 16 x i8>)1389declare <vscale x 4 x i32> @llvm.aarch64.sve.ssublb.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>)1390declare <vscale x 2 x i64> @llvm.aarch64.sve.ssublb.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>)1391 1392declare <vscale x 8 x i16> @llvm.aarch64.sve.ssublt.nxv8i16(<vscale x 16 x i8>, <vscale x 16 x i8>)1393declare <vscale x 4 x i32> @llvm.aarch64.sve.ssublt.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>)1394declare <vscale x 2 x i64> @llvm.aarch64.sve.ssublt.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>)1395 1396declare <vscale x 8 x i16> @llvm.aarch64.sve.ssubwb.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>)1397declare <vscale x 4 x i32> @llvm.aarch64.sve.ssubwb.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>)1398declare <vscale x 2 x i64> @llvm.aarch64.sve.ssubwb.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>)1399 1400declare <vscale x 8 x i16> @llvm.aarch64.sve.ssubwt.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>)1401declare <vscale x 4 x i32> @llvm.aarch64.sve.ssubwt.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>)1402declare <vscale x 2 x i64> @llvm.aarch64.sve.ssubwt.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>)1403 1404declare <vscale x 8 x i16> @llvm.aarch64.sve.uabalb.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>)1405declare <vscale x 4 x i32> @llvm.aarch64.sve.uabalb.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>)1406declare <vscale x 2 x i64> @llvm.aarch64.sve.uabalb.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>)1407 1408declare <vscale x 8 x i16> @llvm.aarch64.sve.uabalt.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>)1409declare <vscale x 4 x i32> @llvm.aarch64.sve.uabalt.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>)1410declare <vscale x 2 x i64> @llvm.aarch64.sve.uabalt.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>)1411 1412declare <vscale x 8 x i16> @llvm.aarch64.sve.uabdlb.nxv8i16(<vscale x 16 x i8>, <vscale x 16 x i8>)1413declare <vscale x 4 x i32> @llvm.aarch64.sve.uabdlb.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>)1414declare <vscale x 2 x i64> @llvm.aarch64.sve.uabdlb.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>)1415 1416declare <vscale x 8 x i16> @llvm.aarch64.sve.uabdlt.nxv8i16(<vscale x 16 x i8>, <vscale x 16 x i8>)1417declare <vscale x 4 x i32> @llvm.aarch64.sve.uabdlt.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>)1418declare <vscale x 2 x i64> @llvm.aarch64.sve.uabdlt.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>)1419 1420declare <vscale x 8 x i16> @llvm.aarch64.sve.uaddlb.nxv8i16(<vscale x 16 x i8>, <vscale x 16 x i8>)1421declare <vscale x 4 x i32> @llvm.aarch64.sve.uaddlb.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>)1422declare <vscale x 2 x i64> @llvm.aarch64.sve.uaddlb.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>)1423 1424declare <vscale x 8 x i16> @llvm.aarch64.sve.uaddlt.nxv8i16(<vscale x 16 x i8>, <vscale x 16 x i8>)1425declare <vscale x 4 x i32> @llvm.aarch64.sve.uaddlt.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>)1426declare <vscale x 2 x i64> @llvm.aarch64.sve.uaddlt.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>)1427 1428declare <vscale x 8 x i16> @llvm.aarch64.sve.uaddwb.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>)1429declare <vscale x 4 x i32> @llvm.aarch64.sve.uaddwb.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>)1430declare <vscale x 2 x i64> @llvm.aarch64.sve.uaddwb.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>)1431 1432declare <vscale x 8 x i16> @llvm.aarch64.sve.uaddwt.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>)1433declare <vscale x 4 x i32> @llvm.aarch64.sve.uaddwt.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>)1434declare <vscale x 2 x i64> @llvm.aarch64.sve.uaddwt.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>)1435 1436declare <vscale x 8 x i16> @llvm.aarch64.sve.umullb.nxv8i16(<vscale x 16 x i8>, <vscale x 16 x i8>)1437declare <vscale x 4 x i32> @llvm.aarch64.sve.umullb.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>)1438declare <vscale x 2 x i64> @llvm.aarch64.sve.umullb.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>)1439 1440declare <vscale x 4 x i32> @llvm.aarch64.sve.umullb.lane.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>, i32)1441declare <vscale x 2 x i64> @llvm.aarch64.sve.umullb.lane.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32)1442 1443declare <vscale x 8 x i16> @llvm.aarch64.sve.umullt.nxv8i16(<vscale x 16 x i8>, <vscale x 16 x i8>)1444declare <vscale x 4 x i32> @llvm.aarch64.sve.umullt.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>)1445declare <vscale x 2 x i64> @llvm.aarch64.sve.umullt.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>)1446 1447declare <vscale x 4 x i32> @llvm.aarch64.sve.umullt.lane.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>, i32)1448declare <vscale x 2 x i64> @llvm.aarch64.sve.umullt.lane.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>, i32)1449 1450declare <vscale x 8 x i16> @llvm.aarch64.sve.ushllb.nxv8i16(<vscale x 16 x i8>, i32)1451declare <vscale x 4 x i32> @llvm.aarch64.sve.ushllb.nxv4i32(<vscale x 8 x i16>, i32)1452declare <vscale x 2 x i64> @llvm.aarch64.sve.ushllb.nxv2i64(<vscale x 4 x i32>, i32)1453 1454declare <vscale x 8 x i16> @llvm.aarch64.sve.ushllt.nxv8i16(<vscale x 16 x i8>, i32)1455declare <vscale x 4 x i32> @llvm.aarch64.sve.ushllt.nxv4i32(<vscale x 8 x i16>, i32)1456declare <vscale x 2 x i64> @llvm.aarch64.sve.ushllt.nxv2i64(<vscale x 4 x i32>, i32)1457 1458declare <vscale x 8 x i16> @llvm.aarch64.sve.usublb.nxv8i16(<vscale x 16 x i8>, <vscale x 16 x i8>)1459declare <vscale x 4 x i32> @llvm.aarch64.sve.usublb.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>)1460declare <vscale x 2 x i64> @llvm.aarch64.sve.usublb.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>)1461 1462declare <vscale x 8 x i16> @llvm.aarch64.sve.usublt.nxv8i16(<vscale x 16 x i8>, <vscale x 16 x i8>)1463declare <vscale x 4 x i32> @llvm.aarch64.sve.usublt.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>)1464declare <vscale x 2 x i64> @llvm.aarch64.sve.usublt.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>)1465 1466declare <vscale x 8 x i16> @llvm.aarch64.sve.usubwb.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>)1467declare <vscale x 4 x i32> @llvm.aarch64.sve.usubwb.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>)1468declare <vscale x 2 x i64> @llvm.aarch64.sve.usubwb.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>)1469 1470declare <vscale x 8 x i16> @llvm.aarch64.sve.usubwt.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>)1471declare <vscale x 4 x i32> @llvm.aarch64.sve.usubwt.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>)1472declare <vscale x 2 x i64> @llvm.aarch64.sve.usubwt.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>)1473