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1; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s2 3;4; SMLALB5;6define <vscale x 4 x i32> @smlalb_i32(<vscale x 4 x i32> %a,7 <vscale x 8 x i16> %b,8 <vscale x 8 x i16> %c) {9; CHECK-LABEL: smlalb_i3210; CHECK: smlalb z0.s, z1.h, z2.h[1]11; CHECK-NEXT: ret12 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.smlalb.lane.nxv4i32(<vscale x 4 x i32> %a,13 <vscale x 8 x i16> %b,14 <vscale x 8 x i16> %c,15 i32 1)16 ret <vscale x 4 x i32> %res17}18 19define <vscale x 4 x i32> @smlalb_i32_2(<vscale x 4 x i32> %a,20 <vscale x 8 x i16> %b,21 <vscale x 8 x i16> %c) {22; CHECK-LABEL: smlalb_i32_223; CHECK: smlalb z0.s, z1.h, z2.h[7]24; CHECK-NEXT: ret25 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.smlalb.lane.nxv4i32(<vscale x 4 x i32> %a,26 <vscale x 8 x i16> %b,27 <vscale x 8 x i16> %c,28 i32 7)29 ret <vscale x 4 x i32> %res30}31 32define <vscale x 2 x i64> @smlalb_i64(<vscale x 2 x i64> %a,33 <vscale x 4 x i32> %b,34 <vscale x 4 x i32> %c) {35; CHECK-LABEL: smlalb_i6436; CHECK: smlalb z0.d, z1.s, z2.s[0]37; CHECK-NEXT: ret38 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.smlalb.lane.nxv2i64(<vscale x 2 x i64> %a,39 <vscale x 4 x i32> %b,40 <vscale x 4 x i32> %c,41 i32 0)42 ret <vscale x 2 x i64> %res43}44 45define <vscale x 2 x i64> @smlalb_i64_2(<vscale x 2 x i64> %a,46 <vscale x 4 x i32> %b,47 <vscale x 4 x i32> %c) {48; CHECK-LABEL: smlalb_i64_249; CHECK: smlalb z0.d, z1.s, z2.s[3]50; CHECK-NEXT: ret51 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.smlalb.lane.nxv2i64(<vscale x 2 x i64> %a,52 <vscale x 4 x i32> %b,53 <vscale x 4 x i32> %c,54 i32 3)55 ret <vscale x 2 x i64> %res56}57 58;59; SMLALT60;61define <vscale x 4 x i32> @smlalt_i32(<vscale x 4 x i32> %a,62 <vscale x 8 x i16> %b,63 <vscale x 8 x i16> %c) {64; CHECK-LABEL: smlalt_i3265; CHECK: smlalt z0.s, z1.h, z2.h[1]66; CHECK-NEXT: ret67 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.smlalt.lane.nxv4i32(<vscale x 4 x i32> %a,68 <vscale x 8 x i16> %b,69 <vscale x 8 x i16> %c,70 i32 1)71 ret <vscale x 4 x i32> %res72}73 74define <vscale x 4 x i32> @smlalt_i32_2(<vscale x 4 x i32> %a,75 <vscale x 8 x i16> %b,76 <vscale x 8 x i16> %c) {77; CHECK-LABEL: smlalt_i32_278; CHECK: smlalt z0.s, z1.h, z2.h[7]79; CHECK-NEXT: ret80 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.smlalt.lane.nxv4i32(<vscale x 4 x i32> %a,81 <vscale x 8 x i16> %b,82 <vscale x 8 x i16> %c,83 i32 7)84 ret <vscale x 4 x i32> %res85}86 87define <vscale x 2 x i64> @smlalt_i64(<vscale x 2 x i64> %a,88 <vscale x 4 x i32> %b,89 <vscale x 4 x i32> %c) {90; CHECK-LABEL: smlalt_i6491; CHECK: smlalt z0.d, z1.s, z2.s[0]92; CHECK-NEXT: ret93 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.smlalt.lane.nxv2i64(<vscale x 2 x i64> %a,94 <vscale x 4 x i32> %b,95 <vscale x 4 x i32> %c,96 i32 0)97 ret <vscale x 2 x i64> %res98}99 100define <vscale x 2 x i64> @smlalt_i64_2(<vscale x 2 x i64> %a,101 <vscale x 4 x i32> %b,102 <vscale x 4 x i32> %c) {103; CHECK-LABEL: smlalt_i64_2104; CHECK: smlalt z0.d, z1.s, z2.s[3]105; CHECK-NEXT: ret106 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.smlalt.lane.nxv2i64(<vscale x 2 x i64> %a,107 <vscale x 4 x i32> %b,108 <vscale x 4 x i32> %c,109 i32 3)110 ret <vscale x 2 x i64> %res111}112 113;114; UMLALB115;116define <vscale x 4 x i32> @umlalb_i32(<vscale x 4 x i32> %a,117 <vscale x 8 x i16> %b,118 <vscale x 8 x i16> %c) {119; CHECK-LABEL: umlalb_i32120; CHECK: umlalb z0.s, z1.h, z2.h[1]121; CHECK-NEXT: ret122 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.umlalb.lane.nxv4i32(<vscale x 4 x i32> %a,123 <vscale x 8 x i16> %b,124 <vscale x 8 x i16> %c,125 i32 1)126 ret <vscale x 4 x i32> %res127}128 129define <vscale x 4 x i32> @umlalb_i32_2(<vscale x 4 x i32> %a,130 <vscale x 8 x i16> %b,131 <vscale x 8 x i16> %c) {132; CHECK-LABEL: umlalb_i32_2133; CHECK: umlalb z0.s, z1.h, z2.h[7]134; CHECK-NEXT: ret135 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.umlalb.lane.nxv4i32(<vscale x 4 x i32> %a,136 <vscale x 8 x i16> %b,137 <vscale x 8 x i16> %c,138 i32 7)139 ret <vscale x 4 x i32> %res140}141 142define <vscale x 2 x i64> @umlalb_i64(<vscale x 2 x i64> %a,143 <vscale x 4 x i32> %b,144 <vscale x 4 x i32> %c) {145; CHECK-LABEL: umlalb_i64146; CHECK: umlalb z0.d, z1.s, z2.s[0]147; CHECK-NEXT: ret148 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.umlalb.lane.nxv2i64(<vscale x 2 x i64> %a,149 <vscale x 4 x i32> %b,150 <vscale x 4 x i32> %c,151 i32 0)152 ret <vscale x 2 x i64> %res153}154 155define <vscale x 2 x i64> @umlalb_i64_2(<vscale x 2 x i64> %a,156 <vscale x 4 x i32> %b,157 <vscale x 4 x i32> %c) {158; CHECK-LABEL: umlalb_i64_2159; CHECK: umlalb z0.d, z1.s, z2.s[3]160; CHECK-NEXT: ret161 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.umlalb.lane.nxv2i64(<vscale x 2 x i64> %a,162 <vscale x 4 x i32> %b,163 <vscale x 4 x i32> %c,164 i32 3)165 ret <vscale x 2 x i64> %res166}167 168;169; UMLALT170;171define <vscale x 4 x i32> @umlalt_i32(<vscale x 4 x i32> %a,172 <vscale x 8 x i16> %b,173 <vscale x 8 x i16> %c) {174; CHECK-LABEL: umlalt_i32175; CHECK: umlalt z0.s, z1.h, z2.h[1]176; CHECK-NEXT: ret177 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.umlalt.lane.nxv4i32(<vscale x 4 x i32> %a,178 <vscale x 8 x i16> %b,179 <vscale x 8 x i16> %c,180 i32 1)181 ret <vscale x 4 x i32> %res182}183 184define <vscale x 4 x i32> @umlalt_i32_2(<vscale x 4 x i32> %a,185 <vscale x 8 x i16> %b,186 <vscale x 8 x i16> %c) {187; CHECK-LABEL: umlalt_i32_2188; CHECK: umlalt z0.s, z1.h, z2.h[7]189; CHECK-NEXT: ret190 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.umlalt.lane.nxv4i32(<vscale x 4 x i32> %a,191 <vscale x 8 x i16> %b,192 <vscale x 8 x i16> %c,193 i32 7)194 ret <vscale x 4 x i32> %res195}196 197define <vscale x 2 x i64> @umlalt_i64(<vscale x 2 x i64> %a,198 <vscale x 4 x i32> %b,199 <vscale x 4 x i32> %c) {200; CHECK-LABEL: umlalt_i64201; CHECK: umlalt z0.d, z1.s, z2.s[0]202; CHECK-NEXT: ret203 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.umlalt.lane.nxv2i64(<vscale x 2 x i64> %a,204 <vscale x 4 x i32> %b,205 <vscale x 4 x i32> %c,206 i32 0)207 ret <vscale x 2 x i64> %res208}209 210define <vscale x 2 x i64> @umlalt_i64_2(<vscale x 2 x i64> %a,211 <vscale x 4 x i32> %b,212 <vscale x 4 x i32> %c) {213; CHECK-LABEL: umlalt_i64_2214; CHECK: umlalt z0.d, z1.s, z2.s[3]215; CHECK-NEXT: ret216 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.umlalt.lane.nxv2i64(<vscale x 2 x i64> %a,217 <vscale x 4 x i32> %b,218 <vscale x 4 x i32> %c,219 i32 3)220 ret <vscale x 2 x i64> %res221}222 223;224; SMLSLB225;226define <vscale x 4 x i32> @smlslb_i32(<vscale x 4 x i32> %a,227 <vscale x 8 x i16> %b,228 <vscale x 8 x i16> %c) {229; CHECK-LABEL: smlslb_i32230; CHECK: smlslb z0.s, z1.h, z2.h[1]231; CHECK-NEXT: ret232 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.smlslb.lane.nxv4i32(<vscale x 4 x i32> %a,233 <vscale x 8 x i16> %b,234 <vscale x 8 x i16> %c,235 i32 1)236 ret <vscale x 4 x i32> %res237}238 239define <vscale x 4 x i32> @smlslb_i32_2(<vscale x 4 x i32> %a,240 <vscale x 8 x i16> %b,241 <vscale x 8 x i16> %c) {242; CHECK-LABEL: smlslb_i32_2243; CHECK: smlslb z0.s, z1.h, z2.h[7]244; CHECK-NEXT: ret245 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.smlslb.lane.nxv4i32(<vscale x 4 x i32> %a,246 <vscale x 8 x i16> %b,247 <vscale x 8 x i16> %c,248 i32 7)249 ret <vscale x 4 x i32> %res250}251 252define <vscale x 2 x i64> @smlslb_i64(<vscale x 2 x i64> %a,253 <vscale x 4 x i32> %b,254 <vscale x 4 x i32> %c) {255; CHECK-LABEL: smlslb_i64256; CHECK: smlslb z0.d, z1.s, z2.s[0]257; CHECK-NEXT: ret258 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.smlslb.lane.nxv2i64(<vscale x 2 x i64> %a,259 <vscale x 4 x i32> %b,260 <vscale x 4 x i32> %c,261 i32 0)262 ret <vscale x 2 x i64> %res263}264 265define <vscale x 2 x i64> @smlslb_i64_2(<vscale x 2 x i64> %a,266 <vscale x 4 x i32> %b,267 <vscale x 4 x i32> %c) {268; CHECK-LABEL: smlslb_i64_2269; CHECK: smlslb z0.d, z1.s, z2.s[3]270; CHECK-NEXT: ret271 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.smlslb.lane.nxv2i64(<vscale x 2 x i64> %a,272 <vscale x 4 x i32> %b,273 <vscale x 4 x i32> %c,274 i32 3)275 ret <vscale x 2 x i64> %res276}277 278;279; SMLSLT280;281define <vscale x 4 x i32> @smlslt_i32(<vscale x 4 x i32> %a,282 <vscale x 8 x i16> %b,283 <vscale x 8 x i16> %c) {284; CHECK-LABEL: smlslt_i32285; CHECK: smlslt z0.s, z1.h, z2.h[1]286; CHECK-NEXT: ret287 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.smlslt.lane.nxv4i32(<vscale x 4 x i32> %a,288 <vscale x 8 x i16> %b,289 <vscale x 8 x i16> %c,290 i32 1)291 ret <vscale x 4 x i32> %res292}293 294define <vscale x 4 x i32> @smlslt_i32_2(<vscale x 4 x i32> %a,295 <vscale x 8 x i16> %b,296 <vscale x 8 x i16> %c) {297; CHECK-LABEL: smlslt_i32_2298; CHECK: smlslt z0.s, z1.h, z2.h[7]299; CHECK-NEXT: ret300 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.smlslt.lane.nxv4i32(<vscale x 4 x i32> %a,301 <vscale x 8 x i16> %b,302 <vscale x 8 x i16> %c,303 i32 7)304 ret <vscale x 4 x i32> %res305}306 307define <vscale x 2 x i64> @smlslt_i64(<vscale x 2 x i64> %a,308 <vscale x 4 x i32> %b,309 <vscale x 4 x i32> %c) {310; CHECK-LABEL: smlslt_i64311; CHECK: smlslt z0.d, z1.s, z2.s[0]312; CHECK-NEXT: ret313 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.smlslt.lane.nxv2i64(<vscale x 2 x i64> %a,314 <vscale x 4 x i32> %b,315 <vscale x 4 x i32> %c,316 i32 0)317 ret <vscale x 2 x i64> %res318}319 320define <vscale x 2 x i64> @smlslt_i64_2(<vscale x 2 x i64> %a,321 <vscale x 4 x i32> %b,322 <vscale x 4 x i32> %c) {323; CHECK-LABEL: smlslt_i64_2324; CHECK: smlslt z0.d, z1.s, z2.s[3]325; CHECK-NEXT: ret326 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.smlslt.lane.nxv2i64(<vscale x 2 x i64> %a,327 <vscale x 4 x i32> %b,328 <vscale x 4 x i32> %c,329 i32 3)330 ret <vscale x 2 x i64> %res331}332 333;334; UMLSLB335;336define <vscale x 4 x i32> @umlslb_i32(<vscale x 4 x i32> %a,337 <vscale x 8 x i16> %b,338 <vscale x 8 x i16> %c) {339; CHECK-LABEL: umlslb_i32340; CHECK: umlslb z0.s, z1.h, z2.h[1]341; CHECK-NEXT: ret342 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.umlslb.lane.nxv4i32(<vscale x 4 x i32> %a,343 <vscale x 8 x i16> %b,344 <vscale x 8 x i16> %c,345 i32 1)346 ret <vscale x 4 x i32> %res347}348 349define <vscale x 4 x i32> @umlslb_i32_2(<vscale x 4 x i32> %a,350 <vscale x 8 x i16> %b,351 <vscale x 8 x i16> %c) {352; CHECK-LABEL: umlslb_i32_2353; CHECK: umlslb z0.s, z1.h, z2.h[7]354; CHECK-NEXT: ret355 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.umlslb.lane.nxv4i32(<vscale x 4 x i32> %a,356 <vscale x 8 x i16> %b,357 <vscale x 8 x i16> %c,358 i32 7)359 ret <vscale x 4 x i32> %res360}361 362define <vscale x 2 x i64> @umlslb_i64(<vscale x 2 x i64> %a,363 <vscale x 4 x i32> %b,364 <vscale x 4 x i32> %c) {365; CHECK-LABEL: umlslb_i64366; CHECK: umlslb z0.d, z1.s, z2.s[0]367; CHECK-NEXT: ret368 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.umlslb.lane.nxv2i64(<vscale x 2 x i64> %a,369 <vscale x 4 x i32> %b,370 <vscale x 4 x i32> %c,371 i32 0)372 ret <vscale x 2 x i64> %res373}374 375define <vscale x 2 x i64> @umlslb_i64_2(<vscale x 2 x i64> %a,376 <vscale x 4 x i32> %b,377 <vscale x 4 x i32> %c) {378; CHECK-LABEL: umlslb_i64_2379; CHECK: umlslb z0.d, z1.s, z2.s[3]380; CHECK-NEXT: ret381 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.umlslb.lane.nxv2i64(<vscale x 2 x i64> %a,382 <vscale x 4 x i32> %b,383 <vscale x 4 x i32> %c,384 i32 3)385 ret <vscale x 2 x i64> %res386}387 388;389; UMLSLT390;391define <vscale x 4 x i32> @umlslt_i32(<vscale x 4 x i32> %a,392 <vscale x 8 x i16> %b,393 <vscale x 8 x i16> %c) {394; CHECK-LABEL: umlslt_i32395; CHECK: umlslt z0.s, z1.h, z2.h[1]396; CHECK-NEXT: ret397 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.umlslt.lane.nxv4i32(<vscale x 4 x i32> %a,398 <vscale x 8 x i16> %b,399 <vscale x 8 x i16> %c,400 i32 1)401 ret <vscale x 4 x i32> %res402}403 404define <vscale x 4 x i32> @umlslt_i32_2(<vscale x 4 x i32> %a,405 <vscale x 8 x i16> %b,406 <vscale x 8 x i16> %c) {407; CHECK-LABEL: umlslt_i32_2408; CHECK: umlslt z0.s, z1.h, z2.h[7]409; CHECK-NEXT: ret410 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.umlslt.lane.nxv4i32(<vscale x 4 x i32> %a,411 <vscale x 8 x i16> %b,412 <vscale x 8 x i16> %c,413 i32 7)414 ret <vscale x 4 x i32> %res415}416 417define <vscale x 2 x i64> @umlslt_i64(<vscale x 2 x i64> %a,418 <vscale x 4 x i32> %b,419 <vscale x 4 x i32> %c) {420; CHECK-LABEL: umlslt_i64421; CHECK: umlslt z0.d, z1.s, z2.s[0]422; CHECK-NEXT: ret423 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.umlslt.lane.nxv2i64(<vscale x 2 x i64> %a,424 <vscale x 4 x i32> %b,425 <vscale x 4 x i32> %c,426 i32 0)427 ret <vscale x 2 x i64> %res428}429 430define <vscale x 2 x i64> @umlslt_i64_2(<vscale x 2 x i64> %a,431 <vscale x 4 x i32> %b,432 <vscale x 4 x i32> %c) {433; CHECK-LABEL: umlslt_i64_2434; CHECK: umlslt z0.d, z1.s, z2.s[3]435; CHECK-NEXT: ret436 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.umlslt.lane.nxv2i64(<vscale x 2 x i64> %a,437 <vscale x 4 x i32> %b,438 <vscale x 4 x i32> %c,439 i32 3)440 ret <vscale x 2 x i64> %res441}442 443;444; SQDMLALB445;446define <vscale x 4 x i32> @sqdmlalb_i32(<vscale x 4 x i32> %a,447 <vscale x 8 x i16> %b,448 <vscale x 8 x i16> %c) {449; CHECK-LABEL: sqdmlalb_i32450; CHECK: sqdmlalb z0.s, z1.h, z2.h[1]451; CHECK-NEXT: ret452 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlalb.lane.nxv4i32(<vscale x 4 x i32> %a,453 <vscale x 8 x i16> %b,454 <vscale x 8 x i16> %c,455 i32 1)456 ret <vscale x 4 x i32> %res457}458 459define <vscale x 4 x i32> @sqdmlalb_i32_2(<vscale x 4 x i32> %a,460 <vscale x 8 x i16> %b,461 <vscale x 8 x i16> %c) {462; CHECK-LABEL: sqdmlalb_i32_2463; CHECK: sqdmlalb z0.s, z1.h, z2.h[7]464; CHECK-NEXT: ret465 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlalb.lane.nxv4i32(<vscale x 4 x i32> %a,466 <vscale x 8 x i16> %b,467 <vscale x 8 x i16> %c,468 i32 7)469 ret <vscale x 4 x i32> %res470}471 472define <vscale x 2 x i64> @sqdmlalb_i64(<vscale x 2 x i64> %a,473 <vscale x 4 x i32> %b,474 <vscale x 4 x i32> %c) {475; CHECK-LABEL: sqdmlalb_i64476; CHECK: sqdmlalb z0.d, z1.s, z2.s[0]477; CHECK-NEXT: ret478 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlalb.lane.nxv2i64(<vscale x 2 x i64> %a,479 <vscale x 4 x i32> %b,480 <vscale x 4 x i32> %c,481 i32 0)482 ret <vscale x 2 x i64> %res483}484 485define <vscale x 2 x i64> @sqdmlalb_i64_2(<vscale x 2 x i64> %a,486 <vscale x 4 x i32> %b,487 <vscale x 4 x i32> %c) {488; CHECK-LABEL: sqdmlalb_i64_2489; CHECK: sqdmlalb z0.d, z1.s, z2.s[3]490; CHECK-NEXT: ret491 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlalb.lane.nxv2i64(<vscale x 2 x i64> %a,492 <vscale x 4 x i32> %b,493 <vscale x 4 x i32> %c,494 i32 3)495 ret <vscale x 2 x i64> %res496}497 498;499; SQDMLALT500;501define <vscale x 4 x i32> @sqdmlalt_i32(<vscale x 4 x i32> %a,502 <vscale x 8 x i16> %b,503 <vscale x 8 x i16> %c) {504; CHECK-LABEL: sqdmlalt_i32505; CHECK: sqdmlalt z0.s, z1.h, z2.h[1]506; CHECK-NEXT: ret507 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlalt.lane.nxv4i32(<vscale x 4 x i32> %a,508 <vscale x 8 x i16> %b,509 <vscale x 8 x i16> %c,510 i32 1)511 ret <vscale x 4 x i32> %res512}513 514define <vscale x 4 x i32> @sqdmlalt_i32_2(<vscale x 4 x i32> %a,515 <vscale x 8 x i16> %b,516 <vscale x 8 x i16> %c) {517; CHECK-LABEL: sqdmlalt_i32_2518; CHECK: sqdmlalt z0.s, z1.h, z2.h[7]519; CHECK-NEXT: ret520 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlalt.lane.nxv4i32(<vscale x 4 x i32> %a,521 <vscale x 8 x i16> %b,522 <vscale x 8 x i16> %c,523 i32 7)524 ret <vscale x 4 x i32> %res525}526 527define <vscale x 2 x i64> @sqdmlalt_i64(<vscale x 2 x i64> %a,528 <vscale x 4 x i32> %b,529 <vscale x 4 x i32> %c) {530; CHECK-LABEL: sqdmlalt_i64531; CHECK: sqdmlalt z0.d, z1.s, z2.s[0]532; CHECK-NEXT: ret533 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlalt.lane.nxv2i64(<vscale x 2 x i64> %a,534 <vscale x 4 x i32> %b,535 <vscale x 4 x i32> %c,536 i32 0)537 ret <vscale x 2 x i64> %res538}539 540define <vscale x 2 x i64> @sqdmlalt_i64_2(<vscale x 2 x i64> %a,541 <vscale x 4 x i32> %b,542 <vscale x 4 x i32> %c) {543; CHECK-LABEL: sqdmlalt_i64_2544; CHECK: sqdmlalt z0.d, z1.s, z2.s[3]545; CHECK-NEXT: ret546 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlalt.lane.nxv2i64(<vscale x 2 x i64> %a,547 <vscale x 4 x i32> %b,548 <vscale x 4 x i32> %c,549 i32 3)550 ret <vscale x 2 x i64> %res551}552 553;554; SQDMLSLB555;556define <vscale x 4 x i32> @sqdmlslb_i32(<vscale x 4 x i32> %a,557 <vscale x 8 x i16> %b,558 <vscale x 8 x i16> %c) {559; CHECK-LABEL: sqdmlslb_i32560; CHECK: sqdmlslb z0.s, z1.h, z2.h[1]561; CHECK-NEXT: ret562 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlslb.lane.nxv4i32(<vscale x 4 x i32> %a,563 <vscale x 8 x i16> %b,564 <vscale x 8 x i16> %c,565 i32 1)566 ret <vscale x 4 x i32> %res567}568 569define <vscale x 4 x i32> @sqdmlslb_i32_2(<vscale x 4 x i32> %a,570 <vscale x 8 x i16> %b,571 <vscale x 8 x i16> %c) {572; CHECK-LABEL: sqdmlslb_i32_2573; CHECK: sqdmlslb z0.s, z1.h, z2.h[7]574; CHECK-NEXT: ret575 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlslb.lane.nxv4i32(<vscale x 4 x i32> %a,576 <vscale x 8 x i16> %b,577 <vscale x 8 x i16> %c,578 i32 7)579 ret <vscale x 4 x i32> %res580}581 582define <vscale x 2 x i64> @sqdmlslb_i64(<vscale x 2 x i64> %a,583 <vscale x 4 x i32> %b,584 <vscale x 4 x i32> %c) {585; CHECK-LABEL: sqdmlslb_i64586; CHECK: sqdmlslb z0.d, z1.s, z2.s[0]587; CHECK-NEXT: ret588 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlslb.lane.nxv2i64(<vscale x 2 x i64> %a,589 <vscale x 4 x i32> %b,590 <vscale x 4 x i32> %c,591 i32 0)592 ret <vscale x 2 x i64> %res593}594 595define <vscale x 2 x i64> @sqdmlslb_i64_2(<vscale x 2 x i64> %a,596 <vscale x 4 x i32> %b,597 <vscale x 4 x i32> %c) {598; CHECK-LABEL: sqdmlslb_i64_2599; CHECK: sqdmlslb z0.d, z1.s, z2.s[3]600; CHECK-NEXT: ret601 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlslb.lane.nxv2i64(<vscale x 2 x i64> %a,602 <vscale x 4 x i32> %b,603 <vscale x 4 x i32> %c,604 i32 3)605 ret <vscale x 2 x i64> %res606}607 608;609; SQDMLSLT610;611define <vscale x 4 x i32> @sqdmlslt_i32(<vscale x 4 x i32> %a,612 <vscale x 8 x i16> %b,613 <vscale x 8 x i16> %c) {614; CHECK-LABEL: sqdmlslt_i32615; CHECK: sqdmlslt z0.s, z1.h, z2.h[1]616; CHECK-NEXT: ret617 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlslt.lane.nxv4i32(<vscale x 4 x i32> %a,618 <vscale x 8 x i16> %b,619 <vscale x 8 x i16> %c,620 i32 1)621 ret <vscale x 4 x i32> %res622}623 624define <vscale x 4 x i32> @sqdmlslt_i32_2(<vscale x 4 x i32> %a,625 <vscale x 8 x i16> %b,626 <vscale x 8 x i16> %c) {627; CHECK-LABEL: sqdmlslt_i32_2628; CHECK: sqdmlslt z0.s, z1.h, z2.h[7]629; CHECK-NEXT: ret630 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlslt.lane.nxv4i32(<vscale x 4 x i32> %a,631 <vscale x 8 x i16> %b,632 <vscale x 8 x i16> %c,633 i32 7)634 ret <vscale x 4 x i32> %res635}636 637define <vscale x 2 x i64> @sqdmlslt_i64(<vscale x 2 x i64> %a,638 <vscale x 4 x i32> %b,639 <vscale x 4 x i32> %c) {640; CHECK-LABEL: sqdmlslt_i64641; CHECK: sqdmlslt z0.d, z1.s, z2.s[0]642; CHECK-NEXT: ret643 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlslt.lane.nxv2i64(<vscale x 2 x i64> %a,644 <vscale x 4 x i32> %b,645 <vscale x 4 x i32> %c,646 i32 0)647 ret <vscale x 2 x i64> %res648}649 650define <vscale x 2 x i64> @sqdmlslt_i64_2(<vscale x 2 x i64> %a,651 <vscale x 4 x i32> %b,652 <vscale x 4 x i32> %c) {653; CHECK-LABEL: sqdmlslt_i64_2654; CHECK: sqdmlslt z0.d, z1.s, z2.s[3]655; CHECK-NEXT: ret656 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlslt.lane.nxv2i64(<vscale x 2 x i64> %a,657 <vscale x 4 x i32> %b,658 <vscale x 4 x i32> %c,659 i32 3)660 ret <vscale x 2 x i64> %res661}662 663declare <vscale x 4 x i32> @llvm.aarch64.sve.smlalb.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32)664declare <vscale x 2 x i64> @llvm.aarch64.sve.smlalb.lane.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>, i32)665declare <vscale x 4 x i32> @llvm.aarch64.sve.smlalt.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32)666declare <vscale x 2 x i64> @llvm.aarch64.sve.smlalt.lane.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>, i32)667declare <vscale x 4 x i32> @llvm.aarch64.sve.umlalb.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32)668declare <vscale x 2 x i64> @llvm.aarch64.sve.umlalb.lane.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>, i32)669declare <vscale x 4 x i32> @llvm.aarch64.sve.umlalt.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32)670declare <vscale x 2 x i64> @llvm.aarch64.sve.umlalt.lane.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>, i32)671declare <vscale x 4 x i32> @llvm.aarch64.sve.smlslb.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32)672declare <vscale x 2 x i64> @llvm.aarch64.sve.smlslb.lane.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>, i32)673declare <vscale x 4 x i32> @llvm.aarch64.sve.smlslt.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32)674declare <vscale x 2 x i64> @llvm.aarch64.sve.smlslt.lane.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>, i32)675declare <vscale x 4 x i32> @llvm.aarch64.sve.umlslb.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32)676declare <vscale x 2 x i64> @llvm.aarch64.sve.umlslb.lane.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>, i32)677declare <vscale x 4 x i32> @llvm.aarch64.sve.umlslt.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32)678declare <vscale x 2 x i64> @llvm.aarch64.sve.umlslt.lane.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>, i32)679declare <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlalb.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32)680declare <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlalb.lane.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>, i32)681declare <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlalt.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32)682declare <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlalt.lane.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>, i32)683declare <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlslb.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32)684declare <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlslb.lane.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>, i32)685declare <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlslt.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32)686declare <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlslt.lane.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>, i32)687