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1; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s2 3;4; SMLALB5;6define <vscale x 8 x i16> @smlalb_i16(<vscale x 8 x i16> %a,7 <vscale x 16 x i8> %b,8 <vscale x 16 x i8> %c) {9; CHECK-LABEL: smlalb_i1610; CHECK: smlalb z0.h, z1.b, z2.b11; CHECK-NEXT: ret12 %res = call <vscale x 8 x i16> @llvm.aarch64.sve.smlalb.nxv8i16(<vscale x 8 x i16> %a,13 <vscale x 16 x i8> %b,14 <vscale x 16 x i8> %c)15 ret <vscale x 8 x i16> %res16}17 18define <vscale x 4 x i32> @smlalb_i32(<vscale x 4 x i32> %a,19 <vscale x 8 x i16> %b,20 <vscale x 8 x i16> %c) {21; CHECK-LABEL: smlalb_i3222; CHECK: smlalb z0.s, z1.h, z2.h23; CHECK-NEXT: ret24 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.smlalb.nxv4i32(<vscale x 4 x i32> %a,25 <vscale x 8 x i16> %b,26 <vscale x 8 x i16> %c)27 ret <vscale x 4 x i32> %res28}29 30define <vscale x 2 x i64> @smlalb_i64(<vscale x 2 x i64> %a,31 <vscale x 4 x i32> %b,32 <vscale x 4 x i32> %c) {33; CHECK-LABEL: smlalb_i6434; CHECK: smlalb z0.d, z1.s, z2.s35; CHECK-NEXT: ret36 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.smlalb.nxv2i64(<vscale x 2 x i64> %a,37 <vscale x 4 x i32> %b,38 <vscale x 4 x i32> %c)39 ret <vscale x 2 x i64> %res40}41 42;43; SMLALT44;45define <vscale x 8 x i16> @smlalt_i16(<vscale x 8 x i16> %a,46 <vscale x 16 x i8> %b,47 <vscale x 16 x i8> %c) {48; CHECK-LABEL: smlalt_i1649; CHECK: smlalt z0.h, z1.b, z2.b50; CHECK-NEXT: ret51 %res = call <vscale x 8 x i16> @llvm.aarch64.sve.smlalt.nxv8i16(<vscale x 8 x i16> %a,52 <vscale x 16 x i8> %b,53 <vscale x 16 x i8> %c)54 ret <vscale x 8 x i16> %res55}56 57define <vscale x 4 x i32> @smlalt_i32(<vscale x 4 x i32> %a,58 <vscale x 8 x i16> %b,59 <vscale x 8 x i16> %c) {60; CHECK-LABEL: smlalt_i3261; CHECK: smlalt z0.s, z1.h, z2.h62; CHECK-NEXT: ret63 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.smlalt.nxv4i32(<vscale x 4 x i32> %a,64 <vscale x 8 x i16> %b,65 <vscale x 8 x i16> %c)66 ret <vscale x 4 x i32> %res67}68 69define <vscale x 2 x i64> @smlalt_i64(<vscale x 2 x i64> %a,70 <vscale x 4 x i32> %b,71 <vscale x 4 x i32> %c) {72; CHECK-LABEL: smlalt_i6473; CHECK: smlalt z0.d, z1.s, z2.s74; CHECK-NEXT: ret75 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.smlalt.nxv2i64(<vscale x 2 x i64> %a,76 <vscale x 4 x i32> %b,77 <vscale x 4 x i32> %c)78 ret <vscale x 2 x i64> %res79}80 81;82; UMLALB83;84define <vscale x 8 x i16> @umlalb_i16(<vscale x 8 x i16> %a,85 <vscale x 16 x i8> %b,86 <vscale x 16 x i8> %c) {87; CHECK-LABEL: umlalb_i1688; CHECK: umlalb z0.h, z1.b, z2.b89; CHECK-NEXT: ret90 %res = call <vscale x 8 x i16> @llvm.aarch64.sve.umlalb.nxv8i16(<vscale x 8 x i16> %a,91 <vscale x 16 x i8> %b,92 <vscale x 16 x i8> %c)93 ret <vscale x 8 x i16> %res94}95 96define <vscale x 4 x i32> @umlalb_i32(<vscale x 4 x i32> %a,97 <vscale x 8 x i16> %b,98 <vscale x 8 x i16> %c) {99; CHECK-LABEL: umlalb_i32100; CHECK: umlalb z0.s, z1.h, z2.h101; CHECK-NEXT: ret102 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.umlalb.nxv4i32(<vscale x 4 x i32> %a,103 <vscale x 8 x i16> %b,104 <vscale x 8 x i16> %c)105 ret <vscale x 4 x i32> %res106}107 108define <vscale x 2 x i64> @umlalb_i64(<vscale x 2 x i64> %a,109 <vscale x 4 x i32> %b,110 <vscale x 4 x i32> %c) {111; CHECK-LABEL: umlalb_i64112; CHECK: umlalb z0.d, z1.s, z2.s113; CHECK-NEXT: ret114 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.umlalb.nxv2i64(<vscale x 2 x i64> %a,115 <vscale x 4 x i32> %b,116 <vscale x 4 x i32> %c)117 ret <vscale x 2 x i64> %res118}119 120;121; UMLALT122;123define <vscale x 8 x i16> @umlalt_i16(<vscale x 8 x i16> %a,124 <vscale x 16 x i8> %b,125 <vscale x 16 x i8> %c) {126; CHECK-LABEL: umlalt_i16127; CHECK: umlalt z0.h, z1.b, z2.b128; CHECK-NEXT: ret129 %res = call <vscale x 8 x i16> @llvm.aarch64.sve.umlalt.nxv8i16(<vscale x 8 x i16> %a,130 <vscale x 16 x i8> %b,131 <vscale x 16 x i8> %c)132 ret <vscale x 8 x i16> %res133}134 135define <vscale x 4 x i32> @umlalt_i32(<vscale x 4 x i32> %a,136 <vscale x 8 x i16> %b,137 <vscale x 8 x i16> %c) {138; CHECK-LABEL: umlalt_i32139; CHECK: umlalt z0.s, z1.h, z2.h140; CHECK-NEXT: ret141 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.umlalt.nxv4i32(<vscale x 4 x i32> %a,142 <vscale x 8 x i16> %b,143 <vscale x 8 x i16> %c)144 ret <vscale x 4 x i32> %res145}146 147define <vscale x 2 x i64> @umlalt_i64(<vscale x 2 x i64> %a,148 <vscale x 4 x i32> %b,149 <vscale x 4 x i32> %c) {150; CHECK-LABEL: umlalt_i64151; CHECK: umlalt z0.d, z1.s, z2.s152; CHECK-NEXT: ret153 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.umlalt.nxv2i64(<vscale x 2 x i64> %a,154 <vscale x 4 x i32> %b,155 <vscale x 4 x i32> %c)156 ret <vscale x 2 x i64> %res157}158 159;160; SMLSLB161;162define <vscale x 8 x i16> @smlslb_i16(<vscale x 8 x i16> %a,163 <vscale x 16 x i8> %b,164 <vscale x 16 x i8> %c) {165; CHECK-LABEL: smlslb_i16166; CHECK: smlslb z0.h, z1.b, z2.b167; CHECK-NEXT: ret168 %res = call <vscale x 8 x i16> @llvm.aarch64.sve.smlslb.nxv8i16(<vscale x 8 x i16> %a,169 <vscale x 16 x i8> %b,170 <vscale x 16 x i8> %c)171 ret <vscale x 8 x i16> %res172}173 174define <vscale x 4 x i32> @smlslb_i32(<vscale x 4 x i32> %a,175 <vscale x 8 x i16> %b,176 <vscale x 8 x i16> %c) {177; CHECK-LABEL: smlslb_i32178; CHECK: smlslb z0.s, z1.h, z2.h179; CHECK-NEXT: ret180 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.smlslb.nxv4i32(<vscale x 4 x i32> %a,181 <vscale x 8 x i16> %b,182 <vscale x 8 x i16> %c)183 ret <vscale x 4 x i32> %res184}185 186define <vscale x 2 x i64> @smlslb_i64(<vscale x 2 x i64> %a,187 <vscale x 4 x i32> %b,188 <vscale x 4 x i32> %c) {189; CHECK-LABEL: smlslb_i64190; CHECK: smlslb z0.d, z1.s, z2.s191; CHECK-NEXT: ret192 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.smlslb.nxv2i64(<vscale x 2 x i64> %a,193 <vscale x 4 x i32> %b,194 <vscale x 4 x i32> %c)195 ret <vscale x 2 x i64> %res196}197 198;199; SMLSLT200;201define <vscale x 8 x i16> @smlslt_i16(<vscale x 8 x i16> %a,202 <vscale x 16 x i8> %b,203 <vscale x 16 x i8> %c) {204; CHECK-LABEL: smlslt_i16205; CHECK: smlslt z0.h, z1.b, z2.b206; CHECK-NEXT: ret207 %res = call <vscale x 8 x i16> @llvm.aarch64.sve.smlslt.nxv8i16(<vscale x 8 x i16> %a,208 <vscale x 16 x i8> %b,209 <vscale x 16 x i8> %c)210 ret <vscale x 8 x i16> %res211}212 213define <vscale x 4 x i32> @smlslt_i32(<vscale x 4 x i32> %a,214 <vscale x 8 x i16> %b,215 <vscale x 8 x i16> %c) {216; CHECK-LABEL: smlslt_i32217; CHECK: smlslt z0.s, z1.h, z2.h218; CHECK-NEXT: ret219 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.smlslt.nxv4i32(<vscale x 4 x i32> %a,220 <vscale x 8 x i16> %b,221 <vscale x 8 x i16> %c)222 ret <vscale x 4 x i32> %res223}224 225define <vscale x 2 x i64> @smlslt_i64(<vscale x 2 x i64> %a,226 <vscale x 4 x i32> %b,227 <vscale x 4 x i32> %c) {228; CHECK-LABEL: smlslt_i64229; CHECK: smlslt z0.d, z1.s, z2.s230; CHECK-NEXT: ret231 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.smlslt.nxv2i64(<vscale x 2 x i64> %a,232 <vscale x 4 x i32> %b,233 <vscale x 4 x i32> %c)234 ret <vscale x 2 x i64> %res235}236 237;238; UMLSLB239;240define <vscale x 8 x i16> @umlslb_i16(<vscale x 8 x i16> %a,241 <vscale x 16 x i8> %b,242 <vscale x 16 x i8> %c) {243; CHECK-LABEL: umlslb_i16244; CHECK: umlslb z0.h, z1.b, z2.b245; CHECK-NEXT: ret246 %res = call <vscale x 8 x i16> @llvm.aarch64.sve.umlslb.nxv8i16(<vscale x 8 x i16> %a,247 <vscale x 16 x i8> %b,248 <vscale x 16 x i8> %c)249 ret <vscale x 8 x i16> %res250}251 252define <vscale x 4 x i32> @umlslb_i32(<vscale x 4 x i32> %a,253 <vscale x 8 x i16> %b,254 <vscale x 8 x i16> %c) {255; CHECK-LABEL: umlslb_i32256; CHECK: umlslb z0.s, z1.h, z2.h257; CHECK-NEXT: ret258 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.umlslb.nxv4i32(<vscale x 4 x i32> %a,259 <vscale x 8 x i16> %b,260 <vscale x 8 x i16> %c)261 ret <vscale x 4 x i32> %res262}263 264define <vscale x 2 x i64> @umlslb_i64(<vscale x 2 x i64> %a,265 <vscale x 4 x i32> %b,266 <vscale x 4 x i32> %c) {267; CHECK-LABEL: umlslb_i64268; CHECK: umlslb z0.d, z1.s, z2.s269; CHECK-NEXT: ret270 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.umlslb.nxv2i64(<vscale x 2 x i64> %a,271 <vscale x 4 x i32> %b,272 <vscale x 4 x i32> %c)273 ret <vscale x 2 x i64> %res274}275 276;277; UMLSLT278;279define <vscale x 8 x i16> @umlslt_i16(<vscale x 8 x i16> %a,280 <vscale x 16 x i8> %b,281 <vscale x 16 x i8> %c) {282; CHECK-LABEL: umlslt_i16283; CHECK: umlslt z0.h, z1.b, z2.b284; CHECK-NEXT: ret285 %res = call <vscale x 8 x i16> @llvm.aarch64.sve.umlslt.nxv8i16(<vscale x 8 x i16> %a,286 <vscale x 16 x i8> %b,287 <vscale x 16 x i8> %c)288 ret <vscale x 8 x i16> %res289}290 291define <vscale x 4 x i32> @umlslt_i32(<vscale x 4 x i32> %a,292 <vscale x 8 x i16> %b,293 <vscale x 8 x i16> %c) {294; CHECK-LABEL: umlslt_i32295; CHECK: umlslt z0.s, z1.h, z2.h296; CHECK-NEXT: ret297 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.umlslt.nxv4i32(<vscale x 4 x i32> %a,298 <vscale x 8 x i16> %b,299 <vscale x 8 x i16> %c)300 ret <vscale x 4 x i32> %res301}302 303define <vscale x 2 x i64> @umlslt_i64(<vscale x 2 x i64> %a,304 <vscale x 4 x i32> %b,305 <vscale x 4 x i32> %c) {306; CHECK-LABEL: umlslt_i64307; CHECK: umlslt z0.d, z1.s, z2.s308; CHECK-NEXT: ret309 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.umlslt.nxv2i64(<vscale x 2 x i64> %a,310 <vscale x 4 x i32> %b,311 <vscale x 4 x i32> %c)312 ret <vscale x 2 x i64> %res313}314 315;316; SQDMLALB317;318define <vscale x 8 x i16> @sqdmlalb_i16(<vscale x 8 x i16> %a,319 <vscale x 16 x i8> %b,320 <vscale x 16 x i8> %c) {321; CHECK-LABEL: sqdmlalb_i16322; CHECK: sqdmlalb z0.h, z1.b, z2.b323; CHECK-NEXT: ret324 %res = call <vscale x 8 x i16> @llvm.aarch64.sve.sqdmlalb.nxv8i16(<vscale x 8 x i16> %a,325 <vscale x 16 x i8> %b,326 <vscale x 16 x i8> %c)327 ret <vscale x 8 x i16> %res328}329 330define <vscale x 4 x i32> @sqdmlalb_i32(<vscale x 4 x i32> %a,331 <vscale x 8 x i16> %b,332 <vscale x 8 x i16> %c) {333; CHECK-LABEL: sqdmlalb_i32334; CHECK: sqdmlalb z0.s, z1.h, z2.h335; CHECK-NEXT: ret336 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlalb.nxv4i32(<vscale x 4 x i32> %a,337 <vscale x 8 x i16> %b,338 <vscale x 8 x i16> %c)339 ret <vscale x 4 x i32> %res340}341 342define <vscale x 2 x i64> @sqdmlalb_i64(<vscale x 2 x i64> %a,343 <vscale x 4 x i32> %b,344 <vscale x 4 x i32> %c) {345; CHECK-LABEL: sqdmlalb_i64346; CHECK: sqdmlalb z0.d, z1.s, z2.s347; CHECK-NEXT: ret348 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlalb.nxv2i64(<vscale x 2 x i64> %a,349 <vscale x 4 x i32> %b,350 <vscale x 4 x i32> %c)351 ret <vscale x 2 x i64> %res352}353 354;355; SQDMLALT356;357define <vscale x 8 x i16> @sqdmlalt_i16(<vscale x 8 x i16> %a,358 <vscale x 16 x i8> %b,359 <vscale x 16 x i8> %c) {360; CHECK-LABEL: sqdmlalt_i16361; CHECK: sqdmlalt z0.h, z1.b, z2.b362; CHECK-NEXT: ret363 %res = call <vscale x 8 x i16> @llvm.aarch64.sve.sqdmlalt.nxv8i16(<vscale x 8 x i16> %a,364 <vscale x 16 x i8> %b,365 <vscale x 16 x i8> %c)366 ret <vscale x 8 x i16> %res367}368 369define <vscale x 4 x i32> @sqdmlalt_i32(<vscale x 4 x i32> %a,370 <vscale x 8 x i16> %b,371 <vscale x 8 x i16> %c) {372; CHECK-LABEL: sqdmlalt_i32373; CHECK: sqdmlalt z0.s, z1.h, z2.h374; CHECK-NEXT: ret375 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlalt.nxv4i32(<vscale x 4 x i32> %a,376 <vscale x 8 x i16> %b,377 <vscale x 8 x i16> %c)378 ret <vscale x 4 x i32> %res379}380 381define <vscale x 2 x i64> @sqdmlalt_i64(<vscale x 2 x i64> %a,382 <vscale x 4 x i32> %b,383 <vscale x 4 x i32> %c) {384; CHECK-LABEL: sqdmlalt_i64385; CHECK: sqdmlalt z0.d, z1.s, z2.s386; CHECK-NEXT: ret387 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlalt.nxv2i64(<vscale x 2 x i64> %a,388 <vscale x 4 x i32> %b,389 <vscale x 4 x i32> %c)390 ret <vscale x 2 x i64> %res391}392 393;394; SQDMLSLB395;396define <vscale x 8 x i16> @sqdmlslb_i16(<vscale x 8 x i16> %a,397 <vscale x 16 x i8> %b,398 <vscale x 16 x i8> %c) {399; CHECK-LABEL: sqdmlslb_i16400; CHECK: sqdmlslb z0.h, z1.b, z2.b401; CHECK-NEXT: ret402 %res = call <vscale x 8 x i16> @llvm.aarch64.sve.sqdmlslb.nxv8i16(<vscale x 8 x i16> %a,403 <vscale x 16 x i8> %b,404 <vscale x 16 x i8> %c)405 ret <vscale x 8 x i16> %res406}407 408define <vscale x 4 x i32> @sqdmlslb_i32(<vscale x 4 x i32> %a,409 <vscale x 8 x i16> %b,410 <vscale x 8 x i16> %c) {411; CHECK-LABEL: sqdmlslb_i32412; CHECK: sqdmlslb z0.s, z1.h, z2.h413; CHECK-NEXT: ret414 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlslb.nxv4i32(<vscale x 4 x i32> %a,415 <vscale x 8 x i16> %b,416 <vscale x 8 x i16> %c)417 ret <vscale x 4 x i32> %res418}419 420define <vscale x 2 x i64> @sqdmlslb_i64(<vscale x 2 x i64> %a,421 <vscale x 4 x i32> %b,422 <vscale x 4 x i32> %c) {423; CHECK-LABEL: sqdmlslb_i64424; CHECK: sqdmlslb z0.d, z1.s, z2.s425; CHECK-NEXT: ret426 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlslb.nxv2i64(<vscale x 2 x i64> %a,427 <vscale x 4 x i32> %b,428 <vscale x 4 x i32> %c)429 ret <vscale x 2 x i64> %res430}431 432;433; SQDMLSLT434;435define <vscale x 8 x i16> @sqdmlslt_i16(<vscale x 8 x i16> %a,436 <vscale x 16 x i8> %b,437 <vscale x 16 x i8> %c) {438; CHECK-LABEL: sqdmlslt_i16439; CHECK: sqdmlslt z0.h, z1.b, z2.b440; CHECK-NEXT: ret441 %res = call <vscale x 8 x i16> @llvm.aarch64.sve.sqdmlslt.nxv8i16(<vscale x 8 x i16> %a,442 <vscale x 16 x i8> %b,443 <vscale x 16 x i8> %c)444 ret <vscale x 8 x i16> %res445}446 447define <vscale x 4 x i32> @sqdmlslt_i32(<vscale x 4 x i32> %a,448 <vscale x 8 x i16> %b,449 <vscale x 8 x i16> %c) {450; CHECK-LABEL: sqdmlslt_i32451; CHECK: sqdmlslt z0.s, z1.h, z2.h452; CHECK-NEXT: ret453 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlslt.nxv4i32(<vscale x 4 x i32> %a,454 <vscale x 8 x i16> %b,455 <vscale x 8 x i16> %c)456 ret <vscale x 4 x i32> %res457}458 459define <vscale x 2 x i64> @sqdmlslt_i64(<vscale x 2 x i64> %a,460 <vscale x 4 x i32> %b,461 <vscale x 4 x i32> %c) {462; CHECK-LABEL: sqdmlslt_i64463; CHECK: sqdmlslt z0.d, z1.s, z2.s464; CHECK-NEXT: ret465 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlslt.nxv2i64(<vscale x 2 x i64> %a,466 <vscale x 4 x i32> %b,467 <vscale x 4 x i32> %c)468 ret <vscale x 2 x i64> %res469}470 471;472; SQDMLALBT473;474define <vscale x 8 x i16> @sqdmlalbt_i16(<vscale x 8 x i16> %a,475 <vscale x 16 x i8> %b,476 <vscale x 16 x i8> %c) {477; CHECK-LABEL: sqdmlalbt_i16478; CHECK: sqdmlalbt z0.h, z1.b, z2.b479; CHECK-NEXT: ret480 %res = call <vscale x 8 x i16> @llvm.aarch64.sve.sqdmlalbt.nxv8i16(<vscale x 8 x i16> %a,481 <vscale x 16 x i8> %b,482 <vscale x 16 x i8> %c)483 ret <vscale x 8 x i16> %res484}485 486define <vscale x 4 x i32> @sqdmlalbt_i32(<vscale x 4 x i32> %a,487 <vscale x 8 x i16> %b,488 <vscale x 8 x i16> %c) {489; CHECK-LABEL: sqdmlalbt_i32490; CHECK: sqdmlalbt z0.s, z1.h, z2.h491; CHECK-NEXT: ret492 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlalbt.nxv4i32(<vscale x 4 x i32> %a,493 <vscale x 8 x i16> %b,494 <vscale x 8 x i16> %c)495 ret <vscale x 4 x i32> %res496}497 498define <vscale x 2 x i64> @sqdmlalbt_i64(<vscale x 2 x i64> %a,499 <vscale x 4 x i32> %b,500 <vscale x 4 x i32> %c) {501; CHECK-LABEL: sqdmlalbt_i64502; CHECK: sqdmlalbt z0.d, z1.s, z2.s503; CHECK-NEXT: ret504 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlalbt.nxv2i64(<vscale x 2 x i64> %a,505 <vscale x 4 x i32> %b,506 <vscale x 4 x i32> %c)507 ret <vscale x 2 x i64> %res508}509 510;511; SQDMLSLBT512;513define <vscale x 8 x i16> @sqdmlslbt_i16(<vscale x 8 x i16> %a,514 <vscale x 16 x i8> %b,515 <vscale x 16 x i8> %c) {516; CHECK-LABEL: sqdmlslbt_i16517; CHECK: sqdmlslbt z0.h, z1.b, z2.b518; CHECK-NEXT: ret519 %res = call <vscale x 8 x i16> @llvm.aarch64.sve.sqdmlslbt.nxv8i16(<vscale x 8 x i16> %a,520 <vscale x 16 x i8> %b,521 <vscale x 16 x i8> %c)522 ret <vscale x 8 x i16> %res523}524 525define <vscale x 4 x i32> @sqdmlslbt_i32(<vscale x 4 x i32> %a,526 <vscale x 8 x i16> %b,527 <vscale x 8 x i16> %c) {528; CHECK-LABEL: sqdmlslbt_i32529; CHECK: sqdmlslbt z0.s, z1.h, z2.h530; CHECK-NEXT: ret531 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlslbt.nxv4i32(<vscale x 4 x i32> %a,532 <vscale x 8 x i16> %b,533 <vscale x 8 x i16> %c)534 ret <vscale x 4 x i32> %res535}536 537define <vscale x 2 x i64> @sqdmlslbt_i64(<vscale x 2 x i64> %a,538 <vscale x 4 x i32> %b,539 <vscale x 4 x i32> %c) {540; CHECK-LABEL: sqdmlslbt_i64541; CHECK: sqdmlslbt z0.d, z1.s, z2.s542; CHECK-NEXT: ret543 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlslbt.nxv2i64(<vscale x 2 x i64> %a,544 <vscale x 4 x i32> %b,545 <vscale x 4 x i32> %c)546 ret <vscale x 2 x i64> %res547}548 549declare <vscale x 8 x i16> @llvm.aarch64.sve.smlalb.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>)550declare <vscale x 4 x i32> @llvm.aarch64.sve.smlalb.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>)551declare <vscale x 2 x i64> @llvm.aarch64.sve.smlalb.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>)552declare <vscale x 8 x i16> @llvm.aarch64.sve.smlalt.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>)553declare <vscale x 4 x i32> @llvm.aarch64.sve.smlalt.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>)554declare <vscale x 2 x i64> @llvm.aarch64.sve.smlalt.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>)555declare <vscale x 8 x i16> @llvm.aarch64.sve.umlalb.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>)556declare <vscale x 4 x i32> @llvm.aarch64.sve.umlalb.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>)557declare <vscale x 2 x i64> @llvm.aarch64.sve.umlalb.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>)558declare <vscale x 8 x i16> @llvm.aarch64.sve.umlalt.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>)559declare <vscale x 4 x i32> @llvm.aarch64.sve.umlalt.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>)560declare <vscale x 2 x i64> @llvm.aarch64.sve.umlalt.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>)561declare <vscale x 8 x i16> @llvm.aarch64.sve.smlslb.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>)562declare <vscale x 4 x i32> @llvm.aarch64.sve.smlslb.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>)563declare <vscale x 2 x i64> @llvm.aarch64.sve.smlslb.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>)564declare <vscale x 8 x i16> @llvm.aarch64.sve.smlslt.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>)565declare <vscale x 4 x i32> @llvm.aarch64.sve.smlslt.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>)566declare <vscale x 2 x i64> @llvm.aarch64.sve.smlslt.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>)567declare <vscale x 8 x i16> @llvm.aarch64.sve.umlslb.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>)568declare <vscale x 4 x i32> @llvm.aarch64.sve.umlslb.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>)569declare <vscale x 2 x i64> @llvm.aarch64.sve.umlslb.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>)570declare <vscale x 8 x i16> @llvm.aarch64.sve.umlslt.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>)571declare <vscale x 4 x i32> @llvm.aarch64.sve.umlslt.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>)572declare <vscale x 2 x i64> @llvm.aarch64.sve.umlslt.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>)573declare <vscale x 8 x i16> @llvm.aarch64.sve.sqdmlalb.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>)574declare <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlalb.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>)575declare <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlalb.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>)576declare <vscale x 8 x i16> @llvm.aarch64.sve.sqdmlalt.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>)577declare <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlalt.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>)578declare <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlalt.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>)579declare <vscale x 8 x i16> @llvm.aarch64.sve.sqdmlslb.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>)580declare <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlslb.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>)581declare <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlslb.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>)582declare <vscale x 8 x i16> @llvm.aarch64.sve.sqdmlslt.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>)583declare <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlslt.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>)584declare <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlslt.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>)585declare <vscale x 8 x i16> @llvm.aarch64.sve.sqdmlalbt.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>)586declare <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlalbt.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>)587declare <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlalbt.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>)588declare <vscale x 8 x i16> @llvm.aarch64.sve.sqdmlslbt.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>)589declare <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlslbt.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>)590declare <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlslbt.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>)591