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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=aarch64 -mattr=+sve < %s -o - | FileCheck --check-prefixes=CHECK,SVE %s3; RUN: llc -mtriple=aarch64 -mattr=+sve2 < %s -o - | FileCheck --check-prefixes=CHECK,SVE2 %s4 5; Wrong add/shift amount. Should be 32 for shift of 6.6define <vscale x 2 x i64> @neg_urshr_1(<vscale x 2 x i64> %x) {7; CHECK-LABEL: neg_urshr_1:8; CHECK: // %bb.0:9; CHECK-NEXT: add z0.d, z0.d, #16 // =0x1010; CHECK-NEXT: lsr z0.d, z0.d, #611; CHECK-NEXT: ret12 %add = add nuw nsw <vscale x 2 x i64> %x, splat (i64 16)13 %sh = lshr <vscale x 2 x i64> %add, splat (i64 6)14 ret <vscale x 2 x i64> %sh15}16 17; Vector Shift.18define <vscale x 2 x i64> @neg_urshr_2(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y) {19; CHECK-LABEL: neg_urshr_2:20; CHECK: // %bb.0:21; CHECK-NEXT: add z0.d, z0.d, #32 // =0x2022; CHECK-NEXT: ptrue p0.d23; CHECK-NEXT: lsr z0.d, p0/m, z0.d, z1.d24; CHECK-NEXT: ret25 %add = add nuw nsw <vscale x 2 x i64> %x, splat (i64 32)26 %sh = lshr <vscale x 2 x i64> %add, %y27 ret <vscale x 2 x i64> %sh28}29 30; Vector Add.31define <vscale x 2 x i64> @neg_urshr_3(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y) {32; CHECK-LABEL: neg_urshr_3:33; CHECK: // %bb.0:34; CHECK-NEXT: add z0.d, z0.d, z1.d35; CHECK-NEXT: lsr z0.d, z0.d, #636; CHECK-NEXT: ret37 %add = add nuw nsw <vscale x 2 x i64> %x, %y38 %sh = lshr <vscale x 2 x i64> %add, splat (i64 6)39 ret <vscale x 2 x i64> %sh40}41 42; Add has two uses.43define <vscale x 2 x i64> @neg_urshr_4(<vscale x 2 x i64> %x, ptr %p) {44; CHECK-LABEL: neg_urshr_4:45; CHECK: // %bb.0:46; CHECK-NEXT: mov z1.d, z0.d47; CHECK-NEXT: add z1.d, z1.d, #32 // =0x2048; CHECK-NEXT: lsr z0.d, z1.d, #649; CHECK-NEXT: str z1, [x0]50; CHECK-NEXT: ret51 %add = add nuw nsw <vscale x 2 x i64> %x, splat (i64 32)52 %sh = lshr <vscale x 2 x i64> %add, splat (i64 6)53 store <vscale x 2 x i64> %add, ptr %p54 ret <vscale x 2 x i64> %sh55}56 57; Add can overflow.58define <vscale x 2 x i64> @neg_urshr_5(<vscale x 2 x i64> %x) {59; CHECK-LABEL: neg_urshr_5:60; CHECK: // %bb.0:61; CHECK-NEXT: add z0.d, z0.d, #32 // =0x2062; CHECK-NEXT: lsr z0.d, z0.d, #663; CHECK-NEXT: ret64 %add = add <vscale x 2 x i64> %x, splat (i64 32)65 %sh = lshr <vscale x 2 x i64> %add, splat (i64 6)66 ret <vscale x 2 x i64> %sh67}68 69define <vscale x 16 x i8> @urshr_i8(<vscale x 16 x i8> %x) {70; SVE-LABEL: urshr_i8:71; SVE: // %bb.0:72; SVE-NEXT: add z0.b, z0.b, #32 // =0x2073; SVE-NEXT: lsr z0.b, z0.b, #674; SVE-NEXT: ret75;76; SVE2-LABEL: urshr_i8:77; SVE2: // %bb.0:78; SVE2-NEXT: ptrue p0.b79; SVE2-NEXT: urshr z0.b, p0/m, z0.b, #680; SVE2-NEXT: ret81 %add = add nuw nsw <vscale x 16 x i8> %x, splat (i8 32)82 %sh = lshr <vscale x 16 x i8> %add, splat (i8 6)83 ret <vscale x 16 x i8> %sh84}85 86define <vscale x 16 x i8> @urshr_8_wide_trunc(<vscale x 16 x i8> %x) {87; SVE-LABEL: urshr_8_wide_trunc:88; SVE: // %bb.0:89; SVE-NEXT: uunpkhi z1.h, z0.b90; SVE-NEXT: uunpklo z0.h, z0.b91; SVE-NEXT: add z0.h, z0.h, #32 // =0x2092; SVE-NEXT: add z1.h, z1.h, #32 // =0x2093; SVE-NEXT: lsr z1.h, z1.h, #694; SVE-NEXT: lsr z0.h, z0.h, #695; SVE-NEXT: uzp1 z0.b, z0.b, z1.b96; SVE-NEXT: ret97;98; SVE2-LABEL: urshr_8_wide_trunc:99; SVE2: // %bb.0:100; SVE2-NEXT: ptrue p0.b101; SVE2-NEXT: urshr z0.b, p0/m, z0.b, #6102; SVE2-NEXT: ret103 %ext = zext <vscale x 16 x i8> %x to <vscale x 16 x i16>104 %add = add nuw nsw <vscale x 16 x i16> %ext, splat (i16 32)105 %sh = lshr <vscale x 16 x i16> %add, splat (i16 6)106 %sht = trunc <vscale x 16 x i16> %sh to <vscale x 16 x i8>107 ret <vscale x 16 x i8> %sht108}109 110define <vscale x 16 x i8> @urshr_8_wide_trunc_nomerge(<vscale x 16 x i16> %ext) {111; SVE-LABEL: urshr_8_wide_trunc_nomerge:112; SVE: // %bb.0:113; SVE-NEXT: add z0.h, z0.h, #256 // =0x100114; SVE-NEXT: add z1.h, z1.h, #256 // =0x100115; SVE-NEXT: lsr z1.h, z1.h, #9116; SVE-NEXT: lsr z0.h, z0.h, #9117; SVE-NEXT: uzp1 z0.b, z0.b, z1.b118; SVE-NEXT: ret119;120; SVE2-LABEL: urshr_8_wide_trunc_nomerge:121; SVE2: // %bb.0:122; SVE2-NEXT: ptrue p0.h123; SVE2-NEXT: urshr z1.h, p0/m, z1.h, #9124; SVE2-NEXT: urshr z0.h, p0/m, z0.h, #9125; SVE2-NEXT: uzp1 z0.b, z0.b, z1.b126; SVE2-NEXT: ret127 %add = add nuw nsw <vscale x 16 x i16> %ext, splat (i16 256)128 %sh = lshr <vscale x 16 x i16> %add, splat (i16 9)129 %sht = trunc <vscale x 16 x i16> %sh to <vscale x 16 x i8>130 ret <vscale x 16 x i8> %sht131}132 133define <vscale x 8 x i16> @urshr_i16(<vscale x 8 x i16> %x) {134; SVE-LABEL: urshr_i16:135; SVE: // %bb.0:136; SVE-NEXT: add z0.h, z0.h, #32 // =0x20137; SVE-NEXT: lsr z0.h, z0.h, #6138; SVE-NEXT: ret139;140; SVE2-LABEL: urshr_i16:141; SVE2: // %bb.0:142; SVE2-NEXT: ptrue p0.h143; SVE2-NEXT: urshr z0.h, p0/m, z0.h, #6144; SVE2-NEXT: ret145 %add = add nuw nsw <vscale x 8 x i16> %x, splat (i16 32)146 %sh = lshr <vscale x 8 x i16> %add, splat (i16 6)147 ret <vscale x 8 x i16> %sh148}149 150define <vscale x 8 x i16> @urshr_16_wide_trunc(<vscale x 8 x i16> %x) {151; SVE-LABEL: urshr_16_wide_trunc:152; SVE: // %bb.0:153; SVE-NEXT: uunpkhi z1.s, z0.h154; SVE-NEXT: uunpklo z0.s, z0.h155; SVE-NEXT: add z0.s, z0.s, #32 // =0x20156; SVE-NEXT: add z1.s, z1.s, #32 // =0x20157; SVE-NEXT: lsr z1.s, z1.s, #6158; SVE-NEXT: lsr z0.s, z0.s, #6159; SVE-NEXT: uzp1 z0.h, z0.h, z1.h160; SVE-NEXT: ret161;162; SVE2-LABEL: urshr_16_wide_trunc:163; SVE2: // %bb.0:164; SVE2-NEXT: ptrue p0.h165; SVE2-NEXT: urshr z0.h, p0/m, z0.h, #6166; SVE2-NEXT: ret167 %ext = zext <vscale x 8 x i16> %x to <vscale x 8 x i32>168 %add = add nuw nsw <vscale x 8 x i32> %ext, splat (i32 32)169 %sh = lshr <vscale x 8 x i32> %add, splat (i32 6)170 %sht = trunc <vscale x 8 x i32> %sh to <vscale x 8 x i16>171 ret <vscale x 8 x i16> %sht172}173 174define <vscale x 8 x i16> @urshr_16_wide_trunc_nomerge(<vscale x 8 x i32> %ext) {175; SVE-LABEL: urshr_16_wide_trunc_nomerge:176; SVE: // %bb.0:177; SVE-NEXT: mov z2.s, #0x10000178; SVE-NEXT: add z0.s, z0.s, z2.s179; SVE-NEXT: add z1.s, z1.s, z2.s180; SVE-NEXT: lsr z1.s, z1.s, #17181; SVE-NEXT: lsr z0.s, z0.s, #17182; SVE-NEXT: uzp1 z0.h, z0.h, z1.h183; SVE-NEXT: ret184;185; SVE2-LABEL: urshr_16_wide_trunc_nomerge:186; SVE2: // %bb.0:187; SVE2-NEXT: ptrue p0.s188; SVE2-NEXT: urshr z1.s, p0/m, z1.s, #17189; SVE2-NEXT: urshr z0.s, p0/m, z0.s, #17190; SVE2-NEXT: uzp1 z0.h, z0.h, z1.h191; SVE2-NEXT: ret192 %add = add nuw nsw <vscale x 8 x i32> %ext, splat (i32 65536)193 %sh = lshr <vscale x 8 x i32> %add, splat (i32 17)194 %sht = trunc <vscale x 8 x i32> %sh to <vscale x 8 x i16>195 ret <vscale x 8 x i16> %sht196}197 198define <vscale x 4 x i32> @urshr_i32(<vscale x 4 x i32> %x) {199; SVE-LABEL: urshr_i32:200; SVE: // %bb.0:201; SVE-NEXT: add z0.s, z0.s, #32 // =0x20202; SVE-NEXT: lsr z0.s, z0.s, #6203; SVE-NEXT: ret204;205; SVE2-LABEL: urshr_i32:206; SVE2: // %bb.0:207; SVE2-NEXT: ptrue p0.s208; SVE2-NEXT: urshr z0.s, p0/m, z0.s, #6209; SVE2-NEXT: ret210 %add = add nuw nsw <vscale x 4 x i32> %x, splat (i32 32)211 %sh = lshr <vscale x 4 x i32> %add, splat (i32 6)212 ret <vscale x 4 x i32> %sh213}214 215define <vscale x 4 x i32> @urshr_32_wide_trunc(<vscale x 4 x i32> %x) {216; SVE-LABEL: urshr_32_wide_trunc:217; SVE: // %bb.0:218; SVE-NEXT: uunpkhi z1.d, z0.s219; SVE-NEXT: uunpklo z0.d, z0.s220; SVE-NEXT: add z0.d, z0.d, #32 // =0x20221; SVE-NEXT: add z1.d, z1.d, #32 // =0x20222; SVE-NEXT: lsr z1.d, z1.d, #6223; SVE-NEXT: lsr z0.d, z0.d, #6224; SVE-NEXT: uzp1 z0.s, z0.s, z1.s225; SVE-NEXT: ret226;227; SVE2-LABEL: urshr_32_wide_trunc:228; SVE2: // %bb.0:229; SVE2-NEXT: ptrue p0.s230; SVE2-NEXT: urshr z0.s, p0/m, z0.s, #6231; SVE2-NEXT: ret232 %ext = zext <vscale x 4 x i32> %x to <vscale x 4 x i64>233 %add = add nuw nsw <vscale x 4 x i64> %ext, splat (i64 32)234 %sh = lshr <vscale x 4 x i64> %add, splat (i64 6)235 %sht = trunc <vscale x 4 x i64> %sh to <vscale x 4 x i32>236 ret <vscale x 4 x i32> %sht237}238 239define <vscale x 4 x i32> @urshr_32_wide_trunc_nomerge(<vscale x 4 x i64> %ext) {240; SVE-LABEL: urshr_32_wide_trunc_nomerge:241; SVE: // %bb.0:242; SVE-NEXT: mov z2.d, #0x100000000243; SVE-NEXT: add z0.d, z0.d, z2.d244; SVE-NEXT: add z1.d, z1.d, z2.d245; SVE-NEXT: lsr z1.d, z1.d, #33246; SVE-NEXT: lsr z0.d, z0.d, #33247; SVE-NEXT: uzp1 z0.s, z0.s, z1.s248; SVE-NEXT: ret249;250; SVE2-LABEL: urshr_32_wide_trunc_nomerge:251; SVE2: // %bb.0:252; SVE2-NEXT: ptrue p0.d253; SVE2-NEXT: urshr z1.d, p0/m, z1.d, #33254; SVE2-NEXT: urshr z0.d, p0/m, z0.d, #33255; SVE2-NEXT: uzp1 z0.s, z0.s, z1.s256; SVE2-NEXT: ret257 %add = add nuw nsw <vscale x 4 x i64> %ext, splat (i64 4294967296)258 %sh = lshr <vscale x 4 x i64> %add, splat (i64 33)259 %sht = trunc <vscale x 4 x i64> %sh to <vscale x 4 x i32>260 ret <vscale x 4 x i32> %sht261}262 263define <vscale x 2 x i64> @urshr_i64(<vscale x 2 x i64> %x) {264; SVE-LABEL: urshr_i64:265; SVE: // %bb.0:266; SVE-NEXT: add z0.d, z0.d, #32 // =0x20267; SVE-NEXT: lsr z0.d, z0.d, #6268; SVE-NEXT: ret269;270; SVE2-LABEL: urshr_i64:271; SVE2: // %bb.0:272; SVE2-NEXT: ptrue p0.d273; SVE2-NEXT: urshr z0.d, p0/m, z0.d, #6274; SVE2-NEXT: ret275 %add = add nuw nsw <vscale x 2 x i64> %x, splat (i64 32)276 %sh = lshr <vscale x 2 x i64> %add, splat (i64 6)277 ret <vscale x 2 x i64> %sh278}279