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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=aarch64 -mattr=+sve < %s -o - | FileCheck --check-prefixes=CHECK,SVE %s3; RUN: llc -mtriple=aarch64 -mattr=+sve2 < %s -o - | FileCheck --check-prefixes=CHECK,SVE2 %s4 5define <vscale x 16 x i8> @testLeftGood16x8(<vscale x 16 x i8> %src1, <vscale x 16 x i8> %src2) {6; SVE-LABEL: testLeftGood16x8:7; SVE: // %bb.0:8; SVE-NEXT: and z0.b, z0.b, #0x79; SVE-NEXT: lsl z1.b, z1.b, #310; SVE-NEXT: orr z0.d, z0.d, z1.d11; SVE-NEXT: ret12;13; SVE2-LABEL: testLeftGood16x8:14; SVE2: // %bb.0:15; SVE2-NEXT: sli z0.b, z1.b, #316; SVE2-NEXT: ret17 %and.i = and <vscale x 16 x i8> %src1, splat(i8 7)18 %vshl_n = shl <vscale x 16 x i8> %src2, splat(i8 3)19 %result = or <vscale x 16 x i8> %and.i, %vshl_n20 ret <vscale x 16 x i8> %result21}22 23define <vscale x 16 x i8> @testLeftBad16x8(<vscale x 16 x i8> %src1, <vscale x 16 x i8> %src2) {24; CHECK-LABEL: testLeftBad16x8:25; CHECK: // %bb.0:26; CHECK-NEXT: mov z2.b, #-91 // =0xffffffffffffffa527; CHECK-NEXT: lsl z1.b, z1.b, #128; CHECK-NEXT: and z0.d, z0.d, z2.d29; CHECK-NEXT: orr z0.d, z0.d, z1.d30; CHECK-NEXT: ret31 %and.i = and <vscale x 16 x i8> %src1, splat(i8 165)32 %vshl_n = shl <vscale x 16 x i8> %src2, splat(i8 1)33 %result = or <vscale x 16 x i8> %and.i, %vshl_n34 ret <vscale x 16 x i8> %result35}36 37define <vscale x 16 x i8> @testRightGood16x8(<vscale x 16 x i8> %src1, <vscale x 16 x i8> %src2) {38; SVE-LABEL: testRightGood16x8:39; SVE: // %bb.0:40; SVE-NEXT: and z0.b, z0.b, #0xe041; SVE-NEXT: lsr z1.b, z1.b, #342; SVE-NEXT: orr z0.d, z0.d, z1.d43; SVE-NEXT: ret44;45; SVE2-LABEL: testRightGood16x8:46; SVE2: // %bb.0:47; SVE2-NEXT: sri z0.b, z1.b, #348; SVE2-NEXT: ret49 %and.i = and <vscale x 16 x i8> %src1, splat(i8 224)50 %vshl_n = lshr <vscale x 16 x i8> %src2, splat(i8 3)51 %result = or <vscale x 16 x i8> %and.i, %vshl_n52 ret <vscale x 16 x i8> %result53}54 55define <vscale x 16 x i8> @testRightBad16x8(<vscale x 16 x i8> %src1, <vscale x 16 x i8> %src2) {56; CHECK-LABEL: testRightBad16x8:57; CHECK: // %bb.0:58; CHECK-NEXT: mov z2.b, #-91 // =0xffffffffffffffa559; CHECK-NEXT: lsr z1.b, z1.b, #160; CHECK-NEXT: and z0.d, z0.d, z2.d61; CHECK-NEXT: orr z0.d, z0.d, z1.d62; CHECK-NEXT: ret63 %and.i = and <vscale x 16 x i8> %src1, splat(i8 165)64 %vshl_n = lshr <vscale x 16 x i8> %src2, splat(i8 1)65 %result = or <vscale x 16 x i8> %and.i, %vshl_n66 ret <vscale x 16 x i8> %result67}68 69define <vscale x 8 x i16> @testLeftGood8x16(<vscale x 8 x i16> %src1, <vscale x 8 x i16> %src2) {70; SVE-LABEL: testLeftGood8x16:71; SVE: // %bb.0:72; SVE-NEXT: and z0.h, z0.h, #0x3fff73; SVE-NEXT: lsl z1.h, z1.h, #1474; SVE-NEXT: orr z0.d, z0.d, z1.d75; SVE-NEXT: ret76;77; SVE2-LABEL: testLeftGood8x16:78; SVE2: // %bb.0:79; SVE2-NEXT: sli z0.h, z1.h, #1480; SVE2-NEXT: ret81 %and.i = and <vscale x 8 x i16> %src1, splat(i16 16383)82 %vshl_n = shl <vscale x 8 x i16> %src2, splat(i16 14)83 %result = or <vscale x 8 x i16> %and.i, %vshl_n84 ret <vscale x 8 x i16> %result85}86 87define <vscale x 8 x i16> @testLeftBad8x16(<vscale x 8 x i16> %src1, <vscale x 8 x i16> %src2) {88; CHECK-LABEL: testLeftBad8x16:89; CHECK: // %bb.0:90; CHECK-NEXT: mov w8, #16500 // =0x407491; CHECK-NEXT: lsl z1.h, z1.h, #1492; CHECK-NEXT: mov z2.h, w893; CHECK-NEXT: and z0.d, z0.d, z2.d94; CHECK-NEXT: orr z0.d, z0.d, z1.d95; CHECK-NEXT: ret96 %and.i = and <vscale x 8 x i16> %src1, splat(i16 16500)97 %vshl_n = shl <vscale x 8 x i16> %src2, splat(i16 14)98 %result = or <vscale x 8 x i16> %and.i, %vshl_n99 ret <vscale x 8 x i16> %result100}101 102define <vscale x 8 x i16> @testRightGood8x16(<vscale x 8 x i16> %src1, <vscale x 8 x i16> %src2) {103; SVE-LABEL: testRightGood8x16:104; SVE: // %bb.0:105; SVE-NEXT: and z0.h, z0.h, #0xfffc106; SVE-NEXT: lsr z1.h, z1.h, #14107; SVE-NEXT: orr z0.d, z0.d, z1.d108; SVE-NEXT: ret109;110; SVE2-LABEL: testRightGood8x16:111; SVE2: // %bb.0:112; SVE2-NEXT: sri z0.h, z1.h, #14113; SVE2-NEXT: ret114 %and.i = and <vscale x 8 x i16> %src1, splat(i16 65532)115 %vshl_n = lshr <vscale x 8 x i16> %src2, splat(i16 14)116 %result = or <vscale x 8 x i16> %and.i, %vshl_n117 ret <vscale x 8 x i16> %result118}119 120define <vscale x 8 x i16> @testRightBad8x16(<vscale x 8 x i16> %src1, <vscale x 8 x i16> %src2) {121; CHECK-LABEL: testRightBad8x16:122; CHECK: // %bb.0:123; CHECK-NEXT: mov w8, #16500 // =0x4074124; CHECK-NEXT: lsr z1.h, z1.h, #14125; CHECK-NEXT: mov z2.h, w8126; CHECK-NEXT: and z0.d, z0.d, z2.d127; CHECK-NEXT: orr z0.d, z0.d, z1.d128; CHECK-NEXT: ret129 %and.i = and <vscale x 8 x i16> %src1, splat(i16 16500)130 %vshl_n = lshr <vscale x 8 x i16> %src2, splat(i16 14)131 %result = or <vscale x 8 x i16> %and.i, %vshl_n132 ret <vscale x 8 x i16> %result133}134 135define <vscale x 4 x i32> @testLeftGood4x32(<vscale x 4 x i32> %src1, <vscale x 4 x i32> %src2) {136; SVE-LABEL: testLeftGood4x32:137; SVE: // %bb.0:138; SVE-NEXT: and z0.s, z0.s, #0x3fffff139; SVE-NEXT: lsl z1.s, z1.s, #22140; SVE-NEXT: orr z0.d, z0.d, z1.d141; SVE-NEXT: ret142;143; SVE2-LABEL: testLeftGood4x32:144; SVE2: // %bb.0:145; SVE2-NEXT: sli z0.s, z1.s, #22146; SVE2-NEXT: ret147 %and.i = and <vscale x 4 x i32> %src1, splat(i32 4194303)148 %vshl_n = shl <vscale x 4 x i32> %src2, splat(i32 22)149 %result = or <vscale x 4 x i32> %and.i, %vshl_n150 ret <vscale x 4 x i32> %result151}152 153define <vscale x 4 x i32> @testLeftBad4x32(<vscale x 4 x i32> %src1, <vscale x 4 x i32> %src2) {154; CHECK-LABEL: testLeftBad4x32:155; CHECK: // %bb.0:156; CHECK-NEXT: and z0.s, z0.s, #0x3ffffc157; CHECK-NEXT: lsl z1.s, z1.s, #22158; CHECK-NEXT: orr z0.d, z0.d, z1.d159; CHECK-NEXT: ret160 %and.i = and <vscale x 4 x i32> %src1, splat(i32 4194300)161 %vshl_n = shl <vscale x 4 x i32> %src2, splat(i32 22)162 %result = or <vscale x 4 x i32> %and.i, %vshl_n163 ret <vscale x 4 x i32> %result164}165 166define <vscale x 4 x i32> @testRightGood4x32(<vscale x 4 x i32> %src1, <vscale x 4 x i32> %src2) {167; SVE-LABEL: testRightGood4x32:168; SVE: // %bb.0:169; SVE-NEXT: and z0.s, z0.s, #0xfffffc00170; SVE-NEXT: lsr z1.s, z1.s, #22171; SVE-NEXT: orr z0.d, z0.d, z1.d172; SVE-NEXT: ret173;174; SVE2-LABEL: testRightGood4x32:175; SVE2: // %bb.0:176; SVE2-NEXT: sri z0.s, z1.s, #22177; SVE2-NEXT: ret178 %and.i = and <vscale x 4 x i32> %src1, splat(i32 4294966272)179 %vshl_n = lshr <vscale x 4 x i32> %src2, splat(i32 22)180 %result = or <vscale x 4 x i32> %and.i, %vshl_n181 ret <vscale x 4 x i32> %result182}183 184define <vscale x 4 x i32> @testRightBad4x32(<vscale x 4 x i32> %src1, <vscale x 4 x i32> %src2) {185; CHECK-LABEL: testRightBad4x32:186; CHECK: // %bb.0:187; CHECK-NEXT: and z0.s, z0.s, #0x3ffffc188; CHECK-NEXT: lsr z1.s, z1.s, #22189; CHECK-NEXT: orr z0.d, z0.d, z1.d190; CHECK-NEXT: ret191 %and.i = and <vscale x 4 x i32> %src1, splat(i32 4194300)192 %vshl_n = lshr <vscale x 4 x i32> %src2, splat(i32 22)193 %result = or <vscale x 4 x i32> %and.i, %vshl_n194 ret <vscale x 4 x i32> %result195}196 197define <vscale x 2 x i64> @testLeftGood2x64(<vscale x 2 x i64> %src1, <vscale x 2 x i64> %src2) {198; SVE-LABEL: testLeftGood2x64:199; SVE: // %bb.0:200; SVE-NEXT: and z0.d, z0.d, #0xffffffffffff201; SVE-NEXT: lsl z1.d, z1.d, #48202; SVE-NEXT: orr z0.d, z0.d, z1.d203; SVE-NEXT: ret204;205; SVE2-LABEL: testLeftGood2x64:206; SVE2: // %bb.0:207; SVE2-NEXT: sli z0.d, z1.d, #48208; SVE2-NEXT: ret209 %and.i = and <vscale x 2 x i64> %src1, splat(i64 281474976710655)210 %vshl_n = shl <vscale x 2 x i64> %src2, splat(i64 48)211 %result = or <vscale x 2 x i64> %and.i, %vshl_n212 ret <vscale x 2 x i64> %result213}214 215define <vscale x 2 x i64> @testLeftBad2x64(<vscale x 2 x i64> %src1, <vscale x 2 x i64> %src2) {216; CHECK-LABEL: testLeftBad2x64:217; CHECK: // %bb.0:218; CHECK-NEXT: mov x8, #10 // =0xa219; CHECK-NEXT: lsl z1.d, z1.d, #48220; CHECK-NEXT: movk x8, #1, lsl #48221; CHECK-NEXT: mov z2.d, x8222; CHECK-NEXT: and z0.d, z0.d, z2.d223; CHECK-NEXT: orr z0.d, z0.d, z1.d224; CHECK-NEXT: ret225 %and.i = and <vscale x 2 x i64> %src1, splat(i64 281474976710666)226 %vshl_n = shl <vscale x 2 x i64> %src2, splat(i64 48)227 %result = or <vscale x 2 x i64> %and.i, %vshl_n228 ret <vscale x 2 x i64> %result229}230 231define <vscale x 2 x i64> @testRightGood2x64(<vscale x 2 x i64> %src1, <vscale x 2 x i64> %src2) {232; SVE-LABEL: testRightGood2x64:233; SVE: // %bb.0:234; SVE-NEXT: and z0.d, z0.d, #0xffffffffffff0000235; SVE-NEXT: lsr z1.d, z1.d, #48236; SVE-NEXT: orr z0.d, z0.d, z1.d237; SVE-NEXT: ret238;239; SVE2-LABEL: testRightGood2x64:240; SVE2: // %bb.0:241; SVE2-NEXT: sri z0.d, z1.d, #48242; SVE2-NEXT: ret243 %and.i = and <vscale x 2 x i64> %src1, splat(i64 18446744073709486080)244 %vshl_n = lshr <vscale x 2 x i64> %src2, splat(i64 48)245 %result = or <vscale x 2 x i64> %and.i, %vshl_n246 ret <vscale x 2 x i64> %result247}248 249define <vscale x 2 x i64> @testRightBad2x64(<vscale x 2 x i64> %src1, <vscale x 2 x i64> %src2) {250; CHECK-LABEL: testRightBad2x64:251; CHECK: // %bb.0:252; CHECK-NEXT: mov x8, #10 // =0xa253; CHECK-NEXT: lsr z1.d, z1.d, #48254; CHECK-NEXT: movk x8, #1, lsl #48255; CHECK-NEXT: mov z2.d, x8256; CHECK-NEXT: and z0.d, z0.d, z2.d257; CHECK-NEXT: orr z0.d, z0.d, z1.d258; CHECK-NEXT: ret259 %and.i = and <vscale x 2 x i64> %src1, splat(i64 281474976710666)260 %vshl_n = lshr <vscale x 2 x i64> %src2, splat(i64 48)261 %result = or <vscale x 2 x i64> %and.i, %vshl_n262 ret <vscale x 2 x i64> %result263}264