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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s | FileCheck %s3 4target triple = "aarch64-unknown-linux-gnu"5 6; USRA7 8define <vscale x 16 x i8> @usra_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {9; CHECK-LABEL: usra_i8:10; CHECK: // %bb.0:11; CHECK-NEXT: usra z0.b, z1.b, #112; CHECK-NEXT: ret13 %shift = lshr <vscale x 16 x i8> %b, splat(i8 1)14 %add = add <vscale x 16 x i8> %a, %shift15 ret <vscale x 16 x i8> %add16}17 18define <vscale x 8 x i16> @usra_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {19; CHECK-LABEL: usra_i16:20; CHECK: // %bb.0:21; CHECK-NEXT: usra z0.h, z1.h, #222; CHECK-NEXT: ret23 %shift = lshr <vscale x 8 x i16> %b, splat(i16 2)24 %add = add <vscale x 8 x i16> %a, %shift25 ret <vscale x 8 x i16> %add26}27 28define <vscale x 4 x i32> @usra_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {29; CHECK-LABEL: usra_i32:30; CHECK: // %bb.0:31; CHECK-NEXT: usra z0.s, z1.s, #332; CHECK-NEXT: ret33 %shift = lshr <vscale x 4 x i32> %b, splat(i32 3)34 %add = add <vscale x 4 x i32> %a, %shift35 ret <vscale x 4 x i32> %add36}37 38define <vscale x 2 x i64> @usra_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {39; CHECK-LABEL: usra_i64:40; CHECK: // %bb.0:41; CHECK-NEXT: usra z0.d, z1.d, #442; CHECK-NEXT: ret43 %shift = lshr <vscale x 2 x i64> %b, splat(i64 4)44 %add = add <vscale x 2 x i64> %a, %shift45 ret <vscale x 2 x i64> %add46}47 48define <vscale x 16 x i8> @usra_intr_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {49; CHECK-LABEL: usra_intr_i8:50; CHECK: // %bb.0:51; CHECK-NEXT: usra z0.b, z1.b, #152; CHECK-NEXT: ret53 %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)54 %shift = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.u.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %b, <vscale x 16 x i8> splat(i8 1))55 %add = add <vscale x 16 x i8> %a, %shift56 ret <vscale x 16 x i8> %add57}58 59define <vscale x 8 x i16> @usra_intr_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {60; CHECK-LABEL: usra_intr_i16:61; CHECK: // %bb.0:62; CHECK-NEXT: usra z0.h, z1.h, #263; CHECK-NEXT: ret64 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)65 %shift = call <vscale x 8 x i16> @llvm.aarch64.sve.lsr.u.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %b, <vscale x 8 x i16> splat(i16 2))66 %add = add <vscale x 8 x i16> %a, %shift67 ret <vscale x 8 x i16> %add68}69 70define <vscale x 4 x i32> @usra_intr_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {71; CHECK-LABEL: usra_intr_i32:72; CHECK: // %bb.0:73; CHECK-NEXT: usra z0.s, z1.s, #374; CHECK-NEXT: ret75 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)76 %shift = call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %b, <vscale x 4 x i32> splat(i32 3))77 %add = add <vscale x 4 x i32> %a, %shift78 ret <vscale x 4 x i32> %add79}80 81define <vscale x 2 x i64> @usra_intr_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {82; CHECK-LABEL: usra_intr_i64:83; CHECK: // %bb.0:84; CHECK-NEXT: usra z0.d, z1.d, #485; CHECK-NEXT: ret86 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)87 %shift = call <vscale x 2 x i64> @llvm.aarch64.sve.lsr.u.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %b, <vscale x 2 x i64> splat(i64 4))88 %add = add <vscale x 2 x i64> %a, %shift89 ret <vscale x 2 x i64> %add90}91 92define <vscale x 16 x i8> @usra_intr_u_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {93; CHECK-LABEL: usra_intr_u_i8:94; CHECK: // %bb.0:95; CHECK-NEXT: usra z0.b, z1.b, #196; CHECK-NEXT: ret97 %shift = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.u.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %b, <vscale x 16 x i8> splat(i8 1))98 %add = add <vscale x 16 x i8> %a, %shift99 ret <vscale x 16 x i8> %add100}101 102define <vscale x 8 x i16> @usra_intr_u_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {103; CHECK-LABEL: usra_intr_u_i16:104; CHECK: // %bb.0:105; CHECK-NEXT: usra z0.h, z1.h, #2106; CHECK-NEXT: ret107 %shift = call <vscale x 8 x i16> @llvm.aarch64.sve.lsr.u.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %b, <vscale x 8 x i16> splat(i16 2))108 %add = add <vscale x 8 x i16> %a, %shift109 ret <vscale x 8 x i16> %add110}111 112define <vscale x 4 x i32> @usra_intr_u_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {113; CHECK-LABEL: usra_intr_u_i32:114; CHECK: // %bb.0:115; CHECK-NEXT: usra z0.s, z1.s, #3116; CHECK-NEXT: ret117 %shift = call <vscale x 4 x i32> @llvm.aarch64.sve.lsr.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %b, <vscale x 4 x i32> splat(i32 3))118 %add = add <vscale x 4 x i32> %a, %shift119 ret <vscale x 4 x i32> %add120}121 122define <vscale x 2 x i64> @usra_intr_u_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {123; CHECK-LABEL: usra_intr_u_i64:124; CHECK: // %bb.0:125; CHECK-NEXT: usra z0.d, z1.d, #4126; CHECK-NEXT: ret127 %shift = call <vscale x 2 x i64> @llvm.aarch64.sve.lsr.u.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %b, <vscale x 2 x i64> splat(i64 4))128 %add = add <vscale x 2 x i64> %a, %shift129 ret <vscale x 2 x i64> %add130}131 132; SSRA133 134define <vscale x 16 x i8> @ssra_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {135; CHECK-LABEL: ssra_i8:136; CHECK: // %bb.0:137; CHECK-NEXT: ssra z0.b, z1.b, #1138; CHECK-NEXT: ret139 %shift = ashr <vscale x 16 x i8> %b, splat(i8 1)140 %add = add <vscale x 16 x i8> %a, %shift141 ret <vscale x 16 x i8> %add142}143 144define <vscale x 8 x i16> @ssra_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {145; CHECK-LABEL: ssra_i16:146; CHECK: // %bb.0:147; CHECK-NEXT: ssra z0.h, z1.h, #2148; CHECK-NEXT: ret149 %shift = ashr <vscale x 8 x i16> %b, splat(i16 2)150 %add = add <vscale x 8 x i16> %a, %shift151 ret <vscale x 8 x i16> %add152}153 154define <vscale x 4 x i32> @ssra_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {155; CHECK-LABEL: ssra_i32:156; CHECK: // %bb.0:157; CHECK-NEXT: ssra z0.s, z1.s, #3158; CHECK-NEXT: ret159 %shift = ashr <vscale x 4 x i32> %b, splat(i32 3)160 %add = add <vscale x 4 x i32> %a, %shift161 ret <vscale x 4 x i32> %add162}163 164define <vscale x 2 x i64> @ssra_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {165; CHECK-LABEL: ssra_i64:166; CHECK: // %bb.0:167; CHECK-NEXT: ssra z0.d, z1.d, #4168; CHECK-NEXT: ret169 %shift = ashr <vscale x 2 x i64> %b, splat(i64 4)170 %add = add <vscale x 2 x i64> %a, %shift171 ret <vscale x 2 x i64> %add172}173 174define <vscale x 16 x i8> @ssra_intr_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {175; CHECK-LABEL: ssra_intr_i8:176; CHECK: // %bb.0:177; CHECK-NEXT: ssra z0.b, z1.b, #1178; CHECK-NEXT: ret179 %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)180 %shift = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.u.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %b, <vscale x 16 x i8> splat(i8 1))181 %add = add <vscale x 16 x i8> %a, %shift182 ret <vscale x 16 x i8> %add183}184 185define <vscale x 8 x i16> @ssra_intr_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {186; CHECK-LABEL: ssra_intr_i16:187; CHECK: // %bb.0:188; CHECK-NEXT: ssra z0.h, z1.h, #2189; CHECK-NEXT: ret190 %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)191 %shift = call <vscale x 8 x i16> @llvm.aarch64.sve.asr.u.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %b, <vscale x 8 x i16> splat(i16 2))192 %add = add <vscale x 8 x i16> %a, %shift193 ret <vscale x 8 x i16> %add194}195 196define <vscale x 4 x i32> @ssra_intr_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {197; CHECK-LABEL: ssra_intr_i32:198; CHECK: // %bb.0:199; CHECK-NEXT: ssra z0.s, z1.s, #3200; CHECK-NEXT: ret201 %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)202 %shift = call <vscale x 4 x i32> @llvm.aarch64.sve.asr.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %b, <vscale x 4 x i32> splat(i32 3))203 %add = add <vscale x 4 x i32> %a, %shift204 ret <vscale x 4 x i32> %add205}206 207define <vscale x 2 x i64> @ssra_intr_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {208; CHECK-LABEL: ssra_intr_i64:209; CHECK: // %bb.0:210; CHECK-NEXT: ssra z0.d, z1.d, #4211; CHECK-NEXT: ret212 %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)213 %shift = call <vscale x 2 x i64> @llvm.aarch64.sve.asr.u.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %b, <vscale x 2 x i64> splat(i64 4))214 %add = add <vscale x 2 x i64> %a, %shift215 ret <vscale x 2 x i64> %add216}217 218define <vscale x 16 x i8> @ssra_intr_u_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {219; CHECK-LABEL: ssra_intr_u_i8:220; CHECK: // %bb.0:221; CHECK-NEXT: ssra z0.b, z1.b, #1222; CHECK-NEXT: ret223 %shift = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.u.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %b, <vscale x 16 x i8> splat(i8 1))224 %add = add <vscale x 16 x i8> %a, %shift225 ret <vscale x 16 x i8> %add226}227 228define <vscale x 8 x i16> @ssra_intr_u_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {229; CHECK-LABEL: ssra_intr_u_i16:230; CHECK: // %bb.0:231; CHECK-NEXT: ssra z0.h, z1.h, #2232; CHECK-NEXT: ret233 %shift = call <vscale x 8 x i16> @llvm.aarch64.sve.asr.u.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %b, <vscale x 8 x i16> splat(i16 2))234 %add = add <vscale x 8 x i16> %a, %shift235 ret <vscale x 8 x i16> %add236}237 238define <vscale x 4 x i32> @ssra_intr_u_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {239; CHECK-LABEL: ssra_intr_u_i32:240; CHECK: // %bb.0:241; CHECK-NEXT: ssra z0.s, z1.s, #3242; CHECK-NEXT: ret243 %shift = call <vscale x 4 x i32> @llvm.aarch64.sve.asr.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %b, <vscale x 4 x i32> splat(i32 3))244 %add = add <vscale x 4 x i32> %a, %shift245 ret <vscale x 4 x i32> %add246}247 248define <vscale x 2 x i64> @ssra_intr_u_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {249; CHECK-LABEL: ssra_intr_u_i64:250; CHECK: // %bb.0:251; CHECK-NEXT: ssra z0.d, z1.d, #4252; CHECK-NEXT: ret253 %shift = call <vscale x 2 x i64> @llvm.aarch64.sve.asr.u.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %b, <vscale x 2 x i64> splat(i64 4))254 %add = add <vscale x 2 x i64> %a, %shift255 ret <vscale x 2 x i64> %add256}257 258declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 immarg)259declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 immarg)260declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 immarg)261declare <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 immarg)262 263declare <vscale x 16 x i8> @llvm.aarch64.sve.lsr.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)264declare <vscale x 8 x i16> @llvm.aarch64.sve.lsr.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)265declare <vscale x 4 x i32> @llvm.aarch64.sve.lsr.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)266declare <vscale x 2 x i64> @llvm.aarch64.sve.lsr.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)267 268declare <vscale x 16 x i8> @llvm.aarch64.sve.asr.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)269declare <vscale x 8 x i16> @llvm.aarch64.sve.asr.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)270declare <vscale x 4 x i32> @llvm.aarch64.sve.asr.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)271declare <vscale x 2 x i64> @llvm.aarch64.sve.asr.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)272 273attributes #0 = { "target-features"="+sve,+sve2" }274