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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1 < %s | FileCheck %s3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -force-streaming < %s | FileCheck %s4 5define <vscale x 4 x i32> @udot_vl128(<vscale x 4 x i32> %acc, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {6; CHECK-LABEL: udot_vl128:7; CHECK: // %bb.0: // %entry8; CHECK-NEXT: udot z0.s, z1.h, z2.h9; CHECK-NEXT: ret10entry:11 %a.wide = zext <vscale x 8 x i16> %a to <vscale x 8 x i32>12 %b.wide = zext <vscale x 8 x i16> %b to <vscale x 8 x i32>13 %mult = mul nuw nsw <vscale x 8 x i32> %a.wide, %b.wide14 %partial.reduce = tail call <vscale x 4 x i32> @llvm.vector.partial.reduce.add(<vscale x 4 x i32> %acc, <vscale x 8 x i32> %mult)15 ret <vscale x 4 x i32> %partial.reduce16}17 18define <vscale x 4 x i32> @sdot_vl128(<vscale x 4 x i32> %acc, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {19; CHECK-LABEL: sdot_vl128:20; CHECK: // %bb.0: // %entry21; CHECK-NEXT: sdot z0.s, z1.h, z2.h22; CHECK-NEXT: ret23entry:24 %a.wide = sext <vscale x 8 x i16> %a to <vscale x 8 x i32>25 %b.wide = sext <vscale x 8 x i16> %b to <vscale x 8 x i32>26 %mult = mul nuw nsw <vscale x 8 x i32> %a.wide, %b.wide27 %partial.reduce = tail call <vscale x 4 x i32> @llvm.vector.partial.reduce.add(<vscale x 4 x i32> %acc, <vscale x 8 x i32> %mult)28 ret <vscale x 4 x i32> %partial.reduce29}30 31define void @udot_vl256(ptr %accptr, ptr %aptr, ptr %bptr) vscale_range(2,2) {32; CHECK-LABEL: udot_vl256:33; CHECK: // %bb.0: // %entry34; CHECK-NEXT: ldr z0, [x0]35; CHECK-NEXT: ldr z1, [x1]36; CHECK-NEXT: ldr z2, [x2]37; CHECK-NEXT: udot z0.s, z1.h, z2.h38; CHECK-NEXT: str z0, [x0]39; CHECK-NEXT: ret40entry:41 %acc = load <8 x i32>, ptr %accptr42 %a = load <16 x i16>, ptr %aptr43 %b = load <16 x i16>, ptr %bptr44 %a.wide = zext <16 x i16> %a to <16 x i32>45 %b.wide = zext <16 x i16> %b to <16 x i32>46 %mult = mul nuw nsw <16 x i32> %a.wide, %b.wide47 %partial.reduce = tail call <8 x i32> @llvm.vector.partial.reduce.add(<8 x i32> %acc, <16 x i32> %mult)48 store <8 x i32> %partial.reduce, ptr %accptr49 ret void50}51 52define void @sdot_vl256(ptr %accptr, ptr %aptr, ptr %bptr) vscale_range(2,2) {53; CHECK-LABEL: sdot_vl256:54; CHECK: // %bb.0: // %entry55; CHECK-NEXT: ldr z0, [x0]56; CHECK-NEXT: ldr z1, [x1]57; CHECK-NEXT: ldr z2, [x2]58; CHECK-NEXT: sdot z0.s, z1.h, z2.h59; CHECK-NEXT: str z0, [x0]60; CHECK-NEXT: ret61entry:62 %acc = load <8 x i32>, ptr %accptr63 %a = load <16 x i16>, ptr %aptr64 %b = load <16 x i16>, ptr %bptr65 %a.wide = sext <16 x i16> %a to <16 x i32>66 %b.wide = sext <16 x i16> %b to <16 x i32>67 %mult = mul nuw nsw <16 x i32> %a.wide, %b.wide68 %partial.reduce = tail call <8 x i32> @llvm.vector.partial.reduce.add(<8 x i32> %acc, <16 x i32> %mult)69 store <8 x i32> %partial.reduce, ptr %accptr70 ret void71}72 73define <4 x i32> @fixed_udot_s_h(<4 x i32> %acc, <8 x i16> %a, <8 x i16> %b) {74; CHECK-LABEL: fixed_udot_s_h:75; CHECK: // %bb.0: // %entry76; CHECK-NEXT: // kill: def $q0 killed $q0 def $z077; CHECK-NEXT: // kill: def $q2 killed $q2 def $z278; CHECK-NEXT: // kill: def $q1 killed $q1 def $z179; CHECK-NEXT: udot z0.s, z1.h, z2.h80; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z081; CHECK-NEXT: ret82entry:83 %a.wide = zext <8 x i16> %a to <8 x i32>84 %b.wide = zext <8 x i16> %b to <8 x i32>85 %mult = mul nuw nsw <8 x i32> %a.wide, %b.wide86 %partial.reduce = tail call <4 x i32> @llvm.vector.partial.reduce.add(<4 x i32> %acc, <8 x i32> %mult)87 ret <4 x i32> %partial.reduce88}89 90define <4 x i32> @fixed_sdot_s_h(<4 x i32> %acc, <8 x i16> %a, <8 x i16> %b) {91; CHECK-LABEL: fixed_sdot_s_h:92; CHECK: // %bb.0: // %entry93; CHECK-NEXT: // kill: def $q0 killed $q0 def $z094; CHECK-NEXT: // kill: def $q2 killed $q2 def $z295; CHECK-NEXT: // kill: def $q1 killed $q1 def $z196; CHECK-NEXT: sdot z0.s, z1.h, z2.h97; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z098; CHECK-NEXT: ret99entry:100 %a.wide = sext <8 x i16> %a to <8 x i32>101 %b.wide = sext <8 x i16> %b to <8 x i32>102 %mult = mul nuw nsw <8 x i32> %a.wide, %b.wide103 %partial.reduce = tail call <4 x i32> @llvm.vector.partial.reduce.add(<4 x i32> %acc, <8 x i32> %mult)104 ret <4 x i32> %partial.reduce105}106