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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 62; RUN: llc -mattr=+sve2 < %s | FileCheck %s --check-prefixes=CHECK,SVE23; RUN: llc -global-isel -global-isel-abort=2 -mattr=+sve2 < %s | FileCheck %s --check-prefixes=CHECK,SVE24; RUN: llc -mattr=+sve2p1 < %s | FileCheck %s --check-prefixes=CHECK,SVE2P15; RUN: llc -global-isel -global-isel-abort=2 -mattr=+sve2p1 < %s | FileCheck %s --check-prefixes=CHECK,SVE2P16 7target triple = "aarch64-linux-gnu"8 9define <vscale x 4 x float> @fdot_wide_nxv4f32(<vscale x 4 x float> %acc, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {10; SVE2-LABEL: fdot_wide_nxv4f32:11; SVE2: // %bb.0: // %entry12; SVE2-NEXT: uunpklo z3.s, z1.h13; SVE2-NEXT: uunpklo z4.s, z2.h14; SVE2-NEXT: ptrue p0.s15; SVE2-NEXT: uunpkhi z1.s, z1.h16; SVE2-NEXT: uunpkhi z2.s, z2.h17; SVE2-NEXT: fcvt z3.s, p0/m, z3.h18; SVE2-NEXT: fcvt z4.s, p0/m, z4.h19; SVE2-NEXT: fcvt z1.s, p0/m, z1.h20; SVE2-NEXT: fcvt z2.s, p0/m, z2.h21; SVE2-NEXT: fmul z3.s, z3.s, z4.s22; SVE2-NEXT: fmul z1.s, z1.s, z2.s23; SVE2-NEXT: fadd z0.s, z0.s, z3.s24; SVE2-NEXT: fadd z0.s, z0.s, z1.s25; SVE2-NEXT: ret26;27; SVE2P1-LABEL: fdot_wide_nxv4f32:28; SVE2P1: // %bb.0: // %entry29; SVE2P1-NEXT: fdot z0.s, z1.h, z2.h30; SVE2P1-NEXT: ret31entry:32 %a.wide = fpext <vscale x 8 x half> %a to <vscale x 8 x float>33 %b.wide = fpext <vscale x 8 x half> %b to <vscale x 8 x float>34 %mult = fmul <vscale x 8 x float> %a.wide, %b.wide35 %partial.reduce = call <vscale x 4 x float> @llvm.vector.partial.reduce.fadd(<vscale x 4 x float> %acc, <vscale x 8 x float> %mult)36 ret <vscale x 4 x float> %partial.reduce37}38 39define <vscale x 4 x float> @fdot_splat_nxv4f32(<vscale x 4 x float> %acc, <vscale x 8 x half> %a) {40; SVE2-LABEL: fdot_splat_nxv4f32:41; SVE2: // %bb.0: // %entry42; SVE2-NEXT: uunpklo z2.s, z1.h43; SVE2-NEXT: ptrue p0.s44; SVE2-NEXT: uunpkhi z1.s, z1.h45; SVE2-NEXT: fcvt z2.s, p0/m, z2.h46; SVE2-NEXT: fcvt z1.s, p0/m, z1.h47; SVE2-NEXT: fadd z0.s, z0.s, z2.s48; SVE2-NEXT: fadd z0.s, z0.s, z1.s49; SVE2-NEXT: ret50;51; SVE2P1-LABEL: fdot_splat_nxv4f32:52; SVE2P1: // %bb.0: // %entry53; SVE2P1-NEXT: fmov z2.h, #1.0000000054; SVE2P1-NEXT: fdot z0.s, z1.h, z2.h55; SVE2P1-NEXT: ret56entry:57 %a.wide = fpext <vscale x 8 x half> %a to <vscale x 8 x float>58 %partial.reduce = call <vscale x 4 x float> @llvm.vector.partial.reduce.fadd(<vscale x 4 x float> %acc, <vscale x 8 x float> %a.wide)59 ret <vscale x 4 x float> %partial.reduce60}61 62define <vscale x 8 x half> @partial_reduce_nxv8f16(<vscale x 8 x half> %acc, <vscale x 16 x half> %a) {63; CHECK-LABEL: partial_reduce_nxv8f16:64; CHECK: // %bb.0: // %entry65; CHECK-NEXT: fadd z0.h, z0.h, z1.h66; CHECK-NEXT: fadd z0.h, z0.h, z2.h67; CHECK-NEXT: ret68entry:69 %partial.reduce = call <vscale x 8 x half> @llvm.vector.partial.reduce.fadd(<vscale x 8 x half> %acc, <vscale x 16 x half> %a)70 ret <vscale x 8 x half> %partial.reduce71}72 73define <vscale x 4 x float> @partial_reduce_nxv4f32(<vscale x 4 x float> %acc, <vscale x 8 x float> %a) {74; CHECK-LABEL: partial_reduce_nxv4f32:75; CHECK: // %bb.0: // %entry76; CHECK-NEXT: fadd z0.s, z0.s, z1.s77; CHECK-NEXT: fadd z0.s, z0.s, z2.s78; CHECK-NEXT: ret79entry:80 %partial.reduce = call <vscale x 4 x float> @llvm.vector.partial.reduce.fadd(<vscale x 4 x float> %acc, <vscale x 8 x float> %a)81 ret <vscale x 4 x float> %partial.reduce82}83 84define <vscale x 2 x double> @partial_reduce_nxv2f64(<vscale x 2 x double> %acc, <vscale x 4 x double> %a) {85; CHECK-LABEL: partial_reduce_nxv2f64:86; CHECK: // %bb.0: // %entry87; CHECK-NEXT: fadd z0.d, z0.d, z1.d88; CHECK-NEXT: fadd z0.d, z0.d, z2.d89; CHECK-NEXT: ret90entry:91 %partial.reduce = call <vscale x 2 x double> @llvm.vector.partial.reduce.fadd(<vscale x 2 x double> %acc, <vscale x 4 x double> %a)92 ret <vscale x 2 x double> %partial.reduce93}94