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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1 -mattr=+sve-b16b16 -mattr=+use-experimental-zeroing-pseudos -verify-machineinstrs < %s \3; RUN: | FileCheck %s4 5define <vscale x 8 x bfloat> @bfminnm_pred(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b){6; CHECK-LABEL: bfminnm_pred:7; CHECK: // %bb.0:8; CHECK-NEXT: bfminnm z0.h, p0/m, z0.h, z1.h9; CHECK-NEXT: ret10 %res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.nxv8bf16(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)11 ret <vscale x 8 x bfloat> %res12}13 14define <vscale x 8 x bfloat> @bfminnm(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b){15; CHECK-LABEL: bfminnm:16; CHECK: // %bb.0:17; CHECK-NEXT: ptrue p0.h18; CHECK-NEXT: bfminnm z0.h, p0/m, z0.h, z1.h19; CHECK-NEXT: ret20 %elt = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)21 %res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.nxv8bf16(<vscale x 8 x i1> %elt, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)22 ret <vscale x 8 x bfloat> %res23}24 25define <vscale x 8 x bfloat> @bfminnm_zeroing(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) {26; CHECK-LABEL: bfminnm_zeroing:27; CHECK: // %bb.0:28; CHECK-NEXT: movprfx z0.h, p0/z, z0.h29; CHECK-NEXT: bfminnm z0.h, p0/m, z0.h, z1.h30; CHECK-NEXT: ret31 %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> zeroinitializer32 %out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.nxv8bf16(<vscale x 8 x i1> %pg,33 <vscale x 8 x bfloat> %a_z,34 <vscale x 8 x bfloat> %b)35 ret <vscale x 8 x bfloat> %out36}37 38define <vscale x 8 x bfloat> @bfminnm_u_pred(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b){39; CHECK-LABEL: bfminnm_u_pred:40; CHECK: // %bb.0:41; CHECK-NEXT: bfminnm z0.h, p0/m, z0.h, z1.h42; CHECK-NEXT: ret43 %res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.u.nxv8bf16(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)44 ret <vscale x 8 x bfloat> %res45}46 47define <vscale x 8 x bfloat> @bfminnm_u(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b){48; CHECK-LABEL: bfminnm_u:49; CHECK: // %bb.0:50; CHECK-NEXT: ptrue p0.h51; CHECK-NEXT: bfminnm z0.h, p0/m, z0.h, z1.h52; CHECK-NEXT: ret53 %elt = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)54 %res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.u.nxv8bf16(<vscale x 8 x i1> %elt, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)55 ret <vscale x 8 x bfloat> %res56}57 58define <vscale x 8 x bfloat> @bfminnm_u_zeroing(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) {59; CHECK-LABEL: bfminnm_u_zeroing:60; CHECK: // %bb.0:61; CHECK-NEXT: movi v2.2d, #000000000000000062; CHECK-NEXT: sel z0.h, p0, z0.h, z2.h63; CHECK-NEXT: bfminnm z0.h, p0/m, z0.h, z1.h64; CHECK-NEXT: ret65 %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> zeroinitializer66 %out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.u.nxv8bf16(<vscale x 8 x i1> %pg,67 <vscale x 8 x bfloat> %a_z,68 <vscale x 8 x bfloat> %b)69 ret <vscale x 8 x bfloat> %out70}71 72declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)73declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fminnm.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)74declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 immarg)75