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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1 -mattr=+sve-b16b16 -mattr=+use-experimental-zeroing-pseudos -verify-machineinstrs < %s \3; RUN: | FileCheck %s4 5define <vscale x 8 x bfloat> @bfmul_pred(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b){6; CHECK-LABEL: bfmul_pred:7; CHECK: // %bb.0:8; CHECK-NEXT: bfmul z0.h, p0/m, z0.h, z1.h9; CHECK-NEXT: ret10 %res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.nxv8bf16(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)11 ret <vscale x 8 x bfloat> %res12}13 14define <vscale x 8 x bfloat> @bfmul_zeroing(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) {15; CHECK-LABEL: bfmul_zeroing:16; CHECK: // %bb.0:17; CHECK-NEXT: movprfx z0.h, p0/z, z0.h18; CHECK-NEXT: bfmul z0.h, p0/m, z0.h, z1.h19; CHECK-NEXT: ret20 %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> zeroinitializer21 %out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.nxv8bf16(<vscale x 8 x i1> %pg,22 <vscale x 8 x bfloat> %a_z,23 <vscale x 8 x bfloat> %b)24 ret <vscale x 8 x bfloat> %out25}26 27define <vscale x 8 x bfloat> @bfmul_u_pred(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b){28; CHECK-LABEL: bfmul_u_pred:29; CHECK: // %bb.0:30; CHECK-NEXT: bfmul z0.h, p0/m, z0.h, z1.h31; CHECK-NEXT: ret32 %res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.u.nxv8bf16(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)33 ret <vscale x 8 x bfloat> %res34}35 36define <vscale x 8 x bfloat> @bfmul_u(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b){37; CHECK-LABEL: bfmul_u:38; CHECK: // %bb.0:39; CHECK-NEXT: bfmul z0.h, z0.h, z1.h40; CHECK-NEXT: ret41 %elt = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)42 %res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.u.nxv8bf16(<vscale x 8 x i1> %elt, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b)43 ret <vscale x 8 x bfloat> %res44}45 46define <vscale x 8 x bfloat> @bfmul_u_zeroing(<vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) {47; CHECK-LABEL: bfmul_u_zeroing:48; CHECK: // %bb.0:49; CHECK-NEXT: movi v2.2d, #000000000000000050; CHECK-NEXT: sel z0.h, p0, z0.h, z2.h51; CHECK-NEXT: bfmul z0.h, p0/m, z0.h, z1.h52; CHECK-NEXT: ret53 %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> zeroinitializer54 %out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.u.nxv8bf16(<vscale x 8 x i1> %pg,55 <vscale x 8 x bfloat> %a_z,56 <vscale x 8 x bfloat> %b)57 ret <vscale x 8 x bfloat> %out58}59 60declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)61declare <vscale x 8 x bfloat> @llvm.aarch64.sve.fmul.u.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)62declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 immarg)63