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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1 < %s | FileCheck %s3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme2 < %s | FileCheck %s4; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -force-streaming < %s | FileCheck %s5; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme,+sve2p1 -force-streaming < %s | FileCheck %s6 7define <vscale x 4 x i32> @sdot_x2(<vscale x 4 x i32> %zda, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) {8; CHECK-LABEL: sdot_x2:9; CHECK: // %bb.0:10; CHECK-NEXT: sdot z0.s, z1.h, z2.h11; CHECK-NEXT: ret12 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.x2.nxv4i32(<vscale x 4 x i32> %zda, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)13 ret <vscale x 4 x i32> %out14}15 16define <vscale x 4 x i32> @udot_x2(<vscale x 4 x i32> %zda, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) {17; CHECK-LABEL: udot_x2:18; CHECK: // %bb.0:19; CHECK-NEXT: udot z0.s, z1.h, z2.h20; CHECK-NEXT: ret21 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.udot.x2.nxv4i32(<vscale x 4 x i32> %zda, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)22 ret <vscale x 4 x i32> %out23}24 25define <vscale x 4 x float> @fdot_x2(<vscale x 4 x float> %zda, <vscale x 8 x half> %zn, <vscale x 8 x half> %zm) {26; CHECK-LABEL: fdot_x2:27; CHECK: // %bb.0:28; CHECK-NEXT: fdot z0.s, z1.h, z2.h29; CHECK-NEXT: ret30 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fdot.x2.nxv4f32(<vscale x 4 x float> %zda, <vscale x 8 x half> %zn, <vscale x 8 x half> %zm)31 ret <vscale x 4 x float> %out32}33 34define <vscale x 4 x i32> @sdot_lane_x2(<vscale x 4 x i32> %zda, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) {35; CHECK-LABEL: sdot_lane_x2:36; CHECK: // %bb.0:37; CHECK-NEXT: sdot z0.s, z1.h, z2.h[3]38; CHECK-NEXT: ret39 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.lane.x2.nxv4i32(<vscale x 4 x i32> %zda, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm, i32 3)40 ret <vscale x 4 x i32> %out41}42 43define <vscale x 4 x i32> @udot_lane_x2(<vscale x 4 x i32> %zda, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) {44; CHECK-LABEL: udot_lane_x2:45; CHECK: // %bb.0:46; CHECK-NEXT: udot z0.s, z1.h, z2.h[3]47; CHECK-NEXT: ret48 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.udot.lane.x2.nxv4i32(<vscale x 4 x i32> %zda, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm, i32 3)49 ret <vscale x 4 x i32> %out50}51 52define <vscale x 4 x float> @fdot_lane_x2(<vscale x 4 x float> %zda, <vscale x 8 x half> %zn, <vscale x 8 x half> %zm) {53; CHECK-LABEL: fdot_lane_x2:54; CHECK: // %bb.0:55; CHECK-NEXT: fdot z0.s, z1.h, z2.h[3]56; CHECK-NEXT: ret57 %out = call <vscale x 4 x float> @llvm.aarch64.sve.fdot.lane.x2.nxv4f32(<vscale x 4 x float> %zda, <vscale x 8 x half> %zn, <vscale x 8 x half> %zm, i32 3)58 ret <vscale x 4 x float> %out59}60 61 62declare <vscale x 4 x i32> @llvm.aarch64.sve.sdot.x2.nxv4i32(<vscale x 4 x i32> %zda, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)63declare <vscale x 4 x i32> @llvm.aarch64.sve.udot.x2.nxv4i32(<vscale x 4 x i32> %zda, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)64declare <vscale x 4 x float> @llvm.aarch64.sve.fdot.x2.nxv4f32(<vscale x 4 x float> %zda, <vscale x 8 x half> %zn, <vscale x 8 x half> %zm)65declare <vscale x 4 x i32> @llvm.aarch64.sve.sdot.lane.x2.nxv4i32(<vscale x 4 x i32> %zda, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm, i32)66declare <vscale x 4 x i32> @llvm.aarch64.sve.udot.lane.x2.nxv4i32(<vscale x 4 x i32> %zda, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm, i32)67declare <vscale x 4 x float> @llvm.aarch64.sve.fdot.lane.x2.nxv4f32(<vscale x 4 x float> %zda, <vscale x 8 x half> %zn, <vscale x 8 x half> %zm, i32)68