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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve2p1 < %s | FileCheck %s3; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve,+sme2p1 < %s | FileCheck %s4; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sme2p1 -force-streaming < %s | FileCheck %s5; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sme,+sve2p1 -force-streaming < %s | FileCheck %s6 7define <vscale x 16 x i8> @test_dupq_i8 (<vscale x 16 x i8> %zn) {8; CHECK-LABEL: test_dupq_i8:9; CHECK: // %bb.0:10; CHECK-NEXT: dupq z0.b, z0.b[15]11; CHECK-NEXT: ret12 %res = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.laneq.nxv16i8(<vscale x 16 x i8> %zn, i32 15)13 ret <vscale x 16 x i8> %res14}15 16define <vscale x 8 x i16> @test_dupq_i16 (<vscale x 8 x i16> %zn) {17; CHECK-LABEL: test_dupq_i16:18; CHECK: // %bb.0:19; CHECK-NEXT: dupq z0.h, z0.h[7]20; CHECK-NEXT: ret21 %res = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.laneq.nxv8i16(<vscale x 8 x i16> %zn, i32 7)22 ret <vscale x 8 x i16> %res23}24 25define <vscale x 4 x i32> @test_dupq__i32 (<vscale x 4 x i32> %zn) {26; CHECK-LABEL: test_dupq__i32:27; CHECK: // %bb.0:28; CHECK-NEXT: dupq z0.s, z0.s[3]29; CHECK-NEXT: ret30 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.laneq.nxv4i32(<vscale x 4 x i32> %zn, i32 3)31 ret <vscale x 4 x i32> %res32}33 34define <vscale x 2 x i64> @test_dupq_i64 (<vscale x 2 x i64> %zn) {35; CHECK-LABEL: test_dupq_i64:36; CHECK: // %bb.0:37; CHECK-NEXT: dupq z0.d, z0.d[1]38; CHECK-NEXT: ret39 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.laneq.nxv2i64(<vscale x 2 x i64> %zn, i32 1)40 ret <vscale x 2 x i64> %res41}42 43define <vscale x 8 x half> @test_dupq_f16(<vscale x 8 x half> %zn) {44; CHECK-LABEL: test_dupq_f16:45; CHECK: // %bb.0:46; CHECK-NEXT: dupq z0.h, z0.h[4]47; CHECK-NEXT: ret48 %res = call <vscale x 8 x half> @llvm.aarch64.sve.dup.laneq.nxv8f16(<vscale x 8 x half> %zn, i32 4)49 ret <vscale x 8 x half> %res50}51 52define <vscale x 4 x float> @test_dupq_f32(<vscale x 4 x float> %zn) {53; CHECK-LABEL: test_dupq_f32:54; CHECK: // %bb.0:55; CHECK-NEXT: dupq z0.s, z0.s[2]56; CHECK-NEXT: ret57 %res = call <vscale x 4 x float> @llvm.aarch64.sve.dup.laneq.nxv4f32(<vscale x 4 x float> %zn, i32 2)58 ret <vscale x 4 x float> %res59}60 61define <vscale x 2 x double> @test_dupq_f64(<vscale x 2 x double> %zn) {62; CHECK-LABEL: test_dupq_f64:63; CHECK: // %bb.0:64; CHECK-NEXT: dupq z0.d, z0.d[0]65; CHECK-NEXT: ret66 %res = call <vscale x 2 x double> @llvm.aarch64.sve.dup.laneq.nxv2f64(<vscale x 2 x double> %zn, i32 0)67 ret <vscale x 2 x double> %res68}69 70define <vscale x 8 x bfloat> @test_dupq_bf16(<vscale x 8 x bfloat> %zn) {71; CHECK-LABEL: test_dupq_bf16:72; CHECK: // %bb.0:73; CHECK-NEXT: dupq z0.h, z0.h[1]74; CHECK-NEXT: ret75 %res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.dup.laneq.nxv8bf16(<vscale x 8 x bfloat> %zn, i32 1)76 ret <vscale x 8 x bfloat> %res77}78 79declare <vscale x 16 x i8> @llvm.aarch64.sve.dup.laneq.nxv16i8(<vscale x 16 x i8>, i32)80declare <vscale x 8 x i16> @llvm.aarch64.sve.dup.laneq.nxv8i16(<vscale x 8 x i16>, i32)81declare <vscale x 4 x i32> @llvm.aarch64.sve.dup.laneq.nxv4i32(<vscale x 4 x i32>, i32)82declare <vscale x 2 x i64> @llvm.aarch64.sve.dup.laneq.nxv2i64(<vscale x 2 x i64>, i32)83declare <vscale x 8 x half> @llvm.aarch64.sve.dup.laneq.nxv8f16(<vscale x 8 x half>, i32)84declare <vscale x 4 x float> @llvm.aarch64.sve.dup.laneq.nxv4f32(<vscale x 4 x float>, i32)85declare <vscale x 2 x double> @llvm.aarch64.sve.dup.laneq.nxv2f64(<vscale x 2 x double>, i32)86declare <vscale x 8 x bfloat> @llvm.aarch64.sve.dup.laneq.nxv8bf16(<vscale x 8 x bfloat>, i32)87