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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve2p1 < %s | FileCheck %s3; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve,+sme2p1 < %s | FileCheck %s4; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sme2p1 -force-streaming < %s | FileCheck %s5; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sme,+sve2p1 -force-streaming < %s | FileCheck %s6 7;8; FMAXNMQV9;10 11define <8 x half> @fmaxnmqv_f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {12; CHECK-LABEL: fmaxnmqv_f16:13; CHECK: // %bb.0:14; CHECK-NEXT: fmaxnmqv v0.8h, p0, z0.h15; CHECK-NEXT: ret16 %res = call <8 x half> @llvm.aarch64.sve.fmaxnmqv.v8f16.nxv8f16(<vscale x 8 x i1> %pg,17 <vscale x 8 x half> %a)18 ret <8 x half> %res19}20 21define <4 x float> @fmaxnmqv_f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {22; CHECK-LABEL: fmaxnmqv_f32:23; CHECK: // %bb.0:24; CHECK-NEXT: fmaxnmqv v0.4s, p0, z0.s25; CHECK-NEXT: ret26 %res = call <4 x float> @llvm.aarch64.sve.fmaxnmqv.v4f32.nxv4f32(<vscale x 4 x i1> %pg,27 <vscale x 4 x float> %a)28 ret <4 x float> %res29}30 31define <2 x double> @fmaxnmqv_f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {32; CHECK-LABEL: fmaxnmqv_f64:33; CHECK: // %bb.0:34; CHECK-NEXT: fmaxnmqv v0.2d, p0, z0.d35; CHECK-NEXT: ret36 %res = call <2 x double> @llvm.aarch64.sve.fmaxnmqv.v2f64.nxv2f64(<vscale x 2 x i1> %pg,37 <vscale x 2 x double> %a)38 ret <2 x double> %res39}40 41;42; FMINNMQV43;44 45define <8 x half> @fminnmqv_f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {46; CHECK-LABEL: fminnmqv_f16:47; CHECK: // %bb.0:48; CHECK-NEXT: fminnmqv v0.8h, p0, z0.h49; CHECK-NEXT: ret50 %res = call <8 x half> @llvm.aarch64.sve.fminnmqv.v8f16.nxv8f16(<vscale x 8 x i1> %pg,51 <vscale x 8 x half> %a)52 ret <8 x half> %res53}54 55define <4 x float> @fminnmqv_f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {56; CHECK-LABEL: fminnmqv_f32:57; CHECK: // %bb.0:58; CHECK-NEXT: fminnmqv v0.4s, p0, z0.s59; CHECK-NEXT: ret60 %res = call <4 x float> @llvm.aarch64.sve.fminnmqv.v4f32.nxv4f32(<vscale x 4 x i1> %pg,61 <vscale x 4 x float> %a)62 ret <4 x float> %res63}64 65define <2 x double> @fminnmqv_f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {66; CHECK-LABEL: fminnmqv_f64:67; CHECK: // %bb.0:68; CHECK-NEXT: fminnmqv v0.2d, p0, z0.d69; CHECK-NEXT: ret70 %res = call <2 x double> @llvm.aarch64.sve.fminnmqv.v2f64.nxv2f64(<vscale x 2 x i1> %pg,71 <vscale x 2 x double> %a)72 ret <2 x double> %res73}74 75;76; FADDQV77;78 79define <8 x half> @faddqv_f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {80; CHECK-LABEL: faddqv_f16:81; CHECK: // %bb.0:82; CHECK-NEXT: faddqv v0.8h, p0, z0.h83; CHECK-NEXT: ret84 %res = call <8 x half> @llvm.aarch64.sve.addqv.v8f16.nxv8f16(<vscale x 8 x i1> %pg,85 <vscale x 8 x half> %a)86 ret <8 x half> %res87}88 89define <4 x float> @faddqv_f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {90; CHECK-LABEL: faddqv_f32:91; CHECK: // %bb.0:92; CHECK-NEXT: faddqv v0.4s, p0, z0.s93; CHECK-NEXT: ret94 %res = call <4 x float> @llvm.aarch64.sve.addqv.v4f32.nxv4f32(<vscale x 4 x i1> %pg,95 <vscale x 4 x float> %a)96 ret <4 x float> %res97}98 99define <2 x double> @faddqv_f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {100; CHECK-LABEL: faddqv_f64:101; CHECK: // %bb.0:102; CHECK-NEXT: faddqv v0.2d, p0, z0.d103; CHECK-NEXT: ret104 %res = call <2 x double> @llvm.aarch64.sve.addqv.v2f64.nxv2f64(<vscale x 2 x i1> %pg,105 <vscale x 2 x double> %a)106 ret <2 x double> %res107}108 109;110; FMINQV111;112 113define <8 x half> @fminqv_f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {114; CHECK-LABEL: fminqv_f16:115; CHECK: // %bb.0:116; CHECK-NEXT: fminqv v0.8h, p0, z0.h117; CHECK-NEXT: ret118 %res = call <8 x half> @llvm.aarch64.sve.fminqv.v8f16.nxv8f16(<vscale x 8 x i1> %pg,119 <vscale x 8 x half> %a)120 ret <8 x half> %res121}122 123define <4 x float> @fminqv_f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {124; CHECK-LABEL: fminqv_f32:125; CHECK: // %bb.0:126; CHECK-NEXT: fminqv v0.4s, p0, z0.s127; CHECK-NEXT: ret128 %res = call <4 x float> @llvm.aarch64.sve.fminqv.v4f32.nxv4f32(<vscale x 4 x i1> %pg,129 <vscale x 4 x float> %a)130 ret <4 x float> %res131}132 133define <2 x double> @fminqv_f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {134; CHECK-LABEL: fminqv_f64:135; CHECK: // %bb.0:136; CHECK-NEXT: fminqv v0.2d, p0, z0.d137; CHECK-NEXT: ret138 %res = call <2 x double> @llvm.aarch64.sve.fminqv.v2f64.nxv2f64(<vscale x 2 x i1> %pg,139 <vscale x 2 x double> %a)140 ret <2 x double> %res141}142 143;144; FMAXQV145;146 147define <8 x half> @fmaxqv_f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {148; CHECK-LABEL: fmaxqv_f16:149; CHECK: // %bb.0:150; CHECK-NEXT: fmaxqv v0.8h, p0, z0.h151; CHECK-NEXT: ret152 %res = call <8 x half> @llvm.aarch64.sve.fmaxqv.v8f16.nxv8f16(<vscale x 8 x i1> %pg,153 <vscale x 8 x half> %a)154 ret <8 x half> %res155}156 157define <4 x float> @fmaxqv_f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {158; CHECK-LABEL: fmaxqv_f32:159; CHECK: // %bb.0:160; CHECK-NEXT: fmaxqv v0.4s, p0, z0.s161; CHECK-NEXT: ret162 %res = call <4 x float> @llvm.aarch64.sve.fmaxqv.v4f32.nxv4f32(<vscale x 4 x i1> %pg,163 <vscale x 4 x float> %a)164 ret <4 x float> %res165}166 167define <2 x double> @fmaxqv_f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {168; CHECK-LABEL: fmaxqv_f64:169; CHECK: // %bb.0:170; CHECK-NEXT: fmaxqv v0.2d, p0, z0.d171; CHECK-NEXT: ret172 %res = call <2 x double> @llvm.aarch64.sve.fmaxqv.v2f64.nxv2f64(<vscale x 2 x i1> %pg,173 <vscale x 2 x double> %a)174 ret <2 x double> %res175}176 177declare <8 x half> @llvm.aarch64.sve.fmaxnmqv.v8f16.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>)178declare <4 x float> @llvm.aarch64.sve.fmaxnmqv.v4f32.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>)179declare <2 x double> @llvm.aarch64.sve.fmaxnmqv.v2f64.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>)180declare <8 x half> @llvm.aarch64.sve.fminnmqv.v8f16.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>)181declare <4 x float> @llvm.aarch64.sve.fminnmqv.v4f32.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>)182declare <2 x double> @llvm.aarch64.sve.fminnmqv.v2f64.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>)183declare <8 x half> @llvm.aarch64.sve.addqv.v8f16.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>)184declare <4 x float> @llvm.aarch64.sve.addqv.v4f32.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>)185declare <2 x double> @llvm.aarch64.sve.addqv.v2f64.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>)186declare <8 x half> @llvm.aarch64.sve.fminqv.v8f16.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>)187declare <4 x float> @llvm.aarch64.sve.fminqv.v4f32.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>)188declare <2 x double> @llvm.aarch64.sve.fminqv.v2f64.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>)189declare <8 x half> @llvm.aarch64.sve.fmaxqv.v8f16.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>)190declare <4 x float> @llvm.aarch64.sve.fmaxqv.v4f32.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>)191declare <2 x double> @llvm.aarch64.sve.fmaxqv.v2f64.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>)192