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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 32; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1,+bf16 < %s | FileCheck %s3 4declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2i64.nxv2i64(<vscale x 1 x i1>, <vscale x 2 x i64>, i64)5declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv4i32.nxv2i64(<vscale x 1 x i1>, <vscale x 2 x i64>, i64)6declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv8i16.nxv2i64(<vscale x 1 x i1>, <vscale x 2 x i64>, i64)7declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv16i8.nxv2i64(<vscale x 1 x i1>, <vscale x 2 x i64>, i64)8declare <vscale x 2 x double> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2f64.nxv2i64(<vscale x 1 x i1>, <vscale x 2 x i64>, i64)9declare <vscale x 4 x float> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv4f32.nxv2i64(<vscale x 1 x i1>, <vscale x 2 x i64>, i64)10declare <vscale x 8 x half> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv8f16.nxv2i64(<vscale x 1 x i1>, <vscale x 2 x i64>, i64)11declare <vscale x 8 x bfloat> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv8bf16.nxv2i64(<vscale x 1 x i1>, <vscale x 2 x i64>, i64)12declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1q.gather.index.nxv4i32(<vscale x 1 x i1>, ptr, <vscale x 2 x i64>)13declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1q.gather.index.nxv8i16(<vscale x 1 x i1>, ptr, <vscale x 2 x i64>)14declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1q.gather.index.nxv2i64(<vscale x 1 x i1>, ptr, <vscale x 2 x i64>)15declare <vscale x 8 x bfloat> @llvm.aarch64.sve.ld1q.gather.index.nxv8bf16(<vscale x 1 x i1>, ptr, <vscale x 2 x i64>)16declare <vscale x 8 x half> @llvm.aarch64.sve.ld1q.gather.index.nxv8f16(<vscale x 1 x i1>, ptr, <vscale x 2 x i64>)17declare <vscale x 4 x float> @llvm.aarch64.sve.ld1q.gather.index.nxv4f32(<vscale x 1 x i1>, ptr, <vscale x 2 x i64>)18declare <vscale x 2 x double> @llvm.aarch64.sve.ld1q.gather.index.nxv2f64(<vscale x 1 x i1>, ptr, <vscale x 2 x i64>)19 20define <vscale x 8 x i16> @test_svld1q_gather_u64index_s16(<vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx) {21; CHECK-LABEL: test_svld1q_gather_u64index_s16:22; CHECK: // %bb.0: // %entry23; CHECK-NEXT: lsl z0.d, z0.d, #124; CHECK-NEXT: ld1q { z0.q }, p0/z, [z0.d, x0]25; CHECK-NEXT: ret26entry:27 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.ld1q.gather.index.nxv8i16(<vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx)28 ret <vscale x 8 x i16> %029}30 31define <vscale x 8 x i16> @test_svld1q_gather_u64index_u16(<vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx) {32; CHECK-LABEL: test_svld1q_gather_u64index_u16:33; CHECK: // %bb.0: // %entry34; CHECK-NEXT: lsl z0.d, z0.d, #135; CHECK-NEXT: ld1q { z0.q }, p0/z, [z0.d, x0]36; CHECK-NEXT: ret37entry:38 %0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.ld1q.gather.index.nxv8i16(<vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx)39 ret <vscale x 8 x i16> %040}41 42define <vscale x 4 x i32> @test_svld1q_gather_u64index_s32(<vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx) {43; CHECK-LABEL: test_svld1q_gather_u64index_s32:44; CHECK: // %bb.0: // %entry45; CHECK-NEXT: lsl z0.d, z0.d, #246; CHECK-NEXT: ld1q { z0.q }, p0/z, [z0.d, x0]47; CHECK-NEXT: ret48entry:49 %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.ld1q.gather.index.nxv4i32(<vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx)50 ret <vscale x 4 x i32> %051}52 53define <vscale x 4 x i32> @test_svld1q_gather_u64index_u32(<vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx) {54; CHECK-LABEL: test_svld1q_gather_u64index_u32:55; CHECK: // %bb.0: // %entry56; CHECK-NEXT: lsl z0.d, z0.d, #257; CHECK-NEXT: ld1q { z0.q }, p0/z, [z0.d, x0]58; CHECK-NEXT: ret59entry:60 %0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.ld1q.gather.index.nxv4i32(<vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx)61 ret <vscale x 4 x i32> %062}63 64define <vscale x 2 x i64> @test_svld1q_gather_u64index_s64(<vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx) {65; CHECK-LABEL: test_svld1q_gather_u64index_s64:66; CHECK: // %bb.0: // %entry67; CHECK-NEXT: lsl z0.d, z0.d, #368; CHECK-NEXT: ld1q { z0.q }, p0/z, [z0.d, x0]69; CHECK-NEXT: ret70entry:71 %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.ld1q.gather.index.nxv2i64(<vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx)72 ret <vscale x 2 x i64> %073}74 75define <vscale x 2 x i64> @test_svld1q_gather_u64index_u64(<vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx) {76; CHECK-LABEL: test_svld1q_gather_u64index_u64:77; CHECK: // %bb.0: // %entry78; CHECK-NEXT: lsl z0.d, z0.d, #379; CHECK-NEXT: ld1q { z0.q }, p0/z, [z0.d, x0]80; CHECK-NEXT: ret81entry:82 %0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.ld1q.gather.index.nxv2i64(<vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx)83 ret <vscale x 2 x i64> %084}85 86define <vscale x 8 x bfloat> @test_svld1q_gather_u64index_bf16(<vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx) {87; CHECK-LABEL: test_svld1q_gather_u64index_bf16:88; CHECK: // %bb.0: // %entry89; CHECK-NEXT: lsl z0.d, z0.d, #190; CHECK-NEXT: ld1q { z0.q }, p0/z, [z0.d, x0]91; CHECK-NEXT: ret92entry:93 %0 = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.ld1q.gather.index.nxv8bf16(<vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx)94 ret <vscale x 8 x bfloat> %095}96 97define <vscale x 8 x half> @test_svld1q_gather_u64index_f16(<vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx) {98; CHECK-LABEL: test_svld1q_gather_u64index_f16:99; CHECK: // %bb.0: // %entry100; CHECK-NEXT: lsl z0.d, z0.d, #1101; CHECK-NEXT: ld1q { z0.q }, p0/z, [z0.d, x0]102; CHECK-NEXT: ret103entry:104 %0 = tail call <vscale x 8 x half> @llvm.aarch64.sve.ld1q.gather.index.nxv8f16(<vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx)105 ret <vscale x 8 x half> %0106}107 108define <vscale x 4 x float> @test_svld1q_gather_u64index_f32(<vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx) {109; CHECK-LABEL: test_svld1q_gather_u64index_f32:110; CHECK: // %bb.0: // %entry111; CHECK-NEXT: lsl z0.d, z0.d, #2112; CHECK-NEXT: ld1q { z0.q }, p0/z, [z0.d, x0]113; CHECK-NEXT: ret114entry:115 %0 = tail call <vscale x 4 x float> @llvm.aarch64.sve.ld1q.gather.index.nxv4f32(<vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx)116 ret <vscale x 4 x float> %0117}118 119define <vscale x 2 x double> @test_svld1q_gather_u64index_f64(<vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx) {120; CHECK-LABEL: test_svld1q_gather_u64index_f64:121; CHECK: // %bb.0: // %entry122; CHECK-NEXT: lsl z0.d, z0.d, #3123; CHECK-NEXT: ld1q { z0.q }, p0/z, [z0.d, x0]124; CHECK-NEXT: ret125entry:126 %0 = tail call <vscale x 2 x double> @llvm.aarch64.sve.ld1q.gather.index.nxv2f64(<vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx)127 ret <vscale x 2 x double> %0128}129 130define <vscale x 8 x i16> @test_svld1q_gather_u64base_index_s16(<vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %idx) {131; CHECK-LABEL: test_svld1q_gather_u64base_index_s16:132; CHECK: // %bb.0: // %entry133; CHECK-NEXT: lsl x8, x0, #1134; CHECK-NEXT: ld1q { z0.q }, p0/z, [z0.d, x8]135; CHECK-NEXT: ret136entry:137 %0 = shl i64 %idx, 1138 %1 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv8i16.nxv2i64(<vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %0)139 ret <vscale x 8 x i16> %1140}141 142define <vscale x 8 x i16> @test_svld1q_gather_u64base_index_u16(<vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %idx) {143; CHECK-LABEL: test_svld1q_gather_u64base_index_u16:144; CHECK: // %bb.0: // %entry145; CHECK-NEXT: lsl x8, x0, #1146; CHECK-NEXT: ld1q { z0.q }, p0/z, [z0.d, x8]147; CHECK-NEXT: ret148entry:149 %0 = shl i64 %idx, 1150 %1 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv8i16.nxv2i64(<vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %0)151 ret <vscale x 8 x i16> %1152}153 154define <vscale x 4 x i32> @test_svld1q_gather_u64base_index_s32(<vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %idx) {155; CHECK-LABEL: test_svld1q_gather_u64base_index_s32:156; CHECK: // %bb.0: // %entry157; CHECK-NEXT: lsl x8, x0, #2158; CHECK-NEXT: ld1q { z0.q }, p0/z, [z0.d, x8]159; CHECK-NEXT: ret160entry:161 %0 = shl i64 %idx, 2162 %1 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv4i32.nxv2i64(<vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %0)163 ret <vscale x 4 x i32> %1164}165 166define <vscale x 4 x i32> @test_svld1q_gather_u64base_index_u32(<vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %idx) {167; CHECK-LABEL: test_svld1q_gather_u64base_index_u32:168; CHECK: // %bb.0: // %entry169; CHECK-NEXT: lsl x8, x0, #2170; CHECK-NEXT: ld1q { z0.q }, p0/z, [z0.d, x8]171; CHECK-NEXT: ret172entry:173 %0 = shl i64 %idx, 2174 %1 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv4i32.nxv2i64(<vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %0)175 ret <vscale x 4 x i32> %1176}177 178define <vscale x 2 x i64> @test_svld1q_gather_u64base_index_s64(<vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %idx) {179; CHECK-LABEL: test_svld1q_gather_u64base_index_s64:180; CHECK: // %bb.0: // %entry181; CHECK-NEXT: lsl x8, x0, #3182; CHECK-NEXT: ld1q { z0.q }, p0/z, [z0.d, x8]183; CHECK-NEXT: ret184entry:185 %0 = shl i64 %idx, 3186 %1 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2i64.nxv2i64(<vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %0)187 ret <vscale x 2 x i64> %1188}189 190define <vscale x 2 x i64> @test_svld1q_gather_u64base_index_u64(<vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %idx) {191; CHECK-LABEL: test_svld1q_gather_u64base_index_u64:192; CHECK: // %bb.0: // %entry193; CHECK-NEXT: lsl x8, x0, #3194; CHECK-NEXT: ld1q { z0.q }, p0/z, [z0.d, x8]195; CHECK-NEXT: ret196entry:197 %0 = shl i64 %idx, 3198 %1 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2i64.nxv2i64(<vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %0)199 ret <vscale x 2 x i64> %1200}201 202define <vscale x 8 x bfloat> @test_svld1q_gather_u64base_index_bf16(<vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %idx) {203; CHECK-LABEL: test_svld1q_gather_u64base_index_bf16:204; CHECK: // %bb.0: // %entry205; CHECK-NEXT: lsl x8, x0, #1206; CHECK-NEXT: ld1q { z0.q }, p0/z, [z0.d, x8]207; CHECK-NEXT: ret208entry:209 %0 = shl i64 %idx, 1210 %1 = tail call <vscale x 8 x bfloat> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv8bf16.nxv2i64(<vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %0)211 ret <vscale x 8 x bfloat> %1212}213 214define <vscale x 8 x half> @test_svld1q_gather_u64base_index_f16(<vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %idx) {215; CHECK-LABEL: test_svld1q_gather_u64base_index_f16:216; CHECK: // %bb.0: // %entry217; CHECK-NEXT: lsl x8, x0, #1218; CHECK-NEXT: ld1q { z0.q }, p0/z, [z0.d, x8]219; CHECK-NEXT: ret220entry:221 %0 = shl i64 %idx, 1222 %1 = tail call <vscale x 8 x half> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv8f16.nxv2i64(<vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %0)223 ret <vscale x 8 x half> %1224}225 226define <vscale x 4 x float> @test_svld1q_gather_u64base_index_f32(<vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %idx) {227; CHECK-LABEL: test_svld1q_gather_u64base_index_f32:228; CHECK: // %bb.0: // %entry229; CHECK-NEXT: lsl x8, x0, #2230; CHECK-NEXT: ld1q { z0.q }, p0/z, [z0.d, x8]231; CHECK-NEXT: ret232entry:233 %0 = shl i64 %idx, 2234 %1 = tail call <vscale x 4 x float> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv4f32.nxv2i64(<vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %0)235 ret <vscale x 4 x float> %1236}237 238define <vscale x 2 x double> @test_svld1q_gather_u64base_index_f64(<vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %idx) {239; CHECK-LABEL: test_svld1q_gather_u64base_index_f64:240; CHECK: // %bb.0: // %entry241; CHECK-NEXT: lsl x8, x0, #3242; CHECK-NEXT: ld1q { z0.q }, p0/z, [z0.d, x8]243; CHECK-NEXT: ret244entry:245 %0 = shl i64 %idx, 3246 %1 = tail call <vscale x 2 x double> @llvm.aarch64.sve.ld1q.gather.scalar.offset.nxv2f64.nxv2i64(<vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %0)247 ret <vscale x 2 x double> %1248}249 250