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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve2p1 < %s | FileCheck %s3; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve,+sme2p1 < %s | FileCheck %s4; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sme2p1 -force-streaming < %s | FileCheck %s5; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sme,+sve2p1 -force-streaming < %s | FileCheck %s6 7;8; ORQV9;10 11define <16 x i8> @orqv_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {12; CHECK-LABEL: orqv_i8:13; CHECK: // %bb.0:14; CHECK-NEXT: orqv v0.16b, p0, z0.b15; CHECK-NEXT: ret16 %res = call <16 x i8> @llvm.aarch64.sve.orqv.v16i8.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a);17 ret <16 x i8> %res18}19 20define <8 x i16> @orqv_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {21; CHECK-LABEL: orqv_i16:22; CHECK: // %bb.0:23; CHECK-NEXT: orqv v0.8h, p0, z0.h24; CHECK-NEXT: ret25 %res = call <8 x i16> @llvm.aarch64.sve.orqv.v8i16.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a);26 ret <8 x i16> %res27}28 29define <4 x i32> @orqv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {30; CHECK-LABEL: orqv_i32:31; CHECK: // %bb.0:32; CHECK-NEXT: orqv v0.4s, p0, z0.s33; CHECK-NEXT: ret34 %res = call <4 x i32> @llvm.aarch64.sve.orqv.v4i32.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a);35 ret <4 x i32> %res36}37 38define <2 x i64> @orqv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {39; CHECK-LABEL: orqv_i64:40; CHECK: // %bb.0:41; CHECK-NEXT: orqv v0.2d, p0, z0.d42; CHECK-NEXT: ret43 %res = call <2 x i64> @llvm.aarch64.sve.orqv.v2i64.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a);44 ret <2 x i64> %res45}46 47;48; EORQV49;50 51define <16 x i8> @eorqv_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {52; CHECK-LABEL: eorqv_i8:53; CHECK: // %bb.0:54; CHECK-NEXT: eorqv v0.16b, p0, z0.b55; CHECK-NEXT: ret56 %res = call <16 x i8> @llvm.aarch64.sve.eorqv.v16i8.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a);57 ret <16 x i8> %res58}59 60define <8 x i16> @eorqv_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {61; CHECK-LABEL: eorqv_i16:62; CHECK: // %bb.0:63; CHECK-NEXT: eorqv v0.8h, p0, z0.h64; CHECK-NEXT: ret65 %res = call <8 x i16> @llvm.aarch64.sve.eorqv.v8i16.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a);66 ret <8 x i16> %res67}68 69define <4 x i32> @eorqv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {70; CHECK-LABEL: eorqv_i32:71; CHECK: // %bb.0:72; CHECK-NEXT: eorqv v0.4s, p0, z0.s73; CHECK-NEXT: ret74 %res = call <4 x i32> @llvm.aarch64.sve.eorqv.v4i32.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a);75 ret <4 x i32> %res76}77 78define <2 x i64> @eorqv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {79; CHECK-LABEL: eorqv_i64:80; CHECK: // %bb.0:81; CHECK-NEXT: eorqv v0.2d, p0, z0.d82; CHECK-NEXT: ret83 %res = call <2 x i64> @llvm.aarch64.sve.eorqv.v2i64.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a);84 ret <2 x i64> %res85}86 87;88; ANDQV89;90 91define <16 x i8> @andqv_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {92; CHECK-LABEL: andqv_i8:93; CHECK: // %bb.0:94; CHECK-NEXT: andqv v0.16b, p0, z0.b95; CHECK-NEXT: ret96 %res = call <16 x i8> @llvm.aarch64.sve.andqv.v16i8.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a);97 ret <16 x i8> %res98}99 100define <8 x i16> @andqv_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {101; CHECK-LABEL: andqv_i16:102; CHECK: // %bb.0:103; CHECK-NEXT: andqv v0.8h, p0, z0.h104; CHECK-NEXT: ret105 %res = call <8 x i16> @llvm.aarch64.sve.andqv.v8i16.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a);106 ret <8 x i16> %res107}108 109define <4 x i32> @andqv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {110; CHECK-LABEL: andqv_i32:111; CHECK: // %bb.0:112; CHECK-NEXT: andqv v0.4s, p0, z0.s113; CHECK-NEXT: ret114 %res = call <4 x i32> @llvm.aarch64.sve.andqv.v4i32.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a);115 ret <4 x i32> %res116}117 118define <2 x i64> @andqv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {119; CHECK-LABEL: andqv_i64:120; CHECK: // %bb.0:121; CHECK-NEXT: andqv v0.2d, p0, z0.d122; CHECK-NEXT: ret123 %res = call <2 x i64> @llvm.aarch64.sve.andqv.v2i64.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a);124 ret <2 x i64> %res125}126 127;128; ADDQV129;130 131define <16 x i8> @addqv_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {132; CHECK-LABEL: addqv_i8:133; CHECK: // %bb.0:134; CHECK-NEXT: addqv v0.16b, p0, z0.b135; CHECK-NEXT: ret136 %res = call <16 x i8> @llvm.aarch64.sve.addqv.v16i8.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a);137 ret <16 x i8> %res138}139 140define <8 x i16> @addqv_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {141; CHECK-LABEL: addqv_i16:142; CHECK: // %bb.0:143; CHECK-NEXT: addqv v0.8h, p0, z0.h144; CHECK-NEXT: ret145 %res = call <8 x i16> @llvm.aarch64.sve.addqv.v8i16.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a);146 ret <8 x i16> %res147}148 149define <4 x i32> @addqv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {150; CHECK-LABEL: addqv_i32:151; CHECK: // %bb.0:152; CHECK-NEXT: addqv v0.4s, p0, z0.s153; CHECK-NEXT: ret154 %res = call <4 x i32> @llvm.aarch64.sve.addqv.v4i32.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a);155 ret <4 x i32> %res156}157 158define <2 x i64> @addqv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {159; CHECK-LABEL: addqv_i64:160; CHECK: // %bb.0:161; CHECK-NEXT: addqv v0.2d, p0, z0.d162; CHECK-NEXT: ret163 %res = call <2 x i64> @llvm.aarch64.sve.addqv.v2i64.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a);164 ret <2 x i64> %res165}166 167;168; SMAXQV169;170 171define <16 x i8> @smaxqv_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {172; CHECK-LABEL: smaxqv_i8:173; CHECK: // %bb.0:174; CHECK-NEXT: smaxqv v0.16b, p0, z0.b175; CHECK-NEXT: ret176 %res = call <16 x i8> @llvm.aarch64.sve.smaxqv.v16i8.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a);177 ret <16 x i8> %res178}179 180define <8 x i16> @smaxqv_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {181; CHECK-LABEL: smaxqv_i16:182; CHECK: // %bb.0:183; CHECK-NEXT: smaxqv v0.8h, p0, z0.h184; CHECK-NEXT: ret185 %res = call <8 x i16> @llvm.aarch64.sve.smaxqv.v8i16.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a);186 ret <8 x i16> %res187}188 189define <4 x i32> @smaxqv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {190; CHECK-LABEL: smaxqv_i32:191; CHECK: // %bb.0:192; CHECK-NEXT: smaxqv v0.4s, p0, z0.s193; CHECK-NEXT: ret194 %res = call <4 x i32> @llvm.aarch64.sve.smaxqv.v4i32.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a);195 ret <4 x i32> %res196}197 198define <2 x i64> @smaxqv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {199; CHECK-LABEL: smaxqv_i64:200; CHECK: // %bb.0:201; CHECK-NEXT: smaxqv v0.2d, p0, z0.d202; CHECK-NEXT: ret203 %res = call <2 x i64> @llvm.aarch64.sve.smaxqv.v2i64.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a);204 ret <2 x i64> %res205}206 207;208; UMAXQV209;210 211define <16 x i8> @umaxqv_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {212; CHECK-LABEL: umaxqv_i8:213; CHECK: // %bb.0:214; CHECK-NEXT: umaxqv v0.16b, p0, z0.b215; CHECK-NEXT: ret216 %res = call <16 x i8> @llvm.aarch64.sve.umaxqv.v16i8.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a);217 ret <16 x i8> %res218}219 220define <8 x i16> @umaxqv_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {221; CHECK-LABEL: umaxqv_i16:222; CHECK: // %bb.0:223; CHECK-NEXT: umaxqv v0.8h, p0, z0.h224; CHECK-NEXT: ret225 %res = call <8 x i16> @llvm.aarch64.sve.umaxqv.v8i16.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a);226 ret <8 x i16> %res227}228 229define <4 x i32> @umaxqv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {230; CHECK-LABEL: umaxqv_i32:231; CHECK: // %bb.0:232; CHECK-NEXT: umaxqv v0.4s, p0, z0.s233; CHECK-NEXT: ret234 %res = call <4 x i32> @llvm.aarch64.sve.umaxqv.v4i32.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a);235 ret <4 x i32> %res236}237 238define <2 x i64> @umaxqv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {239; CHECK-LABEL: umaxqv_i64:240; CHECK: // %bb.0:241; CHECK-NEXT: umaxqv v0.2d, p0, z0.d242; CHECK-NEXT: ret243 %res = call <2 x i64> @llvm.aarch64.sve.umaxqv.v2i64.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a);244 ret <2 x i64> %res245}246 247;248; SMINQV249;250 251define <16 x i8> @sminqv_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {252; CHECK-LABEL: sminqv_i8:253; CHECK: // %bb.0:254; CHECK-NEXT: sminqv v0.16b, p0, z0.b255; CHECK-NEXT: ret256 %res = call <16 x i8> @llvm.aarch64.sve.sminqv.v16i8.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a);257 ret <16 x i8> %res258}259 260define <8 x i16> @sminqv_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {261; CHECK-LABEL: sminqv_i16:262; CHECK: // %bb.0:263; CHECK-NEXT: sminqv v0.8h, p0, z0.h264; CHECK-NEXT: ret265 %res = call <8 x i16> @llvm.aarch64.sve.sminqv.v8i16.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a);266 ret <8 x i16> %res267}268 269define <4 x i32> @sminqv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {270; CHECK-LABEL: sminqv_i32:271; CHECK: // %bb.0:272; CHECK-NEXT: sminqv v0.4s, p0, z0.s273; CHECK-NEXT: ret274 %res = call <4 x i32> @llvm.aarch64.sve.sminqv.v4i32.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a);275 ret <4 x i32> %res276}277 278define <2 x i64> @sminqv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {279; CHECK-LABEL: sminqv_i64:280; CHECK: // %bb.0:281; CHECK-NEXT: sminqv v0.2d, p0, z0.d282; CHECK-NEXT: ret283 %res = call <2 x i64> @llvm.aarch64.sve.sminqv.v2i64.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a);284 ret <2 x i64> %res285}286 287;288; UMINQV289;290 291define <16 x i8> @uminqv_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {292; CHECK-LABEL: uminqv_i8:293; CHECK: // %bb.0:294; CHECK-NEXT: uminqv v0.16b, p0, z0.b295; CHECK-NEXT: ret296 %res = call <16 x i8> @llvm.aarch64.sve.uminqv.v16i8.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a);297 ret <16 x i8> %res298}299 300define <8 x i16> @uminqv_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {301; CHECK-LABEL: uminqv_i16:302; CHECK: // %bb.0:303; CHECK-NEXT: uminqv v0.8h, p0, z0.h304; CHECK-NEXT: ret305 %res = call <8 x i16> @llvm.aarch64.sve.uminqv.v8i16.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a);306 ret <8 x i16> %res307}308 309define <4 x i32> @uminqv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) {310; CHECK-LABEL: uminqv_i32:311; CHECK: // %bb.0:312; CHECK-NEXT: uminqv v0.4s, p0, z0.s313; CHECK-NEXT: ret314 %res = call <4 x i32> @llvm.aarch64.sve.uminqv.v4i32.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a);315 ret <4 x i32> %res316}317 318define <2 x i64> @uminqv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) {319; CHECK-LABEL: uminqv_i64:320; CHECK: // %bb.0:321; CHECK-NEXT: uminqv v0.2d, p0, z0.d322; CHECK-NEXT: ret323 %res = call <2 x i64> @llvm.aarch64.sve.uminqv.v2i64.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a);324 ret <2 x i64> %res325}326 327declare <16 x i8> @llvm.aarch64.sve.orqv.v16i8.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>)328declare <8 x i16> @llvm.aarch64.sve.orqv.v8i16.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>)329declare <4 x i32> @llvm.aarch64.sve.orqv.v4i32.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>)330declare <2 x i64> @llvm.aarch64.sve.orqv.v2i64.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>)331declare <16 x i8> @llvm.aarch64.sve.eorqv.v16i8.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>)332declare <8 x i16> @llvm.aarch64.sve.eorqv.v8i16.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>)333declare <4 x i32> @llvm.aarch64.sve.eorqv.v4i32.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>)334declare <2 x i64> @llvm.aarch64.sve.eorqv.v2i64.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>)335declare <16 x i8> @llvm.aarch64.sve.andqv.v16i8.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>)336declare <8 x i16> @llvm.aarch64.sve.andqv.v8i16.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>)337declare <4 x i32> @llvm.aarch64.sve.andqv.v4i32.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>)338declare <2 x i64> @llvm.aarch64.sve.andqv.v2i64.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>)339declare <16 x i8> @llvm.aarch64.sve.addqv.v16i8.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>)340declare <8 x i16> @llvm.aarch64.sve.addqv.v8i16.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>)341declare <4 x i32> @llvm.aarch64.sve.addqv.v4i32.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>)342declare <2 x i64> @llvm.aarch64.sve.addqv.v2i64.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>)343declare <16 x i8> @llvm.aarch64.sve.smaxqv.v16i8.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>)344declare <8 x i16> @llvm.aarch64.sve.smaxqv.v8i16.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>)345declare <4 x i32> @llvm.aarch64.sve.smaxqv.v4i32.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>)346declare <2 x i64> @llvm.aarch64.sve.smaxqv.v2i64.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>)347declare <16 x i8> @llvm.aarch64.sve.umaxqv.v16i8.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>)348declare <8 x i16> @llvm.aarch64.sve.umaxqv.v8i16.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>)349declare <4 x i32> @llvm.aarch64.sve.umaxqv.v4i32.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>)350declare <2 x i64> @llvm.aarch64.sve.umaxqv.v2i64.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>)351declare <16 x i8> @llvm.aarch64.sve.sminqv.v16i8.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>)352declare <8 x i16> @llvm.aarch64.sve.sminqv.v8i16.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>)353declare <4 x i32> @llvm.aarch64.sve.sminqv.v4i32.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>)354declare <2 x i64> @llvm.aarch64.sve.sminqv.v2i64.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>)355declare <16 x i8> @llvm.aarch64.sve.uminqv.v16i8.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>)356declare <8 x i16> @llvm.aarch64.sve.uminqv.v8i16.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>)357declare <4 x i32> @llvm.aarch64.sve.uminqv.v4i32.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>)358declare <2 x i64> @llvm.aarch64.sve.uminqv.v2i64.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>)359