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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve2p1 < %s | FileCheck %s3 4; LD1W5 6define <vscale x 4 x i32> @test_svld1uwq_i32_ss(<vscale x 1 x i1> %pred, ptr %base, i64 %offset) {7; CHECK-LABEL: test_svld1uwq_i32_ss:8; CHECK: // %bb.0:9; CHECK-NEXT: ld1w { z0.q }, p0/z, [x0, x1, lsl #2]10; CHECK-NEXT: ret11 %gep = getelementptr i32, ptr %base, i64 %offset12 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1uwq.nxv4i32(<vscale x 1 x i1> %pred, ptr %gep)13 ret <vscale x 4 x i32> %res14}15 16define <vscale x 4 x i32> @test_svld1uwq_i32_si(<vscale x 1 x i1> %pred, ptr %base) {17; CHECK-LABEL: test_svld1uwq_i32_si:18; CHECK: // %bb.0:19; CHECK-NEXT: ld1w { z0.q }, p0/z, [x0, #-8, mul vl]20; CHECK-NEXT: ld1w { z1.q }, p0/z, [x0, #7, mul vl]21; CHECK-NEXT: add z0.s, z0.s, z1.s22; CHECK-NEXT: ret23 %gep1 = getelementptr inbounds <vscale x 1 x i32>, ptr %base, i64 -824 %res1 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1uwq.nxv4i32(<vscale x 1 x i1> %pred, ptr %gep1)25 26 %gep2 = getelementptr inbounds <vscale x 1 x i32>, ptr %base, i64 727 %res2 = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1uwq.nxv4i32(<vscale x 1 x i1> %pred, ptr %gep2)28 29 %res = add <vscale x 4 x i32> %res1, %res230 ret <vscale x 4 x i32> %res31}32 33define <vscale x 4 x i32> @test_svld1uwq_i32_out_of_bound(<vscale x 1 x i1> %pred, ptr %base) {34; CHECK-LABEL: test_svld1uwq_i32_out_of_bound:35; CHECK: // %bb.0:36; CHECK-NEXT: incb x0, all, mul #237; CHECK-NEXT: ld1w { z0.q }, p0/z, [x0]38; CHECK-NEXT: ret39 %gep = getelementptr inbounds <vscale x 1 x i32>, ptr %base, i64 840 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1uwq.nxv4i32(<vscale x 1 x i1> %pred, ptr %gep)41 42 ret <vscale x 4 x i32> %res43}44 45define <vscale x 4 x float> @test_svld1uwq_f32_ss(<vscale x 1 x i1> %pred, ptr %base, i64 %offset) {46; CHECK-LABEL: test_svld1uwq_f32_ss:47; CHECK: // %bb.0:48; CHECK-NEXT: ld1w { z0.q }, p0/z, [x0, x1, lsl #2]49; CHECK-NEXT: ret50 %gep = getelementptr float, ptr %base, i64 %offset51 %res = call <vscale x 4 x float> @llvm.aarch64.sve.ld1uwq.nxv4f32(<vscale x 1 x i1> %pred, ptr %gep)52 ret <vscale x 4 x float> %res53}54 55define <vscale x 4 x float> @test_svld1uwq_f32_si(<vscale x 1 x i1> %pred, ptr %base) {56; CHECK-LABEL: test_svld1uwq_f32_si:57; CHECK: // %bb.0:58; CHECK-NEXT: ld1w { z0.q }, p0/z, [x0, #-8, mul vl]59; CHECK-NEXT: ld1w { z1.q }, p0/z, [x0, #7, mul vl]60; CHECK-NEXT: fadd z0.s, z0.s, z1.s61; CHECK-NEXT: ret62 %gep1 = getelementptr inbounds <vscale x 1 x float>, ptr %base, i64 -863 %res1 = call <vscale x 4 x float> @llvm.aarch64.sve.ld1uwq.nxv4f32(<vscale x 1 x i1> %pred, ptr %gep1)64 65 %gep2 = getelementptr inbounds <vscale x 1 x float>, ptr %base, i64 766 %res2 = call <vscale x 4 x float> @llvm.aarch64.sve.ld1uwq.nxv4f32(<vscale x 1 x i1> %pred, ptr %gep2)67 68 %res = fadd <vscale x 4 x float> %res1, %res269 ret <vscale x 4 x float> %res70}71 72; LD1D73 74define <vscale x 2 x i64> @test_svld1udq_i64_ss(<vscale x 1 x i1> %pred, ptr %base, i64 %offset) {75; CHECK-LABEL: test_svld1udq_i64_ss:76; CHECK: // %bb.0:77; CHECK-NEXT: ld1d { z0.q }, p0/z, [x0, x1, lsl #3]78; CHECK-NEXT: ret79 %gep = getelementptr i64, ptr %base, i64 %offset80 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1udq.nxv2i64(<vscale x 1 x i1> %pred, ptr %gep)81 ret <vscale x 2 x i64> %res82}83 84define <vscale x 2 x i64> @test_svld1udq_i64_si(<vscale x 1 x i1> %pred, ptr %base) {85; CHECK-LABEL: test_svld1udq_i64_si:86; CHECK: // %bb.0:87; CHECK-NEXT: ld1d { z0.q }, p0/z, [x0, #-8, mul vl]88; CHECK-NEXT: ld1d { z1.q }, p0/z, [x0, #7, mul vl]89; CHECK-NEXT: add z0.d, z0.d, z1.d90; CHECK-NEXT: ret91 %gep1 = getelementptr inbounds <vscale x 1 x i64>, ptr %base, i64 -892 %res1 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1udq.nxv2i64(<vscale x 1 x i1> %pred, ptr %gep1)93 94 %gep2 = getelementptr inbounds <vscale x 1 x i64>, ptr %base, i64 795 %res2 = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1udq.nxv2i64(<vscale x 1 x i1> %pred, ptr %gep2)96 97 %res = add <vscale x 2 x i64> %res1, %res298 ret <vscale x 2 x i64> %res99}100 101define <vscale x 2 x i64> @test_svld1udq_i64_out_of_bound(<vscale x 1 x i1> %pred, ptr %base) {102; CHECK-LABEL: test_svld1udq_i64_out_of_bound:103; CHECK: // %bb.0:104; CHECK-NEXT: addvl x8, x0, #-5105; CHECK-NEXT: ld1d { z0.q }, p0/z, [x8]106; CHECK-NEXT: ret107 %gep = getelementptr inbounds <vscale x 1 x i64>, ptr %base, i64 -10108 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1udq.nxv2i64(<vscale x 1 x i1> %pred, ptr %gep)109 110 ret <vscale x 2 x i64> %res111}112 113define <vscale x 2 x double> @test_svld1udq_f64_ss(<vscale x 1 x i1> %pred, ptr %base, i64 %offset) {114; CHECK-LABEL: test_svld1udq_f64_ss:115; CHECK: // %bb.0:116; CHECK-NEXT: ld1d { z0.q }, p0/z, [x0, x1, lsl #3]117; CHECK-NEXT: ret118 %gep = getelementptr double, ptr %base, i64 %offset119 %res = call <vscale x 2 x double> @llvm.aarch64.sve.ld1udq.nxv2f64(<vscale x 1 x i1> %pred, ptr %gep)120 ret <vscale x 2 x double> %res121}122 123define <vscale x 2 x double> @test_svld1udq_f64_si(<vscale x 1 x i1> %pred, ptr %base) {124; CHECK-LABEL: test_svld1udq_f64_si:125; CHECK: // %bb.0:126; CHECK-NEXT: ld1d { z0.q }, p0/z, [x0, #-8, mul vl]127; CHECK-NEXT: ld1d { z1.q }, p0/z, [x0, #7, mul vl]128; CHECK-NEXT: fadd z0.d, z0.d, z1.d129; CHECK-NEXT: ret130 %gep1 = getelementptr inbounds <vscale x 1 x double>, ptr %base, i64 -8131 %res1 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1udq.nxv2f64(<vscale x 1 x i1> %pred, ptr %gep1)132 133 %gep2 = getelementptr inbounds <vscale x 1 x double>, ptr %base, i64 7134 %res2 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1udq.nxv2f64(<vscale x 1 x i1> %pred, ptr %gep2)135 136 %res = fadd <vscale x 2 x double> %res1, %res2137 ret <vscale x 2 x double> %res138}139 140declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1uwq.nxv4i32(<vscale x 1 x i1>, ptr)141declare <vscale x 4 x float> @llvm.aarch64.sve.ld1uwq.nxv4f32(<vscale x 1 x i1>, ptr)142 143declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1udq.nxv2i64(<vscale x 1 x i1>, ptr)144declare <vscale x 2 x double> @llvm.aarch64.sve.ld1udq.nxv2f64(<vscale x 1 x i1>, ptr)145