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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1 < %s | FileCheck %s3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme2p1 < %s | FileCheck %s4; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2p1 -force-streaming < %s | FileCheck %s5; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme,+sve2p1 -force-streaming < %s | FileCheck %s6 7define <vscale x 16 x i1> @test_pmov_to_pred_i8(<vscale x 16 x i8> %zn) {8; CHECK-LABEL: test_pmov_to_pred_i8:9; CHECK: // %bb.0: // %entry10; CHECK-NEXT: pmov p0.b, z011; CHECK-NEXT: ret12 entry:13 %res = call <vscale x 16 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv16i8(<vscale x 16 x i8> %zn, i32 0)14 ret <vscale x 16 x i1> %res15}16 17define <vscale x 8 x i1> @test_pmov_to_pred_i16(<vscale x 8 x i16> %zn) {18; CHECK-LABEL: test_pmov_to_pred_i16:19; CHECK: // %bb.0: // %entry20; CHECK-NEXT: ptrue p0.h21; CHECK-NEXT: pmov p1.h, z0[0]22; CHECK-NEXT: pmov p2.h, z0[1]23; CHECK-NEXT: eor p0.b, p0/z, p1.b, p2.b24; CHECK-NEXT: ret25 entry:26 %res1 = call <vscale x 8 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv8i16(<vscale x 8 x i16> %zn, i32 0)27 %res2 = call <vscale x 8 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv8i16(<vscale x 8 x i16> %zn, i32 1)28 29 %res = add <vscale x 8 x i1> %res1, %res230 ret <vscale x 8 x i1> %res31}32 33define <vscale x 4 x i1> @test_pmov_to_pred_i32(<vscale x 4 x i32> %zn) {34; CHECK-LABEL: test_pmov_to_pred_i32:35; CHECK: // %bb.0: // %entry36; CHECK-NEXT: ptrue p0.s37; CHECK-NEXT: pmov p1.s, z0[0]38; CHECK-NEXT: pmov p2.s, z0[3]39; CHECK-NEXT: eor p0.b, p0/z, p1.b, p2.b40; CHECK-NEXT: ret41 entry:42 %res1 = call <vscale x 4 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv4i32(<vscale x 4 x i32> %zn, i32 0)43 %res2 = call <vscale x 4 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv4i32(<vscale x 4 x i32> %zn, i32 3)44 45 %res = add <vscale x 4 x i1> %res1, %res246 ret <vscale x 4 x i1> %res47}48 49define <vscale x 2 x i1> @test_pmov_to_pred_i64(<vscale x 2 x i64> %zn) {50; CHECK-LABEL: test_pmov_to_pred_i64:51; CHECK: // %bb.0: // %entry52; CHECK-NEXT: ptrue p0.d53; CHECK-NEXT: pmov p1.d, z0[0]54; CHECK-NEXT: pmov p2.d, z0[7]55; CHECK-NEXT: eor p0.b, p0/z, p1.b, p2.b56; CHECK-NEXT: ret57 entry:58 %res1 = call <vscale x 2 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv2i64(<vscale x 2 x i64> %zn, i32 0)59 %res2 = call <vscale x 2 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv2i64(<vscale x 2 x i64> %zn, i32 7)60 61 %res = add <vscale x 2 x i1> %res1, %res262 ret <vscale x 2 x i1> %res63}64 65declare <vscale x 16 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv16i8(<vscale x 16 x i8>, i32)66declare <vscale x 8 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv8i16(<vscale x 8 x i16>, i32)67declare <vscale x 4 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv4i32(<vscale x 4 x i32>, i32)68declare <vscale x 2 x i1> @llvm.aarch64.sve.pmov.to.pred.lane.nxv2i64(<vscale x 2 x i64>, i32)69