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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1 < %s | FileCheck %s3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme2p1 < %s | FileCheck %s4; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2p1 -force-streaming < %s | FileCheck %s5; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme,+sve2p1 -force-streaming < %s | FileCheck %s6 7; Merge8 9define <vscale x 8 x i16> @test_pmov_to_vector_i16(<vscale x 8 x i16> %zn, <vscale x 8 x i1> %pn) {10; CHECK-LABEL: test_pmov_to_vector_i16:11; CHECK: // %bb.0: // %entry12; CHECK-NEXT: pmov z0[1], p0.h13; CHECK-NEXT: ret14 entry:15 %res = call <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv8i16(<vscale x 8 x i16> %zn, <vscale x 8 x i1> %pn, i32 1)16 ret <vscale x 8 x i16> %res17}18 19define <vscale x 4 x i32> @test_pmov_to_vector_i32(<vscale x 4 x i32> %zn, <vscale x 4 x i1> %pn) {20; CHECK-LABEL: test_pmov_to_vector_i32:21; CHECK: // %bb.0: // %entry22; CHECK-NEXT: pmov z0[3], p0.s23; CHECK-NEXT: ret24 entry:25 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv4i32(<vscale x 4 x i32> %zn, <vscale x 4 x i1> %pn, i32 3)26 ret <vscale x 4 x i32> %res27}28 29define <vscale x 2 x i64> @test_pmov_to_vector_i64(<vscale x 2 x i64> %zn, <vscale x 2 x i1> %pn) {30; CHECK-LABEL: test_pmov_to_vector_i64:31; CHECK: // %bb.0: // %entry32; CHECK-NEXT: pmov z0[7], p0.d33; CHECK-NEXT: ret34 entry:35 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv2i64(<vscale x 2 x i64> %zn, <vscale x 2 x i1> %pn, i32 7)36 ret <vscale x 2 x i64> %res37}38 39 40; Zero41 42define <vscale x 16 x i8> @test_pmov_to_vector_zero_i8(<vscale x 16 x i1> %pn) {43; CHECK-LABEL: test_pmov_to_vector_zero_i8:44; CHECK: // %bb.0: // %entry45; CHECK-NEXT: pmov z0, p0.b46; CHECK-NEXT: ret47 entry:48 %res = call <vscale x 16 x i8> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv16i8(<vscale x 16 x i1> %pn)49 ret <vscale x 16 x i8> %res50}51 52define <vscale x 8 x i16> @test_pmov_to_vector_zero_i16(<vscale x 8 x i1> %pn) {53; CHECK-LABEL: test_pmov_to_vector_zero_i16:54; CHECK: // %bb.0: // %entry55; CHECK-NEXT: pmov z0[0], p0.h56; CHECK-NEXT: ret57 entry:58 %res = call <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv8i16(<vscale x 8 x i1> %pn)59 ret <vscale x 8 x i16> %res60}61 62define <vscale x 4 x i32> @test_pmov_to_vector_zero_i32(<vscale x 4 x i1> %pn) {63; CHECK-LABEL: test_pmov_to_vector_zero_i32:64; CHECK: // %bb.0: // %entry65; CHECK-NEXT: pmov z0[0], p0.s66; CHECK-NEXT: ret67 entry:68 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv4i32(<vscale x 4 x i1> %pn)69 ret <vscale x 4 x i32> %res70}71 72define <vscale x 2 x i64> @test_pmov_to_vector_zero_i64(<vscale x 2 x i1> %pn) {73; CHECK-LABEL: test_pmov_to_vector_zero_i64:74; CHECK: // %bb.0: // %entry75; CHECK-NEXT: pmov z0[0], p0.d76; CHECK-NEXT: ret77 entry:78 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv2i64(<vscale x 2 x i1> %pn)79 ret <vscale x 2 x i64> %res80}81 82declare <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, i32)83declare <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, i32)84declare <vscale x 2 x i64> @llvm.aarch64.sve.pmov.to.vector.lane.merging.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, i32)85 86declare <vscale x 16 x i8> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv16i8(<vscale x 16 x i1>)87declare <vscale x 8 x i16> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv8i16(<vscale x 8 x i1>)88declare <vscale x 4 x i32> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv4i32(<vscale x 4 x i1>)89declare <vscale x 2 x i64> @llvm.aarch64.sve.pmov.to.vector.lane.zeroing.nxv2i64(<vscale x 2 x i1>)90