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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64 -mattr=+sve2p1 < %s | FileCheck %s3; RUN: llc -mtriple=aarch64 -mattr=+sme2 -force-streaming < %s | FileCheck %s4; RUN: llc -mtriple=aarch64 -mattr=+sme,+sve2p1 -force-streaming < %s | FileCheck %s5 6define <vscale x 16 x i1> @pext_b(target("aarch64.svcount") %x) nounwind {7; CHECK-LABEL: pext_b:8; CHECK: // %bb.0:9; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill10; CHECK-NEXT: addvl sp, sp, #-111; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill12; CHECK-NEXT: mov p8.b, p0.b13; CHECK-NEXT: pext p0.b, pn8[2]14; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload15; CHECK-NEXT: addvl sp, sp, #116; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload17; CHECK-NEXT: ret18 %res = call <vscale x 16 x i1> @llvm.aarch64.sve.pext.nxv16i1(target("aarch64.svcount") %x, i32 2)19 ret <vscale x 16 x i1> %res20}21 22define <vscale x 8 x i1> @pext_h(target("aarch64.svcount") %x) nounwind {23; CHECK-LABEL: pext_h:24; CHECK: // %bb.0:25; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill26; CHECK-NEXT: addvl sp, sp, #-127; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill28; CHECK-NEXT: mov p8.b, p0.b29; CHECK-NEXT: pext p0.h, pn8[2]30; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload31; CHECK-NEXT: addvl sp, sp, #132; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload33; CHECK-NEXT: ret34 %res = call <vscale x 8 x i1> @llvm.aarch64.sve.pext.nxv8i1(target("aarch64.svcount") %x, i32 2)35 ret <vscale x 8 x i1> %res36}37 38define <vscale x 4 x i1> @pext_s(target("aarch64.svcount") %x) nounwind {39; CHECK-LABEL: pext_s:40; CHECK: // %bb.0:41; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill42; CHECK-NEXT: addvl sp, sp, #-143; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill44; CHECK-NEXT: mov p8.b, p0.b45; CHECK-NEXT: pext p0.s, pn8[2]46; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload47; CHECK-NEXT: addvl sp, sp, #148; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload49; CHECK-NEXT: ret50 %res = call <vscale x 4 x i1> @llvm.aarch64.sve.pext.nxv4i1(target("aarch64.svcount") %x, i32 2)51 ret <vscale x 4 x i1> %res52}53 54define <vscale x 2 x i1> @pext_d(target("aarch64.svcount") %x) nounwind {55; CHECK-LABEL: pext_d:56; CHECK: // %bb.0:57; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill58; CHECK-NEXT: addvl sp, sp, #-159; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill60; CHECK-NEXT: mov p8.b, p0.b61; CHECK-NEXT: pext p0.d, pn8[2]62; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload63; CHECK-NEXT: addvl sp, sp, #164; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload65; CHECK-NEXT: ret66 %res = call <vscale x 2 x i1> @llvm.aarch64.sve.pext.nxv2i1(target("aarch64.svcount") %x, i32 2)67 ret <vscale x 2 x i1> %res68}69 70declare <vscale x 16 x i1> @llvm.aarch64.sve.pext.nxv16i1(target("aarch64.svcount"), i32)71declare <vscale x 8 x i1> @llvm.aarch64.sve.pext.nxv8i1(target("aarch64.svcount"), i32)72declare <vscale x 4 x i1> @llvm.aarch64.sve.pext.nxv4i1(target("aarch64.svcount"), i32)73declare <vscale x 2 x i1> @llvm.aarch64.sve.pext.nxv2i1(target("aarch64.svcount"), i32)74 75define {<vscale x 16 x i1>,<vscale x 16 x i1>} @pext_x2_b(target("aarch64.svcount") %x) nounwind {76; CHECK-LABEL: pext_x2_b:77; CHECK: // %bb.0:78; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill79; CHECK-NEXT: addvl sp, sp, #-180; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill81; CHECK-NEXT: mov p8.b, p0.b82; CHECK-NEXT: pext { p0.b, p1.b }, pn8[1]83; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload84; CHECK-NEXT: addvl sp, sp, #185; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload86; CHECK-NEXT: ret87 %res = call {<vscale x 16 x i1>,<vscale x 16 x i1>} @llvm.aarch64.sve.pext.x2.nxv16i1(target("aarch64.svcount") %x, i32 1)88 ret {<vscale x 16 x i1>,<vscale x 16 x i1>} %res89}90 91define {<vscale x 8 x i1>,<vscale x 8 x i1>} @pext_x2_h(target("aarch64.svcount") %x) nounwind {92; CHECK-LABEL: pext_x2_h:93; CHECK: // %bb.0:94; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill95; CHECK-NEXT: addvl sp, sp, #-196; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill97; CHECK-NEXT: mov p8.b, p0.b98; CHECK-NEXT: pext { p0.h, p1.h }, pn8[1]99; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload100; CHECK-NEXT: addvl sp, sp, #1101; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload102; CHECK-NEXT: ret103 %res = call {<vscale x 8 x i1>,<vscale x 8 x i1>} @llvm.aarch64.sve.pext.x2.nxv8i1(target("aarch64.svcount") %x, i32 1)104 ret {<vscale x 8 x i1>,<vscale x 8 x i1>} %res105}106 107define {<vscale x 4 x i1>,<vscale x 4 x i1>} @pext_x2_s(target("aarch64.svcount") %x) nounwind {108; CHECK-LABEL: pext_x2_s:109; CHECK: // %bb.0:110; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill111; CHECK-NEXT: addvl sp, sp, #-1112; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill113; CHECK-NEXT: mov p8.b, p0.b114; CHECK-NEXT: pext { p0.s, p1.s }, pn8[1]115; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload116; CHECK-NEXT: addvl sp, sp, #1117; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload118; CHECK-NEXT: ret119 %res = call {<vscale x 4 x i1>,<vscale x 4 x i1>} @llvm.aarch64.sve.pext.x2.nxv4i1(target("aarch64.svcount") %x, i32 1)120 ret {<vscale x 4 x i1>,<vscale x 4 x i1>} %res121}122 123define {<vscale x 2 x i1>,<vscale x 2 x i1>} @pext_x2_d(target("aarch64.svcount") %x) nounwind {124; CHECK-LABEL: pext_x2_d:125; CHECK: // %bb.0:126; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill127; CHECK-NEXT: addvl sp, sp, #-1128; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill129; CHECK-NEXT: mov p8.b, p0.b130; CHECK-NEXT: pext { p0.d, p1.d }, pn8[1]131; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload132; CHECK-NEXT: addvl sp, sp, #1133; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload134; CHECK-NEXT: ret135 %res = call {<vscale x 2 x i1>,<vscale x 2 x i1>} @llvm.aarch64.sve.pext.x2.nxv2i1(target("aarch64.svcount") %x, i32 1)136 ret {<vscale x 2 x i1>,<vscale x 2 x i1>} %res137}138 139declare {<vscale x 16 x i1>,<vscale x 16 x i1>} @llvm.aarch64.sve.pext.x2.nxv16i1(target("aarch64.svcount"), i32)140declare {<vscale x 8 x i1>,<vscale x 8 x i1>} @llvm.aarch64.sve.pext.x2.nxv8i1(target("aarch64.svcount"), i32)141declare {<vscale x 4 x i1>,<vscale x 4 x i1>} @llvm.aarch64.sve.pext.x2.nxv4i1(target("aarch64.svcount"), i32)142declare {<vscale x 2 x i1>,<vscale x 2 x i1>} @llvm.aarch64.sve.pext.x2.nxv2i1(target("aarch64.svcount"), i32)143 144define target("aarch64.svcount") @ptrue_b() nounwind {145; CHECK-LABEL: ptrue_b:146; CHECK: // %bb.0:147; CHECK-NEXT: ptrue pn8.b148; CHECK-NEXT: mov p0.b, p8.b149; CHECK-NEXT: ret150 %res = call target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c8()151 ret target("aarch64.svcount") %res152}153 154define target("aarch64.svcount") @ptrue_h() nounwind {155; CHECK-LABEL: ptrue_h:156; CHECK: // %bb.0:157; CHECK-NEXT: ptrue pn8.h158; CHECK-NEXT: mov p0.b, p8.b159; CHECK-NEXT: ret160 %res = call target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c16()161 ret target("aarch64.svcount") %res162}163 164define target("aarch64.svcount") @ptrue_s() nounwind {165; CHECK-LABEL: ptrue_s:166; CHECK: // %bb.0:167; CHECK-NEXT: ptrue pn8.s168; CHECK-NEXT: mov p0.b, p8.b169; CHECK-NEXT: ret170 %res = call target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c32()171 ret target("aarch64.svcount") %res172}173 174define target("aarch64.svcount") @ptrue_d() nounwind {175; CHECK-LABEL: ptrue_d:176; CHECK: // %bb.0:177; CHECK-NEXT: ptrue pn8.d178; CHECK-NEXT: mov p0.b, p8.b179; CHECK-NEXT: ret180 %res = call target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c64()181 ret target("aarch64.svcount") %res182}183 184declare target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c8()185declare target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c16()186declare target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c32()187declare target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c64()188