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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py$2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1 < %s | FileCheck %s3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme2 < %s | FileCheck %s4; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -force-streaming < %s | FileCheck %s5; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme,+sve2p1 -force-streaming < %s | FileCheck %s6 7;8; SQCVTN9;10 11; x212define <vscale x 8 x i16 > @multi_vector_qcvtn_x2_s16_s32(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2) {13; CHECK-LABEL: multi_vector_qcvtn_x2_s16_s32:14; CHECK: // %bb.0:15; CHECK-NEXT: mov z3.d, z2.d16; CHECK-NEXT: mov z2.d, z1.d17; CHECK-NEXT: sqcvtn z0.h, { z2.s, z3.s }18; CHECK-NEXT: ret19 %res = call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtn.x2.nxv4i32(<vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2)20 ret <vscale x 8 x i16> %res21}22 23;24; UQCVTN25;26 27; x228define <vscale x 8 x i16> @multi_vector_qcvtn_x2_u16_u32(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1) {29; CHECK-LABEL: multi_vector_qcvtn_x2_u16_u32:30; CHECK: // %bb.0:31; CHECK-NEXT: mov z3.d, z2.d32; CHECK-NEXT: mov z2.d, z1.d33; CHECK-NEXT: uqcvtn z0.h, { z2.s, z3.s }34; CHECK-NEXT: ret35 %res = call <vscale x 8 x i16> @llvm.aarch64.sve.uqcvtn.x2.nxv4i32(<vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1)36 ret<vscale x 8 x i16> %res37}38 39;40; SQCVTUN41;42 43; x244define <vscale x 8 x i16 > @multi_vector_qcvtn_x2_s16_u32(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2) {45; CHECK-LABEL: multi_vector_qcvtn_x2_s16_u32:46; CHECK: // %bb.0:47; CHECK-NEXT: mov z3.d, z2.d48; CHECK-NEXT: mov z2.d, z1.d49; CHECK-NEXT: sqcvtun z0.h, { z2.s, z3.s }50; CHECK-NEXT: ret51 %res = call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtun.x2.nxv4i322(<vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2)52 ret <vscale x 8 x i16> %res53}54 55declare <vscale x 8 x i16> @llvm.aarch64.sve.uqcvtn.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)56declare <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtn.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)57declare <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtun.x2.nxv4i322(<vscale x 4 x i32>, <vscale x 4 x i32>)58