52 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1 -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme2 -verify-machineinstrs < %s | FileCheck %s4; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2p1 -force-streaming -verify-machineinstrs < %s | FileCheck %s5; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme,+sve2p1 -force-streaming -verify-machineinstrs < %s | FileCheck %s6 7;8; S/UQRSHRN x29;10 11define <vscale x 8 x i16> @multi_vector_sat_shift_narrow_interleave_x2_s16(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2) {12; CHECK-LABEL: multi_vector_sat_shift_narrow_interleave_x2_s16:13; CHECK: // %bb.0:14; CHECK-NEXT: mov z3.d, z2.d15; CHECK-NEXT: mov z2.d, z1.d16; CHECK-NEXT: sqrshrn z0.h, { z2.s, z3.s }, #1617; CHECK-NEXT: ret18 %res = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrn.x2.nxv8i16(<vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, i32 16)19 ret <vscale x 8 x i16> %res20}21 22define <vscale x 8 x i16> @multi_vector_sat_shift_narrow_interleave_x2_u16(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2) {23; CHECK-LABEL: multi_vector_sat_shift_narrow_interleave_x2_u16:24; CHECK: // %bb.0:25; CHECK-NEXT: mov z3.d, z2.d26; CHECK-NEXT: mov z2.d, z1.d27; CHECK-NEXT: uqrshrn z0.h, { z2.s, z3.s }, #1628; CHECK-NEXT: ret29 %res = call <vscale x 8 x i16> @llvm.aarch64.sve.uqrshrn.x2.nxv8i16(<vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, i32 16)30 ret <vscale x 8 x i16> %res31}32 33;34; SQRSHRUN x235;36 37define <vscale x 8 x i16> @multi_vector_sat_shift_unsigned_narrow_interleave_x2_s16(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2) {38; CHECK-LABEL: multi_vector_sat_shift_unsigned_narrow_interleave_x2_s16:39; CHECK: // %bb.0:40; CHECK-NEXT: mov z3.d, z2.d41; CHECK-NEXT: mov z2.d, z1.d42; CHECK-NEXT: sqrshrun z0.h, { z2.s, z3.s }, #1643; CHECK-NEXT: ret44 %res = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrun.x2.nxv8i16(<vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, i32 16)45 ret <vscale x 8 x i16> %res46}47 48declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrn.x2.nxv8i16(<vscale x 4 x i32>, <vscale x 4 x i32>, i32)49declare <vscale x 8 x i16> @llvm.aarch64.sve.uqrshrn.x2.nxv8i16(<vscale x 4 x i32>, <vscale x 4 x i32>, i32)50 51declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrun.x2.nxv8i16(<vscale x 4 x i32>, <vscale x 4 x i32>, i32)52