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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mattr=+sve2p1 -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mattr=+sve,+sme -verify-machineinstrs < %s | FileCheck %s4; RUN: llc -mattr=+sme -force-streaming -verify-machineinstrs < %s | FileCheck %s5 6target triple = "aarch64-linux-gnu"7 8define <vscale x 16 x i8> @test_sclamp_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {9; CHECK-LABEL: test_sclamp_i8:10; CHECK: // %bb.0:11; CHECK-NEXT: sclamp z0.b, z1.b, z2.b12; CHECK-NEXT: ret13 %res = call <vscale x 16 x i8> @llvm.aarch64.sve.sclamp.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c)14 ret <vscale x 16 x i8> %res15}16 17define <vscale x 8 x i16> @test_sclamp_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {18; CHECK-LABEL: test_sclamp_i16:19; CHECK: // %bb.0:20; CHECK-NEXT: sclamp z0.h, z1.h, z2.h21; CHECK-NEXT: ret22 %res = call <vscale x 8 x i16> @llvm.aarch64.sve.sclamp.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c)23 ret <vscale x 8 x i16> %res24}25 26define <vscale x 4 x i32> @test_sclamp_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {27; CHECK-LABEL: test_sclamp_i32:28; CHECK: // %bb.0:29; CHECK-NEXT: sclamp z0.s, z1.s, z2.s30; CHECK-NEXT: ret31 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.sclamp.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c)32 ret <vscale x 4 x i32> %res33}34 35define <vscale x 2 x i64> @test_sclamp_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {36; CHECK-LABEL: test_sclamp_i64:37; CHECK: // %bb.0:38; CHECK-NEXT: sclamp z0.d, z1.d, z2.d39; CHECK-NEXT: ret40 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.sclamp.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c)41 ret <vscale x 2 x i64> %res42}43 44declare <vscale x 16 x i8> @llvm.aarch64.sve.sclamp.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)45declare <vscale x 8 x i16> @llvm.aarch64.sve.sclamp.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)46declare <vscale x 4 x i32> @llvm.aarch64.sve.sclamp.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)47declare <vscale x 2 x i64> @llvm.aarch64.sve.sclamp.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)48