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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -force-streaming -verify-machineinstrs < %s | FileCheck %s3 4; == 8 to 64-bit elements ==5 6define { <vscale x 16 x i8>, <vscale x 16 x i8> } @sel_x2_i8(target("aarch64.svcount") %pn, <vscale x 16 x i8> %unused, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2) nounwind {7; CHECK-LABEL: sel_x2_i8:8; CHECK: // %bb.0:9; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill10; CHECK-NEXT: addvl sp, sp, #-111; CHECK-NEXT: mov z5.d, z4.d12; CHECK-NEXT: mov z7.d, z2.d13; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill14; CHECK-NEXT: mov z4.d, z3.d15; CHECK-NEXT: mov z6.d, z1.d16; CHECK-NEXT: mov p8.b, p0.b17; CHECK-NEXT: sel { z0.b, z1.b }, pn8, { z6.b, z7.b }, { z4.b, z5.b }18; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload19; CHECK-NEXT: addvl sp, sp, #120; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload21; CHECK-NEXT: ret22 %res = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount") %pn, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2)23 ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %res24}25 26define { <vscale x 8 x i16>, <vscale x 8 x i16> } @sel_x2_i16(target("aarch64.svcount") %pn, <vscale x 8 x i16> %unused, <vscale x 8 x i16> %zn1, <vscale x 8 x i16> %zn2, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2) nounwind {27; CHECK-LABEL: sel_x2_i16:28; CHECK: // %bb.0:29; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill30; CHECK-NEXT: addvl sp, sp, #-131; CHECK-NEXT: mov z5.d, z4.d32; CHECK-NEXT: mov z7.d, z2.d33; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill34; CHECK-NEXT: mov z4.d, z3.d35; CHECK-NEXT: mov z6.d, z1.d36; CHECK-NEXT: mov p8.b, p0.b37; CHECK-NEXT: sel { z0.h, z1.h }, pn8, { z6.h, z7.h }, { z4.h, z5.h }38; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload39; CHECK-NEXT: addvl sp, sp, #140; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload41; CHECK-NEXT: ret42 %res = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sel.x2.nxv8i16(target("aarch64.svcount") %pn, <vscale x 8 x i16> %zn1, <vscale x 8 x i16> %zn2, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2)43 ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %res44}45 46define { <vscale x 8 x half>, <vscale x 8 x half> } @sel_x2_f16(target("aarch64.svcount") %pn, <vscale x 8 x half> %unused, <vscale x 8 x half> %zn1, <vscale x 8 x half> %zn2, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2) nounwind {47; CHECK-LABEL: sel_x2_f16:48; CHECK: // %bb.0:49; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill50; CHECK-NEXT: addvl sp, sp, #-151; CHECK-NEXT: mov z5.d, z4.d52; CHECK-NEXT: mov z7.d, z2.d53; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill54; CHECK-NEXT: mov z4.d, z3.d55; CHECK-NEXT: mov z6.d, z1.d56; CHECK-NEXT: mov p8.b, p0.b57; CHECK-NEXT: sel { z0.h, z1.h }, pn8, { z6.h, z7.h }, { z4.h, z5.h }58; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload59; CHECK-NEXT: addvl sp, sp, #160; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload61; CHECK-NEXT: ret62 %res = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.sel.x2.nxv8f16(target("aarch64.svcount") %pn, <vscale x 8 x half> %zn1, <vscale x 8 x half> %zn2, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2)63 ret { <vscale x 8 x half>, <vscale x 8 x half> } %res64}65 66define { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @sel_x2_bf16(target("aarch64.svcount") %pn, <vscale x 8 x bfloat> %unused, <vscale x 8 x bfloat> %zn1, <vscale x 8 x bfloat> %zn2, <vscale x 8 x bfloat> %zm1, <vscale x 8 x bfloat> %zm2) nounwind {67; CHECK-LABEL: sel_x2_bf16:68; CHECK: // %bb.0:69; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill70; CHECK-NEXT: addvl sp, sp, #-171; CHECK-NEXT: mov z5.d, z4.d72; CHECK-NEXT: mov z7.d, z2.d73; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill74; CHECK-NEXT: mov z4.d, z3.d75; CHECK-NEXT: mov z6.d, z1.d76; CHECK-NEXT: mov p8.b, p0.b77; CHECK-NEXT: sel { z0.h, z1.h }, pn8, { z6.h, z7.h }, { z4.h, z5.h }78; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload79; CHECK-NEXT: addvl sp, sp, #180; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload81; CHECK-NEXT: ret82 %res = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.sel.x2.nxv8bf16(target("aarch64.svcount") %pn, <vscale x 8 x bfloat> %zn1, <vscale x 8 x bfloat> %zn2, <vscale x 8 x bfloat> %zm1, <vscale x 8 x bfloat> %zm2)83 ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %res84}85 86define { <vscale x 4 x i32>, <vscale x 4 x i32> } @sel_x2_i32(target("aarch64.svcount") %pn, <vscale x 4 x i32> %unused, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2) nounwind {87; CHECK-LABEL: sel_x2_i32:88; CHECK: // %bb.0:89; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill90; CHECK-NEXT: addvl sp, sp, #-191; CHECK-NEXT: mov z5.d, z4.d92; CHECK-NEXT: mov z7.d, z2.d93; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill94; CHECK-NEXT: mov z4.d, z3.d95; CHECK-NEXT: mov z6.d, z1.d96; CHECK-NEXT: mov p8.b, p0.b97; CHECK-NEXT: sel { z0.s, z1.s }, pn8, { z6.s, z7.s }, { z4.s, z5.s }98; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload99; CHECK-NEXT: addvl sp, sp, #1100; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload101; CHECK-NEXT: ret102 %res = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sel.x2.nxv4i32(target("aarch64.svcount") %pn, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2)103 ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %res104}105 106define { <vscale x 4 x float>, <vscale x 4 x float> } @sel_x2_f32(target("aarch64.svcount") %pn, <vscale x 4 x float> %unused, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2, <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2) nounwind {107; CHECK-LABEL: sel_x2_f32:108; CHECK: // %bb.0:109; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill110; CHECK-NEXT: addvl sp, sp, #-1111; CHECK-NEXT: mov z5.d, z4.d112; CHECK-NEXT: mov z7.d, z2.d113; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill114; CHECK-NEXT: mov z4.d, z3.d115; CHECK-NEXT: mov z6.d, z1.d116; CHECK-NEXT: mov p8.b, p0.b117; CHECK-NEXT: sel { z0.s, z1.s }, pn8, { z6.s, z7.s }, { z4.s, z5.s }118; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload119; CHECK-NEXT: addvl sp, sp, #1120; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload121; CHECK-NEXT: ret122 %res = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.sel.x2.nxv4f32(target("aarch64.svcount") %pn, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2, <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2)123 ret { <vscale x 4 x float>, <vscale x 4 x float> } %res124}125 126define { <vscale x 2 x i64>, <vscale x 2 x i64> } @sel_x2_i64(target("aarch64.svcount") %pn, <vscale x 2 x i64> %unused, <vscale x 2 x i64> %zn1, <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2) nounwind {127; CHECK-LABEL: sel_x2_i64:128; CHECK: // %bb.0:129; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill130; CHECK-NEXT: addvl sp, sp, #-1131; CHECK-NEXT: mov z5.d, z4.d132; CHECK-NEXT: mov z7.d, z2.d133; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill134; CHECK-NEXT: mov z4.d, z3.d135; CHECK-NEXT: mov z6.d, z1.d136; CHECK-NEXT: mov p8.b, p0.b137; CHECK-NEXT: sel { z0.d, z1.d }, pn8, { z6.d, z7.d }, { z4.d, z5.d }138; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload139; CHECK-NEXT: addvl sp, sp, #1140; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload141; CHECK-NEXT: ret142 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sel.x2.nxv2i64(target("aarch64.svcount") %pn, <vscale x 2 x i64> %zn1, <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2)143 ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %res144}145 146define { <vscale x 2 x double>, <vscale x 2 x double> } @sel_x2_f64(target("aarch64.svcount") %pn, <vscale x 2 x double> %unused, <vscale x 2 x double> %zn1, <vscale x 2 x double> %zn2, <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2) nounwind {147; CHECK-LABEL: sel_x2_f64:148; CHECK: // %bb.0:149; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill150; CHECK-NEXT: addvl sp, sp, #-1151; CHECK-NEXT: mov z5.d, z4.d152; CHECK-NEXT: mov z7.d, z2.d153; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill154; CHECK-NEXT: mov z4.d, z3.d155; CHECK-NEXT: mov z6.d, z1.d156; CHECK-NEXT: mov p8.b, p0.b157; CHECK-NEXT: sel { z0.d, z1.d }, pn8, { z6.d, z7.d }, { z4.d, z5.d }158; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload159; CHECK-NEXT: addvl sp, sp, #1160; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload161; CHECK-NEXT: ret162 %res = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.sel.x2.nxv2f64(target("aarch64.svcount") %pn, <vscale x 2 x double> %zn1, <vscale x 2 x double> %zn2, <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2)163 ret { <vscale x 2 x double>, <vscale x 2 x double> } %res164}165 166; == 8 to 64-bit elements ==167declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sel.x2.nxv16i8(target("aarch64.svcount") %pn, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2)168declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sel.x2.nxv8i16(target("aarch64.svcount") %pn, <vscale x 8 x i16> %zn1, <vscale x 8 x i16> %zn2, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2)169declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sel.x2.nxv4i32(target("aarch64.svcount") %pn, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2)170declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sel.x2.nxv2i64(target("aarch64.svcount") %pn, <vscale x 2 x i64> %zn1, <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2)171declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.sel.x2.nxv8f16(target("aarch64.svcount") %pn, <vscale x 8 x half> %zn1, <vscale x 8 x half> %zn2, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2)172declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.sel.x2.nxv8bf16(target("aarch64.svcount") %pn, <vscale x 8 x bfloat> %zn1, <vscale x 8 x bfloat> %zn2, <vscale x 8 x bfloat> %zm1, <vscale x 8 x bfloat> %zm2)173declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.sel.x2.nxv4f32(target("aarch64.svcount") %pn, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2, <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2)174declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.sel.x2.nxv2f64(target("aarch64.svcount") %pn, <vscale x 2 x double> %zn1, <vscale x 2 x double> %zn2, <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2)175