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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -force-streaming -verify-machineinstrs < %s | FileCheck %s3 4; == 8 to 64-bit elements ==5 6define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @sel_x4_i8(target("aarch64.svcount") %pn, <vscale x 16 x i8> %unused, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, <vscale x 16 x i8> %zn4, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3, <vscale x 16 x i8> %zm4) nounwind {7; CHECK-LABEL: sel_x4_i8:8; CHECK: // %bb.0:9; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill10; CHECK-NEXT: addvl sp, sp, #-111; CHECK-NEXT: mov z26.d, z7.d12; CHECK-NEXT: mov z31.d, z4.d13; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill14; CHECK-NEXT: mov z25.d, z6.d15; CHECK-NEXT: mov z30.d, z3.d16; CHECK-NEXT: mov p8.b, p0.b17; CHECK-NEXT: mov z24.d, z5.d18; CHECK-NEXT: mov z29.d, z2.d19; CHECK-NEXT: ldr z27, [x0]20; CHECK-NEXT: mov z28.d, z1.d21; CHECK-NEXT: sel { z0.b - z3.b }, pn8, { z28.b - z31.b }, { z24.b - z27.b }22; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload23; CHECK-NEXT: addvl sp, sp, #124; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload25; CHECK-NEXT: ret26 %res = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sel.x4.nxv16i8(target("aarch64.svcount") %pn, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, <vscale x 16 x i8> %zn4, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3, <vscale x 16 x i8> %zm4)27 ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %res28}29 30define { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @sel_x4_i16(target("aarch64.svcount") %pn, <vscale x 8 x i16> %unused, <vscale x 8 x i16> %zn1, <vscale x 8 x i16> %zn2, <vscale x 8 x i16> %zn3, <vscale x 8 x i16> %zn4, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2, <vscale x 8 x i16> %zm3, <vscale x 8 x i16> %zm4) nounwind {31; CHECK-LABEL: sel_x4_i16:32; CHECK: // %bb.0:33; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill34; CHECK-NEXT: addvl sp, sp, #-135; CHECK-NEXT: mov z26.d, z7.d36; CHECK-NEXT: mov z31.d, z4.d37; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill38; CHECK-NEXT: mov z25.d, z6.d39; CHECK-NEXT: mov z30.d, z3.d40; CHECK-NEXT: mov p8.b, p0.b41; CHECK-NEXT: mov z24.d, z5.d42; CHECK-NEXT: mov z29.d, z2.d43; CHECK-NEXT: ldr z27, [x0]44; CHECK-NEXT: mov z28.d, z1.d45; CHECK-NEXT: sel { z0.h - z3.h }, pn8, { z28.h - z31.h }, { z24.h - z27.h }46; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload47; CHECK-NEXT: addvl sp, sp, #148; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload49; CHECK-NEXT: ret50 %res = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sel.x4.nxv8i16(target("aarch64.svcount") %pn, <vscale x 8 x i16> %zn1, <vscale x 8 x i16> %zn2, <vscale x 8 x i16> %zn3, <vscale x 8 x i16> %zn4, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2, <vscale x 8 x i16> %zm3, <vscale x 8 x i16> %zm4)51 ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %res52}53 54define { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @sel_x4_f16(target("aarch64.svcount") %pn, <vscale x 8 x half> %unused, <vscale x 8 x half> %zn1, <vscale x 8 x half> %zn2, <vscale x 8 x half> %zn3, <vscale x 8 x half> %zn4, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2, <vscale x 8 x half> %zm3, <vscale x 8 x half> %zm4) nounwind {55; CHECK-LABEL: sel_x4_f16:56; CHECK: // %bb.0:57; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill58; CHECK-NEXT: addvl sp, sp, #-159; CHECK-NEXT: mov z26.d, z7.d60; CHECK-NEXT: mov z31.d, z4.d61; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill62; CHECK-NEXT: mov z25.d, z6.d63; CHECK-NEXT: mov z30.d, z3.d64; CHECK-NEXT: mov p8.b, p0.b65; CHECK-NEXT: mov z24.d, z5.d66; CHECK-NEXT: mov z29.d, z2.d67; CHECK-NEXT: ldr z27, [x0]68; CHECK-NEXT: mov z28.d, z1.d69; CHECK-NEXT: sel { z0.h - z3.h }, pn8, { z28.h - z31.h }, { z24.h - z27.h }70; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload71; CHECK-NEXT: addvl sp, sp, #172; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload73; CHECK-NEXT: ret74 %res = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.sel.x4.nxv8f16(target("aarch64.svcount") %pn, <vscale x 8 x half> %zn1, <vscale x 8 x half> %zn2, <vscale x 8 x half> %zn3, <vscale x 8 x half> %zn4, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2, <vscale x 8 x half> %zm3, <vscale x 8 x half> %zm4)75 ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %res76}77 78define { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @sel_x4_bf16(target("aarch64.svcount") %pn, <vscale x 8 x bfloat> %unused, <vscale x 8 x bfloat> %zn1, <vscale x 8 x bfloat> %zn2, <vscale x 8 x bfloat> %zn3, <vscale x 8 x bfloat> %zn4, <vscale x 8 x bfloat> %zm1, <vscale x 8 x bfloat> %zm2, <vscale x 8 x bfloat> %zm3, <vscale x 8 x bfloat> %zm4) nounwind {79; CHECK-LABEL: sel_x4_bf16:80; CHECK: // %bb.0:81; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill82; CHECK-NEXT: addvl sp, sp, #-183; CHECK-NEXT: mov z26.d, z7.d84; CHECK-NEXT: mov z31.d, z4.d85; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill86; CHECK-NEXT: mov z25.d, z6.d87; CHECK-NEXT: mov z30.d, z3.d88; CHECK-NEXT: mov p8.b, p0.b89; CHECK-NEXT: mov z24.d, z5.d90; CHECK-NEXT: mov z29.d, z2.d91; CHECK-NEXT: ldr z27, [x0]92; CHECK-NEXT: mov z28.d, z1.d93; CHECK-NEXT: sel { z0.h - z3.h }, pn8, { z28.h - z31.h }, { z24.h - z27.h }94; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload95; CHECK-NEXT: addvl sp, sp, #196; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload97; CHECK-NEXT: ret98 %res = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.sel.x4.nxv8bf16(target("aarch64.svcount") %pn, <vscale x 8 x bfloat> %zn1, <vscale x 8 x bfloat> %zn2, <vscale x 8 x bfloat> %zn3, <vscale x 8 x bfloat> %zn4, <vscale x 8 x bfloat> %zm1, <vscale x 8 x bfloat> %zm2, <vscale x 8 x bfloat> %zm3, <vscale x 8 x bfloat> %zm4)99 ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %res100}101 102define { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @sel_x4_i32(target("aarch64.svcount") %pn, <vscale x 4 x i32> %unused, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3, <vscale x 4 x i32> %zn4, <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2, <vscale x 4 x i32> %zm3, <vscale x 4 x i32> %zm4) nounwind {103; CHECK-LABEL: sel_x4_i32:104; CHECK: // %bb.0:105; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill106; CHECK-NEXT: addvl sp, sp, #-1107; CHECK-NEXT: mov z26.d, z7.d108; CHECK-NEXT: mov z31.d, z4.d109; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill110; CHECK-NEXT: mov z25.d, z6.d111; CHECK-NEXT: mov z30.d, z3.d112; CHECK-NEXT: mov p8.b, p0.b113; CHECK-NEXT: mov z24.d, z5.d114; CHECK-NEXT: mov z29.d, z2.d115; CHECK-NEXT: ldr z27, [x0]116; CHECK-NEXT: mov z28.d, z1.d117; CHECK-NEXT: sel { z0.s - z3.s }, pn8, { z28.s - z31.s }, { z24.s - z27.s }118; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload119; CHECK-NEXT: addvl sp, sp, #1120; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload121; CHECK-NEXT: ret122 %res = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sel.x4.nxv4i32(target("aarch64.svcount") %pn, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3, <vscale x 4 x i32> %zn4, <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2, <vscale x 4 x i32> %zm3, <vscale x 4 x i32> %zm4)123 ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %res124}125 126define { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @sel_x4_f32(target("aarch64.svcount") %pn, <vscale x 4 x float> %unused, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3, <vscale x 4 x float> %zn4, <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2, <vscale x 4 x float> %zm3, <vscale x 4 x float> %zm4) nounwind {127; CHECK-LABEL: sel_x4_f32:128; CHECK: // %bb.0:129; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill130; CHECK-NEXT: addvl sp, sp, #-1131; CHECK-NEXT: mov z26.d, z7.d132; CHECK-NEXT: mov z31.d, z4.d133; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill134; CHECK-NEXT: mov z25.d, z6.d135; CHECK-NEXT: mov z30.d, z3.d136; CHECK-NEXT: mov p8.b, p0.b137; CHECK-NEXT: mov z24.d, z5.d138; CHECK-NEXT: mov z29.d, z2.d139; CHECK-NEXT: ldr z27, [x0]140; CHECK-NEXT: mov z28.d, z1.d141; CHECK-NEXT: sel { z0.s - z3.s }, pn8, { z28.s - z31.s }, { z24.s - z27.s }142; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload143; CHECK-NEXT: addvl sp, sp, #1144; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload145; CHECK-NEXT: ret146 %res = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.sel.x4.nxv4f32(target("aarch64.svcount") %pn, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3, <vscale x 4 x float> %zn4, <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2, <vscale x 4 x float> %zm3, <vscale x 4 x float> %zm4)147 ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %res148}149 150define { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @sel_x4_i64(target("aarch64.svcount") %pn, <vscale x 2 x i64> %unused, <vscale x 2 x i64> %zn1, <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3, <vscale x 2 x i64> %zn4, <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3, <vscale x 2 x i64> %zm4) nounwind {151; CHECK-LABEL: sel_x4_i64:152; CHECK: // %bb.0:153; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill154; CHECK-NEXT: addvl sp, sp, #-1155; CHECK-NEXT: mov z26.d, z7.d156; CHECK-NEXT: mov z31.d, z4.d157; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill158; CHECK-NEXT: mov z25.d, z6.d159; CHECK-NEXT: mov z30.d, z3.d160; CHECK-NEXT: mov p8.b, p0.b161; CHECK-NEXT: mov z24.d, z5.d162; CHECK-NEXT: mov z29.d, z2.d163; CHECK-NEXT: ldr z27, [x0]164; CHECK-NEXT: mov z28.d, z1.d165; CHECK-NEXT: sel { z0.d - z3.d }, pn8, { z28.d - z31.d }, { z24.d - z27.d }166; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload167; CHECK-NEXT: addvl sp, sp, #1168; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload169; CHECK-NEXT: ret170 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sel.x4.nxv2i64(target("aarch64.svcount") %pn, <vscale x 2 x i64> %zn1, <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3, <vscale x 2 x i64> %zn4, <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3, <vscale x 2 x i64> %zm4)171 ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %res172}173 174define { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @sel_x4_f64(target("aarch64.svcount") %pn, <vscale x 2 x double> %unused, <vscale x 2 x double> %zn1, <vscale x 2 x double> %zn2, <vscale x 2 x double> %zn3, <vscale x 2 x double> %zn4, <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2, <vscale x 2 x double> %zm3, <vscale x 2 x double> %zm4) nounwind {175; CHECK-LABEL: sel_x4_f64:176; CHECK: // %bb.0:177; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill178; CHECK-NEXT: addvl sp, sp, #-1179; CHECK-NEXT: mov z26.d, z7.d180; CHECK-NEXT: mov z31.d, z4.d181; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill182; CHECK-NEXT: mov z25.d, z6.d183; CHECK-NEXT: mov z30.d, z3.d184; CHECK-NEXT: mov p8.b, p0.b185; CHECK-NEXT: mov z24.d, z5.d186; CHECK-NEXT: mov z29.d, z2.d187; CHECK-NEXT: ldr z27, [x0]188; CHECK-NEXT: mov z28.d, z1.d189; CHECK-NEXT: sel { z0.d - z3.d }, pn8, { z28.d - z31.d }, { z24.d - z27.d }190; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload191; CHECK-NEXT: addvl sp, sp, #1192; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload193; CHECK-NEXT: ret194 %res = call { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.sel.x4.nxv2f64(target("aarch64.svcount") %pn, <vscale x 2 x double> %zn1, <vscale x 2 x double> %zn2, <vscale x 2 x double> %zn3, <vscale x 2 x double> %zn4, <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2, <vscale x 2 x double> %zm3, <vscale x 2 x double> %zm4)195 ret { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %res196}197 198 199; == 8 to 64-bit elements ==200declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sel.x4.nxv16i8(target("aarch64.svcount") %pn, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, <vscale x 16 x i8> %zn4, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3, <vscale x 16 x i8> %zm4)201declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sel.x4.nxv8i16(target("aarch64.svcount") %pn, <vscale x 8 x i16> %zn1, <vscale x 8 x i16> %zn2, <vscale x 8 x i16> %zn3, <vscale x 8 x i16> %zn4, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2, <vscale x 8 x i16> %zm3, <vscale x 8 x i16> %zm4)202declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sel.x4.nxv4i32(target("aarch64.svcount") %pn, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3, <vscale x 4 x i32> %zn4, <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2, <vscale x 4 x i32> %zm3, <vscale x 4 x i32> %zm4)203declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sel.x4.nxv2i64(target("aarch64.svcount") %pn, <vscale x 2 x i64> %zn1, <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3, <vscale x 2 x i64> %zn4, <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3, <vscale x 2 x i64> %zm4)204declare { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.sel.x4.nxv8f16(target("aarch64.svcount") %pn, <vscale x 8 x half> %zn1, <vscale x 8 x half> %zn2, <vscale x 8 x half> %zn3, <vscale x 8 x half> %zn4, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2, <vscale x 8 x half> %zm3, <vscale x 8 x half> %zm4)205declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.sel.x4.nxv8bf16(target("aarch64.svcount") %pn, <vscale x 8 x bfloat> %zn1, <vscale x 8 x bfloat> %zn2, <vscale x 8 x bfloat> %zn3, <vscale x 8 x bfloat> %zn4, <vscale x 8 x bfloat> %zm1, <vscale x 8 x bfloat> %zm2, <vscale x 8 x bfloat> %zm3, <vscale x 8 x bfloat> %zm4)206declare { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.sel.x4.nxv4f32(target("aarch64.svcount") %pn, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3, <vscale x 4 x float> %zn4, <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2, <vscale x 4 x float> %zm3, <vscale x 4 x float> %zm4)207declare { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.sel.x4.nxv2f64(target("aarch64.svcount") %pn, <vscale x 2 x double> %zn1, <vscale x 2 x double> %zn2, <vscale x 2 x double> %zn3, <vscale x 2 x double> %zn4, <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2, <vscale x 2 x double> %zm3, <vscale x 2 x double> %zm4)208