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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve2p1 < %s | FileCheck %s3 4; ST1W5 6define void @test_svst1wq_i32_ss(<vscale x 4 x i32> %zt, <vscale x 1 x i1> %pred, ptr %base, i64 %offset) {7; CHECK-LABEL: test_svst1wq_i32_ss:8; CHECK: // %bb.0:9; CHECK-NEXT: st1w { z0.q }, p0, [x0, x1, lsl #2]10; CHECK-NEXT: ret11 %gep = getelementptr i32, ptr %base, i64 %offset12 call void @llvm.aarch64.sve.st1wq.nxv4i32(<vscale x 4 x i32> %zt, <vscale x 1 x i1> %pred, ptr %gep)13 ret void14}15 16define void @test_svst1wq_i32_si(<vscale x 4 x i32> %zt, <vscale x 1 x i1> %pred, ptr %base) {17; CHECK-LABEL: test_svst1wq_i32_si:18; CHECK: // %bb.0:19; CHECK-NEXT: st1w { z0.q }, p0, [x0, #-8, mul vl]20; CHECK-NEXT: st1w { z0.q }, p0, [x0, #7, mul vl]21; CHECK-NEXT: ret22 %gep1 = getelementptr inbounds <vscale x 1 x i32>, ptr %base, i64 -823 call void @llvm.aarch64.sve.st1wq.nxv4i32(<vscale x 4 x i32> %zt, <vscale x 1 x i1> %pred, ptr %gep1)24 25 %gep2 = getelementptr inbounds <vscale x 1 x i32>, ptr %base, i64 726 call void @llvm.aarch64.sve.st1wq.nxv4i32(<vscale x 4 x i32> %zt, <vscale x 1 x i1> %pred, ptr %gep2)27 ret void28}29 30define void @test_svst1wq_i32_out_of_bound(<vscale x 4 x i32> %zt, <vscale x 1 x i1> %pred, ptr %base) {31; CHECK-LABEL: test_svst1wq_i32_out_of_bound:32; CHECK: // %bb.0:33; CHECK-NEXT: incb x0, all, mul #234; CHECK-NEXT: st1w { z0.q }, p0, [x0]35; CHECK-NEXT: ret36 %gep = getelementptr inbounds <vscale x 1 x i32>, ptr %base, i64 837 call void @llvm.aarch64.sve.st1wq.nxv4i32(<vscale x 4 x i32> %zt, <vscale x 1 x i1> %pred, ptr %gep)38 ret void39}40 41define void @test_svst1wq_f32_ss(<vscale x 4 x float> %zt, <vscale x 1 x i1> %pred, ptr %base, i64 %offset) {42; CHECK-LABEL: test_svst1wq_f32_ss:43; CHECK: // %bb.0:44; CHECK-NEXT: st1w { z0.q }, p0, [x0, x1, lsl #2]45; CHECK-NEXT: ret46 %gep = getelementptr float, ptr %base, i64 %offset47 call void @llvm.aarch64.sve.st1wq.nxv4f32(<vscale x 4 x float> %zt, <vscale x 1 x i1> %pred, ptr %gep)48 ret void49}50 51define void @test_svst1wq_f32_si(<vscale x 4 x float> %zt, <vscale x 1 x i1> %pred, ptr %base) {52; CHECK-LABEL: test_svst1wq_f32_si:53; CHECK: // %bb.0:54; CHECK-NEXT: st1w { z0.q }, p0, [x0, #-8, mul vl]55; CHECK-NEXT: st1w { z0.q }, p0, [x0, #7, mul vl]56; CHECK-NEXT: ret57 %gep1 = getelementptr inbounds <vscale x 1 x float>, ptr %base, i64 -858 call void @llvm.aarch64.sve.st1wq.nxv4f32(<vscale x 4 x float> %zt, <vscale x 1 x i1> %pred, ptr %gep1)59 60 %gep2 = getelementptr inbounds <vscale x 1 x float>, ptr %base, i64 761 call void @llvm.aarch64.sve.st1wq.nxv4f32(<vscale x 4 x float> %zt, <vscale x 1 x i1> %pred, ptr %gep2)62 ret void63}64 65; ST1D66 67define void @test_svst1dq_i64_ss(<vscale x 2 x i64> %zt, <vscale x 1 x i1> %pred, ptr %base, i64 %offset) {68; CHECK-LABEL: test_svst1dq_i64_ss:69; CHECK: // %bb.0:70; CHECK-NEXT: st1d { z0.q }, p0, [x0, x1, lsl #3]71; CHECK-NEXT: ret72 %gep = getelementptr i64, ptr %base, i64 %offset73 call void @llvm.aarch64.sve.st1dq.nxv2i64(<vscale x 2 x i64> %zt, <vscale x 1 x i1> %pred, ptr %gep)74 ret void75}76 77define void @test_svst1dq_i64_si(<vscale x 2 x i64> %zt, <vscale x 1 x i1> %pred, ptr %base) {78; CHECK-LABEL: test_svst1dq_i64_si:79; CHECK: // %bb.0:80; CHECK-NEXT: st1d { z0.q }, p0, [x0, #-8, mul vl]81; CHECK-NEXT: st1d { z0.q }, p0, [x0, #7, mul vl]82; CHECK-NEXT: ret83 %gep1 = getelementptr inbounds <vscale x 1 x i64>, ptr %base, i64 -884 call void @llvm.aarch64.sve.st1dq.nxv2i64(<vscale x 2 x i64> %zt, <vscale x 1 x i1> %pred, ptr %gep1)85 86 %gep2 = getelementptr inbounds <vscale x 1 x i64>, ptr %base, i64 787 call void @llvm.aarch64.sve.st1dq.nxv2i64(<vscale x 2 x i64> %zt, <vscale x 1 x i1> %pred, ptr %gep2)88 ret void89}90 91define void @test_svst1dq_i64_out_of_bound(<vscale x 2 x i64> %zt, <vscale x 1 x i1> %pred, ptr %base) {92; CHECK-LABEL: test_svst1dq_i64_out_of_bound:93; CHECK: // %bb.0:94; CHECK-NEXT: addvl x8, x0, #-595; CHECK-NEXT: st1d { z0.q }, p0, [x8]96; CHECK-NEXT: ret97 %gep = getelementptr inbounds <vscale x 1 x i64>, ptr %base, i64 -1098 call void @llvm.aarch64.sve.st1dq.nxv2i64(<vscale x 2 x i64> %zt, <vscale x 1 x i1> %pred, ptr %gep)99 ret void100}101 102define void @test_svst1dq_f64_ss(<vscale x 2 x double> %zt, <vscale x 1 x i1> %pred, ptr %base, i64 %offset) {103; CHECK-LABEL: test_svst1dq_f64_ss:104; CHECK: // %bb.0:105; CHECK-NEXT: st1d { z0.q }, p0, [x0, x1, lsl #3]106; CHECK-NEXT: ret107 %gep = getelementptr double, ptr %base, i64 %offset108 call void @llvm.aarch64.sve.st1dq.nxv2f64(<vscale x 2 x double> %zt, <vscale x 1 x i1> %pred, ptr %gep)109 ret void110}111 112define void @test_svst1dq_f64_si(<vscale x 2 x double> %zt, <vscale x 1 x i1> %pred, ptr %base) {113; CHECK-LABEL: test_svst1dq_f64_si:114; CHECK: // %bb.0:115; CHECK-NEXT: st1d { z0.q }, p0, [x0, #-8, mul vl]116; CHECK-NEXT: st1d { z0.q }, p0, [x0, #7, mul vl]117; CHECK-NEXT: ret118 %gep1 = getelementptr inbounds <vscale x 1 x double>, ptr %base, i64 -8119 call void @llvm.aarch64.sve.st1dq.nxv2f64(<vscale x 2 x double> %zt, <vscale x 1 x i1> %pred, ptr %gep1)120 121 %gep2 = getelementptr inbounds <vscale x 1 x double>, ptr %base, i64 7122 call void @llvm.aarch64.sve.st1dq.nxv2f64(<vscale x 2 x double> %zt, <vscale x 1 x i1> %pred, ptr %gep2)123 ret void124}125 126declare void @llvm.aarch64.sve.st1wq.nxv4i32(<vscale x 4 x i32>, <vscale x 1 x i1>, ptr)127declare void @llvm.aarch64.sve.st1wq.nxv4f32(<vscale x 4 x float>, <vscale x 1 x i1>, ptr)128 129declare void @llvm.aarch64.sve.st1dq.nxv2i64(<vscale x 2 x i64>, <vscale x 1 x i1>, ptr)130declare void @llvm.aarch64.sve.st1dq.nxv2f64(<vscale x 2 x double>, <vscale x 1 x i1>, ptr)131