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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1 < %s | FileCheck %s3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -force-streaming < %s | FileCheck %s4; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme,+sve2p1 -force-streaming < %s | FileCheck %s5 6; == Normal Multi-Vector Consecutive Stores ==7 8define void @st1_x2_i8(<vscale x 16 x i8> %unused, <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, target("aarch64.svcount") %pn, ptr %ptr) nounwind {9; CHECK-LABEL: st1_x2_i8:10; CHECK: // %bb.0:11; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill12; CHECK-NEXT: addvl sp, sp, #-113; CHECK-NEXT: mov z3.d, z2.d14; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill15; CHECK-NEXT: mov p8.b, p0.b16; CHECK-NEXT: mov z2.d, z1.d17; CHECK-NEXT: st1b { z2.b, z3.b }, pn8, [x0]18; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload19; CHECK-NEXT: addvl sp, sp, #120; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload21; CHECK-NEXT: ret22 call void @llvm.aarch64.sve.st1.pn.x2.nxv16i8(<vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, target("aarch64.svcount") %pn, ptr %ptr);23 ret void24}25 26define void @st1_x2_i16(<vscale x 16 x i8> %unused, <vscale x 8 x i16> %zn0, <vscale x 8 x i16> %zn1, target("aarch64.svcount") %pn, ptr %ptr) nounwind {27; CHECK-LABEL: st1_x2_i16:28; CHECK: // %bb.0:29; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill30; CHECK-NEXT: addvl sp, sp, #-131; CHECK-NEXT: mov z3.d, z2.d32; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill33; CHECK-NEXT: mov p8.b, p0.b34; CHECK-NEXT: mov z2.d, z1.d35; CHECK-NEXT: st1h { z2.h, z3.h }, pn8, [x0]36; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload37; CHECK-NEXT: addvl sp, sp, #138; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload39; CHECK-NEXT: ret40 call void @llvm.aarch64.sve.st1.pn.x2.nxv8i16(<vscale x 8 x i16> %zn0, <vscale x 8 x i16> %zn1, target("aarch64.svcount") %pn, ptr %ptr);41 ret void42}43 44define void @st1_x2_i32(<vscale x 16 x i8> %unused, <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1, target("aarch64.svcount") %pn, ptr %ptr) nounwind {45; CHECK-LABEL: st1_x2_i32:46; CHECK: // %bb.0:47; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill48; CHECK-NEXT: addvl sp, sp, #-149; CHECK-NEXT: mov z3.d, z2.d50; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill51; CHECK-NEXT: mov p8.b, p0.b52; CHECK-NEXT: mov z2.d, z1.d53; CHECK-NEXT: st1w { z2.s, z3.s }, pn8, [x0]54; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload55; CHECK-NEXT: addvl sp, sp, #156; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload57; CHECK-NEXT: ret58 call void @llvm.aarch64.sve.st1.pn.x2.nxv4i32(<vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1, target("aarch64.svcount") %pn, ptr %ptr);59 ret void60}61 62define void @st1_x2_i64(<vscale x 16 x i8> %unused, <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1, target("aarch64.svcount") %pn, ptr %ptr) nounwind {63; CHECK-LABEL: st1_x2_i64:64; CHECK: // %bb.0:65; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill66; CHECK-NEXT: addvl sp, sp, #-167; CHECK-NEXT: mov z3.d, z2.d68; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill69; CHECK-NEXT: mov p8.b, p0.b70; CHECK-NEXT: mov z2.d, z1.d71; CHECK-NEXT: st1d { z2.d, z3.d }, pn8, [x0]72; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload73; CHECK-NEXT: addvl sp, sp, #174; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload75; CHECK-NEXT: ret76 call void @llvm.aarch64.sve.st1.pn.x2.nxv2i64(<vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1, target("aarch64.svcount") %pn, ptr %ptr);77 ret void78}79 80define void @st1_x2_f16(<vscale x 16 x i8> %unused, <vscale x 8 x half> %zn0, <vscale x 8 x half> %zn1, target("aarch64.svcount") %pn, ptr %ptr) nounwind {81; CHECK-LABEL: st1_x2_f16:82; CHECK: // %bb.0:83; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill84; CHECK-NEXT: addvl sp, sp, #-185; CHECK-NEXT: mov z3.d, z2.d86; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill87; CHECK-NEXT: mov p8.b, p0.b88; CHECK-NEXT: mov z2.d, z1.d89; CHECK-NEXT: st1h { z2.h, z3.h }, pn8, [x0]90; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload91; CHECK-NEXT: addvl sp, sp, #192; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload93; CHECK-NEXT: ret94 call void @llvm.aarch64.sve.st1.pn.x2.nxv8f16(<vscale x 8 x half> %zn0, <vscale x 8 x half> %zn1, target("aarch64.svcount") %pn, ptr %ptr);95 ret void96}97 98define void @st1_x2_bf16(<vscale x 16 x i8> %unused, <vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1, target("aarch64.svcount") %pn, ptr %ptr) nounwind {99; CHECK-LABEL: st1_x2_bf16:100; CHECK: // %bb.0:101; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill102; CHECK-NEXT: addvl sp, sp, #-1103; CHECK-NEXT: mov z3.d, z2.d104; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill105; CHECK-NEXT: mov p8.b, p0.b106; CHECK-NEXT: mov z2.d, z1.d107; CHECK-NEXT: st1h { z2.h, z3.h }, pn8, [x0]108; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload109; CHECK-NEXT: addvl sp, sp, #1110; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload111; CHECK-NEXT: ret112 call void @llvm.aarch64.sve.st1.pn.x2.nxv8bf16(<vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1, target("aarch64.svcount") %pn, ptr %ptr);113 ret void114}115 116define void @st1_x2_f32(<vscale x 16 x i8> %unused, <vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1, target("aarch64.svcount") %pn, ptr %ptr) nounwind {117; CHECK-LABEL: st1_x2_f32:118; CHECK: // %bb.0:119; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill120; CHECK-NEXT: addvl sp, sp, #-1121; CHECK-NEXT: mov z3.d, z2.d122; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill123; CHECK-NEXT: mov p8.b, p0.b124; CHECK-NEXT: mov z2.d, z1.d125; CHECK-NEXT: st1w { z2.s, z3.s }, pn8, [x0]126; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload127; CHECK-NEXT: addvl sp, sp, #1128; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload129; CHECK-NEXT: ret130 call void @llvm.aarch64.sve.st1.pn.x2.nxv4f32(<vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1, target("aarch64.svcount") %pn, ptr %ptr);131 ret void132}133 134define void @st1_x2_f64(<vscale x 16 x i8> %unused, <vscale x 2 x double> %zn0, <vscale x 2 x double> %zn1, target("aarch64.svcount") %pn, ptr %ptr) nounwind {135; CHECK-LABEL: st1_x2_f64:136; CHECK: // %bb.0:137; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill138; CHECK-NEXT: addvl sp, sp, #-1139; CHECK-NEXT: mov z3.d, z2.d140; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill141; CHECK-NEXT: mov p8.b, p0.b142; CHECK-NEXT: mov z2.d, z1.d143; CHECK-NEXT: st1d { z2.d, z3.d }, pn8, [x0]144; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload145; CHECK-NEXT: addvl sp, sp, #1146; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload147; CHECK-NEXT: ret148 call void @llvm.aarch64.sve.st1.pn.x2.nxv2f64(<vscale x 2 x double> %zn0, <vscale x 2 x double> %zn1, target("aarch64.svcount") %pn, ptr %ptr);149 ret void150}151 152define void @st1_x4_i8(<vscale x 16 x i8> %unused, <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, target("aarch64.svcount") %pn, ptr %ptr) nounwind {153; CHECK-LABEL: st1_x4_i8:154; CHECK: // %bb.0:155; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill156; CHECK-NEXT: addvl sp, sp, #-1157; CHECK-NEXT: mov z7.d, z4.d158; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill159; CHECK-NEXT: mov p8.b, p0.b160; CHECK-NEXT: mov z6.d, z3.d161; CHECK-NEXT: mov z5.d, z2.d162; CHECK-NEXT: mov z4.d, z1.d163; CHECK-NEXT: st1b { z4.b - z7.b }, pn8, [x0]164; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload165; CHECK-NEXT: addvl sp, sp, #1166; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload167; CHECK-NEXT: ret168 call void @llvm.aarch64.sve.st1.pn.x4.nxv16i8(<vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, target("aarch64.svcount") %pn, ptr %ptr);169 ret void170}171 172define void @st1_x4_i16(<vscale x 16 x i8> %unused, <vscale x 8 x i16> %zn0, <vscale x 8 x i16> %zn1, <vscale x 8 x i16> %zn2, <vscale x 8 x i16> %zn3, target("aarch64.svcount") %pn, ptr %ptr) nounwind {173; CHECK-LABEL: st1_x4_i16:174; CHECK: // %bb.0:175; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill176; CHECK-NEXT: addvl sp, sp, #-1177; CHECK-NEXT: mov z7.d, z4.d178; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill179; CHECK-NEXT: mov p8.b, p0.b180; CHECK-NEXT: mov z6.d, z3.d181; CHECK-NEXT: mov z5.d, z2.d182; CHECK-NEXT: mov z4.d, z1.d183; CHECK-NEXT: st1h { z4.h - z7.h }, pn8, [x0]184; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload185; CHECK-NEXT: addvl sp, sp, #1186; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload187; CHECK-NEXT: ret188 call void @llvm.aarch64.sve.st1.pn.x4.nxv8i16(<vscale x 8 x i16> %zn0, <vscale x 8 x i16> %zn1, <vscale x 8 x i16> %zn2, <vscale x 8 x i16> %zn3, target("aarch64.svcount") %pn, ptr %ptr);189 ret void190}191 192define void @st1_x4_i32(<vscale x 16 x i8> %unused, <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3, target("aarch64.svcount") %pn, ptr %ptr) nounwind {193; CHECK-LABEL: st1_x4_i32:194; CHECK: // %bb.0:195; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill196; CHECK-NEXT: addvl sp, sp, #-1197; CHECK-NEXT: mov z7.d, z4.d198; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill199; CHECK-NEXT: mov p8.b, p0.b200; CHECK-NEXT: mov z6.d, z3.d201; CHECK-NEXT: mov z5.d, z2.d202; CHECK-NEXT: mov z4.d, z1.d203; CHECK-NEXT: st1w { z4.s - z7.s }, pn8, [x0]204; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload205; CHECK-NEXT: addvl sp, sp, #1206; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload207; CHECK-NEXT: ret208 call void @llvm.aarch64.sve.st1.pn.x4.nxv4i32(<vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3, target("aarch64.svcount") %pn, ptr %ptr);209 ret void210}211 212define void @st1_x4_i64(<vscale x 16 x i8> %unused, <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1, <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3, target("aarch64.svcount") %pn, ptr %ptr) nounwind {213; CHECK-LABEL: st1_x4_i64:214; CHECK: // %bb.0:215; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill216; CHECK-NEXT: addvl sp, sp, #-1217; CHECK-NEXT: mov z7.d, z4.d218; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill219; CHECK-NEXT: mov p8.b, p0.b220; CHECK-NEXT: mov z6.d, z3.d221; CHECK-NEXT: mov z5.d, z2.d222; CHECK-NEXT: mov z4.d, z1.d223; CHECK-NEXT: st1d { z4.d - z7.d }, pn8, [x0]224; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload225; CHECK-NEXT: addvl sp, sp, #1226; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload227; CHECK-NEXT: ret228 call void @llvm.aarch64.sve.st1.pn.x4.nxv2i64(<vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1, <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3, target("aarch64.svcount") %pn, ptr %ptr);229 ret void230}231 232define void @st1_x4_f16(<vscale x 16 x i8> %unused, <vscale x 8 x half> %zn0, <vscale x 8 x half> %zn1, <vscale x 8 x half> %zn2, <vscale x 8 x half> %zn3, target("aarch64.svcount") %pn, ptr %ptr) nounwind {233; CHECK-LABEL: st1_x4_f16:234; CHECK: // %bb.0:235; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill236; CHECK-NEXT: addvl sp, sp, #-1237; CHECK-NEXT: mov z7.d, z4.d238; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill239; CHECK-NEXT: mov p8.b, p0.b240; CHECK-NEXT: mov z6.d, z3.d241; CHECK-NEXT: mov z5.d, z2.d242; CHECK-NEXT: mov z4.d, z1.d243; CHECK-NEXT: st1h { z4.h - z7.h }, pn8, [x0]244; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload245; CHECK-NEXT: addvl sp, sp, #1246; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload247; CHECK-NEXT: ret248 call void @llvm.aarch64.sve.st1.pn.x4.nxv8f16(<vscale x 8 x half> %zn0, <vscale x 8 x half> %zn1, <vscale x 8 x half> %zn2, <vscale x 8 x half> %zn3, target("aarch64.svcount") %pn, ptr %ptr);249 ret void250}251 252define void @st1_x4_bf16(<vscale x 16 x i8> %unused, <vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1, <vscale x 8 x bfloat> %zn2, <vscale x 8 x bfloat> %zn3, target("aarch64.svcount") %pn, ptr %ptr) nounwind {253; CHECK-LABEL: st1_x4_bf16:254; CHECK: // %bb.0:255; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill256; CHECK-NEXT: addvl sp, sp, #-1257; CHECK-NEXT: mov z7.d, z4.d258; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill259; CHECK-NEXT: mov p8.b, p0.b260; CHECK-NEXT: mov z6.d, z3.d261; CHECK-NEXT: mov z5.d, z2.d262; CHECK-NEXT: mov z4.d, z1.d263; CHECK-NEXT: st1h { z4.h - z7.h }, pn8, [x0]264; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload265; CHECK-NEXT: addvl sp, sp, #1266; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload267; CHECK-NEXT: ret268 call void @llvm.aarch64.sve.st1.pn.x4.nxv8bf16(<vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1, <vscale x 8 x bfloat> %zn2, <vscale x 8 x bfloat> %zn3, target("aarch64.svcount") %pn, ptr %ptr);269 ret void270}271 272define void @st1_x4_f32(<vscale x 16 x i8> %unused, <vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3, target("aarch64.svcount") %pn, ptr %ptr) nounwind {273; CHECK-LABEL: st1_x4_f32:274; CHECK: // %bb.0:275; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill276; CHECK-NEXT: addvl sp, sp, #-1277; CHECK-NEXT: mov z7.d, z4.d278; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill279; CHECK-NEXT: mov p8.b, p0.b280; CHECK-NEXT: mov z6.d, z3.d281; CHECK-NEXT: mov z5.d, z2.d282; CHECK-NEXT: mov z4.d, z1.d283; CHECK-NEXT: st1w { z4.s - z7.s }, pn8, [x0]284; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload285; CHECK-NEXT: addvl sp, sp, #1286; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload287; CHECK-NEXT: ret288 call void @llvm.aarch64.sve.st1.pn.x4.nxv4f32(<vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3, target("aarch64.svcount") %pn, ptr %ptr);289 ret void290}291 292define void @st1_x4_f64(<vscale x 16 x i8> %unused, <vscale x 2 x double> %zn0, <vscale x 2 x double> %zn1, <vscale x 2 x double> %zn2, <vscale x 2 x double> %zn3, target("aarch64.svcount") %pn, ptr %ptr) nounwind {293; CHECK-LABEL: st1_x4_f64:294; CHECK: // %bb.0:295; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill296; CHECK-NEXT: addvl sp, sp, #-1297; CHECK-NEXT: mov z7.d, z4.d298; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill299; CHECK-NEXT: mov p8.b, p0.b300; CHECK-NEXT: mov z6.d, z3.d301; CHECK-NEXT: mov z5.d, z2.d302; CHECK-NEXT: mov z4.d, z1.d303; CHECK-NEXT: st1d { z4.d - z7.d }, pn8, [x0]304; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload305; CHECK-NEXT: addvl sp, sp, #1306; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload307; CHECK-NEXT: ret308 call void @llvm.aarch64.sve.st1.pn.x4.nxv2f64(<vscale x 2 x double> %zn0, <vscale x 2 x double> %zn1, <vscale x 2 x double> %zn2, <vscale x 2 x double> %zn3, target("aarch64.svcount") %pn, ptr %ptr);309 ret void310}311 312; == Non-temporal Multi-Vector Consecutive Stores ==313 314define void @stnt1_x2_i8(<vscale x 16 x i8> %unused, <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, target("aarch64.svcount") %pn, ptr %ptr) nounwind {315; CHECK-LABEL: stnt1_x2_i8:316; CHECK: // %bb.0:317; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill318; CHECK-NEXT: addvl sp, sp, #-1319; CHECK-NEXT: mov z3.d, z2.d320; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill321; CHECK-NEXT: mov p8.b, p0.b322; CHECK-NEXT: mov z2.d, z1.d323; CHECK-NEXT: stnt1b { z2.b, z3.b }, pn8, [x0]324; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload325; CHECK-NEXT: addvl sp, sp, #1326; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload327; CHECK-NEXT: ret328 call void @llvm.aarch64.sve.stnt1.pn.x2.nxv16i8(<vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, target("aarch64.svcount") %pn, ptr %ptr);329 ret void330}331 332define void @stnt1_x2_i16(<vscale x 16 x i8> %unused, <vscale x 8 x i16> %zn0, <vscale x 8 x i16> %zn1, target("aarch64.svcount") %pn, ptr %ptr) nounwind {333; CHECK-LABEL: stnt1_x2_i16:334; CHECK: // %bb.0:335; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill336; CHECK-NEXT: addvl sp, sp, #-1337; CHECK-NEXT: mov z3.d, z2.d338; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill339; CHECK-NEXT: mov p8.b, p0.b340; CHECK-NEXT: mov z2.d, z1.d341; CHECK-NEXT: stnt1h { z2.h, z3.h }, pn8, [x0]342; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload343; CHECK-NEXT: addvl sp, sp, #1344; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload345; CHECK-NEXT: ret346 call void @llvm.aarch64.sve.stnt1.pn.x2.nxv8i16(<vscale x 8 x i16> %zn0, <vscale x 8 x i16> %zn1, target("aarch64.svcount") %pn, ptr %ptr);347 ret void348}349 350define void @stnt1_x2_i32(<vscale x 16 x i8> %unused, <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1, target("aarch64.svcount") %pn, ptr %ptr) nounwind {351; CHECK-LABEL: stnt1_x2_i32:352; CHECK: // %bb.0:353; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill354; CHECK-NEXT: addvl sp, sp, #-1355; CHECK-NEXT: mov z3.d, z2.d356; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill357; CHECK-NEXT: mov p8.b, p0.b358; CHECK-NEXT: mov z2.d, z1.d359; CHECK-NEXT: stnt1w { z2.s, z3.s }, pn8, [x0]360; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload361; CHECK-NEXT: addvl sp, sp, #1362; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload363; CHECK-NEXT: ret364 call void @llvm.aarch64.sve.stnt1.pn.x2.nxv4i32(<vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1, target("aarch64.svcount") %pn, ptr %ptr);365 ret void366}367 368define void @stnt1_x2_i64(<vscale x 16 x i8> %unused, <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1, target("aarch64.svcount") %pn, ptr %ptr) nounwind {369; CHECK-LABEL: stnt1_x2_i64:370; CHECK: // %bb.0:371; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill372; CHECK-NEXT: addvl sp, sp, #-1373; CHECK-NEXT: mov z3.d, z2.d374; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill375; CHECK-NEXT: mov p8.b, p0.b376; CHECK-NEXT: mov z2.d, z1.d377; CHECK-NEXT: stnt1d { z2.d, z3.d }, pn8, [x0]378; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload379; CHECK-NEXT: addvl sp, sp, #1380; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload381; CHECK-NEXT: ret382 call void @llvm.aarch64.sve.stnt1.pn.x2.nxv2i64(<vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1, target("aarch64.svcount") %pn, ptr %ptr);383 ret void384}385 386define void @stnt1_x2_f16(<vscale x 16 x i8> %unused, <vscale x 8 x half> %zn0, <vscale x 8 x half> %zn1, target("aarch64.svcount") %pn, ptr %ptr) nounwind {387; CHECK-LABEL: stnt1_x2_f16:388; CHECK: // %bb.0:389; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill390; CHECK-NEXT: addvl sp, sp, #-1391; CHECK-NEXT: mov z3.d, z2.d392; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill393; CHECK-NEXT: mov p8.b, p0.b394; CHECK-NEXT: mov z2.d, z1.d395; CHECK-NEXT: stnt1h { z2.h, z3.h }, pn8, [x0]396; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload397; CHECK-NEXT: addvl sp, sp, #1398; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload399; CHECK-NEXT: ret400 call void @llvm.aarch64.sve.stnt1.pn.x2.nxv8f16(<vscale x 8 x half> %zn0, <vscale x 8 x half> %zn1, target("aarch64.svcount") %pn, ptr %ptr);401 ret void402}403 404define void @stnt1_x2_bf16(<vscale x 16 x i8> %unused, <vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1, target("aarch64.svcount") %pn, ptr %ptr) nounwind {405; CHECK-LABEL: stnt1_x2_bf16:406; CHECK: // %bb.0:407; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill408; CHECK-NEXT: addvl sp, sp, #-1409; CHECK-NEXT: mov z3.d, z2.d410; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill411; CHECK-NEXT: mov p8.b, p0.b412; CHECK-NEXT: mov z2.d, z1.d413; CHECK-NEXT: stnt1h { z2.h, z3.h }, pn8, [x0]414; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload415; CHECK-NEXT: addvl sp, sp, #1416; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload417; CHECK-NEXT: ret418 call void @llvm.aarch64.sve.stnt1.pn.x2.nxv8bf16(<vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1, target("aarch64.svcount") %pn, ptr %ptr);419 ret void420}421 422define void @stnt1_x2_f32(<vscale x 16 x i8> %unused, <vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1, target("aarch64.svcount") %pn, ptr %ptr) nounwind {423; CHECK-LABEL: stnt1_x2_f32:424; CHECK: // %bb.0:425; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill426; CHECK-NEXT: addvl sp, sp, #-1427; CHECK-NEXT: mov z3.d, z2.d428; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill429; CHECK-NEXT: mov p8.b, p0.b430; CHECK-NEXT: mov z2.d, z1.d431; CHECK-NEXT: stnt1w { z2.s, z3.s }, pn8, [x0]432; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload433; CHECK-NEXT: addvl sp, sp, #1434; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload435; CHECK-NEXT: ret436 call void @llvm.aarch64.sve.stnt1.pn.x2.nxv4f32(<vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1, target("aarch64.svcount") %pn, ptr %ptr);437 ret void438}439 440define void @stnt1_x2_f64(<vscale x 16 x i8> %unused, <vscale x 2 x double> %zn0, <vscale x 2 x double> %zn1, target("aarch64.svcount") %pn, ptr %ptr) nounwind {441; CHECK-LABEL: stnt1_x2_f64:442; CHECK: // %bb.0:443; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill444; CHECK-NEXT: addvl sp, sp, #-1445; CHECK-NEXT: mov z3.d, z2.d446; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill447; CHECK-NEXT: mov p8.b, p0.b448; CHECK-NEXT: mov z2.d, z1.d449; CHECK-NEXT: stnt1d { z2.d, z3.d }, pn8, [x0]450; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload451; CHECK-NEXT: addvl sp, sp, #1452; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload453; CHECK-NEXT: ret454 call void @llvm.aarch64.sve.stnt1.pn.x2.nxv2f64(<vscale x 2 x double> %zn0, <vscale x 2 x double> %zn1, target("aarch64.svcount") %pn, ptr %ptr);455 ret void456}457 458define void @stnt1_x4_i8(<vscale x 16 x i8> %unused, <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, target("aarch64.svcount") %pn, ptr %ptr) nounwind {459; CHECK-LABEL: stnt1_x4_i8:460; CHECK: // %bb.0:461; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill462; CHECK-NEXT: addvl sp, sp, #-1463; CHECK-NEXT: mov z7.d, z4.d464; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill465; CHECK-NEXT: mov p8.b, p0.b466; CHECK-NEXT: mov z6.d, z3.d467; CHECK-NEXT: mov z5.d, z2.d468; CHECK-NEXT: mov z4.d, z1.d469; CHECK-NEXT: stnt1b { z4.b - z7.b }, pn8, [x0]470; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload471; CHECK-NEXT: addvl sp, sp, #1472; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload473; CHECK-NEXT: ret474 call void @llvm.aarch64.sve.stnt1.pn.x4.nxv16i8(<vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, target("aarch64.svcount") %pn, ptr %ptr);475 ret void476}477 478define void @stnt1_x4_i16(<vscale x 16 x i8> %unused, <vscale x 8 x i16> %zn0, <vscale x 8 x i16> %zn1, <vscale x 8 x i16> %zn2, <vscale x 8 x i16> %zn3, target("aarch64.svcount") %pn, ptr %ptr) nounwind {479; CHECK-LABEL: stnt1_x4_i16:480; CHECK: // %bb.0:481; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill482; CHECK-NEXT: addvl sp, sp, #-1483; CHECK-NEXT: mov z7.d, z4.d484; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill485; CHECK-NEXT: mov p8.b, p0.b486; CHECK-NEXT: mov z6.d, z3.d487; CHECK-NEXT: mov z5.d, z2.d488; CHECK-NEXT: mov z4.d, z1.d489; CHECK-NEXT: stnt1h { z4.h - z7.h }, pn8, [x0]490; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload491; CHECK-NEXT: addvl sp, sp, #1492; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload493; CHECK-NEXT: ret494 call void @llvm.aarch64.sve.stnt1.pn.x4.nxv8i16(<vscale x 8 x i16> %zn0, <vscale x 8 x i16> %zn1, <vscale x 8 x i16> %zn2, <vscale x 8 x i16> %zn3, target("aarch64.svcount") %pn, ptr %ptr);495 ret void496}497 498define void @stnt1_x4_i32(<vscale x 16 x i8> %unused, <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3, target("aarch64.svcount") %pn, ptr %ptr) nounwind {499; CHECK-LABEL: stnt1_x4_i32:500; CHECK: // %bb.0:501; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill502; CHECK-NEXT: addvl sp, sp, #-1503; CHECK-NEXT: mov z7.d, z4.d504; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill505; CHECK-NEXT: mov p8.b, p0.b506; CHECK-NEXT: mov z6.d, z3.d507; CHECK-NEXT: mov z5.d, z2.d508; CHECK-NEXT: mov z4.d, z1.d509; CHECK-NEXT: stnt1w { z4.s - z7.s }, pn8, [x0]510; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload511; CHECK-NEXT: addvl sp, sp, #1512; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload513; CHECK-NEXT: ret514 call void @llvm.aarch64.sve.stnt1.pn.x4.nxv4i32(<vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3, target("aarch64.svcount") %pn, ptr %ptr);515 ret void516}517 518define void @stnt1_x4_i64(<vscale x 16 x i8> %unused, <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1, <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3, target("aarch64.svcount") %pn, ptr %ptr) nounwind {519; CHECK-LABEL: stnt1_x4_i64:520; CHECK: // %bb.0:521; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill522; CHECK-NEXT: addvl sp, sp, #-1523; CHECK-NEXT: mov z7.d, z4.d524; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill525; CHECK-NEXT: mov p8.b, p0.b526; CHECK-NEXT: mov z6.d, z3.d527; CHECK-NEXT: mov z5.d, z2.d528; CHECK-NEXT: mov z4.d, z1.d529; CHECK-NEXT: stnt1d { z4.d - z7.d }, pn8, [x0]530; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload531; CHECK-NEXT: addvl sp, sp, #1532; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload533; CHECK-NEXT: ret534 call void @llvm.aarch64.sve.stnt1.pn.x4.nxv2i64(<vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1, <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3, target("aarch64.svcount") %pn, ptr %ptr);535 ret void536}537 538define void @stnt1_x4_f16(<vscale x 16 x i8> %unused, <vscale x 8 x half> %zn0, <vscale x 8 x half> %zn1, <vscale x 8 x half> %zn2, <vscale x 8 x half> %zn3, target("aarch64.svcount") %pn, ptr %ptr) nounwind {539; CHECK-LABEL: stnt1_x4_f16:540; CHECK: // %bb.0:541; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill542; CHECK-NEXT: addvl sp, sp, #-1543; CHECK-NEXT: mov z7.d, z4.d544; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill545; CHECK-NEXT: mov p8.b, p0.b546; CHECK-NEXT: mov z6.d, z3.d547; CHECK-NEXT: mov z5.d, z2.d548; CHECK-NEXT: mov z4.d, z1.d549; CHECK-NEXT: stnt1h { z4.h - z7.h }, pn8, [x0]550; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload551; CHECK-NEXT: addvl sp, sp, #1552; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload553; CHECK-NEXT: ret554 call void @llvm.aarch64.sve.stnt1.pn.x4.nxv8f16(<vscale x 8 x half> %zn0, <vscale x 8 x half> %zn1, <vscale x 8 x half> %zn2, <vscale x 8 x half> %zn3, target("aarch64.svcount") %pn, ptr %ptr);555 ret void556}557 558define void @stnt1_x4_bf16(<vscale x 16 x i8> %unused, <vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1, <vscale x 8 x bfloat> %zn2, <vscale x 8 x bfloat> %zn3, target("aarch64.svcount") %pn, ptr %ptr) nounwind {559; CHECK-LABEL: stnt1_x4_bf16:560; CHECK: // %bb.0:561; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill562; CHECK-NEXT: addvl sp, sp, #-1563; CHECK-NEXT: mov z7.d, z4.d564; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill565; CHECK-NEXT: mov p8.b, p0.b566; CHECK-NEXT: mov z6.d, z3.d567; CHECK-NEXT: mov z5.d, z2.d568; CHECK-NEXT: mov z4.d, z1.d569; CHECK-NEXT: stnt1h { z4.h - z7.h }, pn8, [x0]570; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload571; CHECK-NEXT: addvl sp, sp, #1572; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload573; CHECK-NEXT: ret574 call void @llvm.aarch64.sve.stnt1.pn.x4.nxv8bf16(<vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1, <vscale x 8 x bfloat> %zn2, <vscale x 8 x bfloat> %zn3, target("aarch64.svcount") %pn, ptr %ptr);575 ret void576}577 578define void @stnt1_x4_f32(<vscale x 16 x i8> %unused, <vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3, target("aarch64.svcount") %pn, ptr %ptr) nounwind {579; CHECK-LABEL: stnt1_x4_f32:580; CHECK: // %bb.0:581; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill582; CHECK-NEXT: addvl sp, sp, #-1583; CHECK-NEXT: mov z7.d, z4.d584; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill585; CHECK-NEXT: mov p8.b, p0.b586; CHECK-NEXT: mov z6.d, z3.d587; CHECK-NEXT: mov z5.d, z2.d588; CHECK-NEXT: mov z4.d, z1.d589; CHECK-NEXT: stnt1w { z4.s - z7.s }, pn8, [x0]590; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload591; CHECK-NEXT: addvl sp, sp, #1592; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload593; CHECK-NEXT: ret594 call void @llvm.aarch64.sve.stnt1.pn.x4.nxv4f32(<vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3, target("aarch64.svcount") %pn, ptr %ptr);595 ret void596}597 598define void @stnt1_x4_f64(<vscale x 16 x i8> %unused, <vscale x 2 x double> %zn0, <vscale x 2 x double> %zn1, <vscale x 2 x double> %zn2, <vscale x 2 x double> %zn3, target("aarch64.svcount") %pn, ptr %ptr) nounwind {599; CHECK-LABEL: stnt1_x4_f64:600; CHECK: // %bb.0:601; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill602; CHECK-NEXT: addvl sp, sp, #-1603; CHECK-NEXT: mov z7.d, z4.d604; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill605; CHECK-NEXT: mov p8.b, p0.b606; CHECK-NEXT: mov z6.d, z3.d607; CHECK-NEXT: mov z5.d, z2.d608; CHECK-NEXT: mov z4.d, z1.d609; CHECK-NEXT: stnt1d { z4.d - z7.d }, pn8, [x0]610; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload611; CHECK-NEXT: addvl sp, sp, #1612; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload613; CHECK-NEXT: ret614 call void @llvm.aarch64.sve.stnt1.pn.x4.nxv2f64(<vscale x 2 x double> %zn0, <vscale x 2 x double> %zn1, <vscale x 2 x double> %zn2, <vscale x 2 x double> %zn3, target("aarch64.svcount") %pn, ptr %ptr);615 ret void616}617 618declare void @llvm.aarch64.sve.st1.pn.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, target("aarch64.svcount"), ptr)619declare void @llvm.aarch64.sve.st1.pn.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, target("aarch64.svcount"), ptr)620declare void @llvm.aarch64.sve.st1.pn.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, target("aarch64.svcount"), ptr)621declare void @llvm.aarch64.sve.st1.pn.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, target("aarch64.svcount"), ptr)622declare void @llvm.aarch64.sve.st1.pn.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, target("aarch64.svcount"), ptr)623declare void @llvm.aarch64.sve.st1.pn.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, target("aarch64.svcount"), ptr)624declare void @llvm.aarch64.sve.st1.pn.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, target("aarch64.svcount"), ptr)625declare void @llvm.aarch64.sve.st1.pn.x2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, target("aarch64.svcount"), ptr)626declare void @llvm.aarch64.sve.stnt1.pn.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, target("aarch64.svcount"), ptr)627declare void @llvm.aarch64.sve.stnt1.pn.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, target("aarch64.svcount"), ptr)628declare void @llvm.aarch64.sve.stnt1.pn.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, target("aarch64.svcount"), ptr)629declare void @llvm.aarch64.sve.stnt1.pn.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, target("aarch64.svcount"), ptr)630declare void @llvm.aarch64.sve.stnt1.pn.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, target("aarch64.svcount"), ptr)631declare void @llvm.aarch64.sve.stnt1.pn.x2.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, target("aarch64.svcount"), ptr)632declare void @llvm.aarch64.sve.stnt1.pn.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, target("aarch64.svcount"), ptr)633declare void @llvm.aarch64.sve.stnt1.pn.x2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, target("aarch64.svcount"), ptr)634 635 636declare void @llvm.aarch64.sve.st1.pn.x4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, target("aarch64.svcount"), ptr)637declare void @llvm.aarch64.sve.st1.pn.x4.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, target("aarch64.svcount"), ptr)638declare void @llvm.aarch64.sve.st1.pn.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, target("aarch64.svcount"), ptr)639declare void @llvm.aarch64.sve.st1.pn.x4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, target("aarch64.svcount"), ptr)640declare void @llvm.aarch64.sve.st1.pn.x4.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, target("aarch64.svcount"), ptr)641declare void @llvm.aarch64.sve.st1.pn.x4.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, target("aarch64.svcount"), ptr)642declare void @llvm.aarch64.sve.st1.pn.x4.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, target("aarch64.svcount"), ptr)643declare void @llvm.aarch64.sve.st1.pn.x4.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, target("aarch64.svcount"), ptr)644declare void @llvm.aarch64.sve.stnt1.pn.x4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, target("aarch64.svcount"), ptr)645declare void @llvm.aarch64.sve.stnt1.pn.x4.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, target("aarch64.svcount"), ptr)646declare void @llvm.aarch64.sve.stnt1.pn.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, target("aarch64.svcount"), ptr)647declare void @llvm.aarch64.sve.stnt1.pn.x4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, target("aarch64.svcount"), ptr)648declare void @llvm.aarch64.sve.stnt1.pn.x4.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, target("aarch64.svcount"), ptr)649declare void @llvm.aarch64.sve.stnt1.pn.x4.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, target("aarch64.svcount"), ptr)650declare void @llvm.aarch64.sve.stnt1.pn.x4.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, target("aarch64.svcount"), ptr)651declare void @llvm.aarch64.sve.stnt1.pn.x4.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, target("aarch64.svcount"), ptr)652