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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -verify-machineinstrs -force-streaming < %s | FileCheck %s3 4; == 8 to 64-bit elements ==5 6define <vscale x 16 x i8> @uzp_x2_i8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) nounwind {7; CHECK-LABEL: uzp_x2_i8:8; CHECK: // %bb.0:9; CHECK-NEXT: uzp { z2.b, z3.b }, z0.b, z1.b10; CHECK-NEXT: add z0.b, z2.b, z0.b11; CHECK-NEXT: ret12 %uzp = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x2.nxv16i8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)13 %uzp0 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %uzp, 014 %add = add <vscale x 16 x i8> %uzp0, %zn15 ret <vscale x 16 x i8> %add16}17 18define <vscale x 8 x i16> @uzp_x2_i16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) nounwind {19; CHECK-LABEL: uzp_x2_i16:20; CHECK: // %bb.0:21; CHECK-NEXT: uzp { z2.h, z3.h }, z0.h, z1.h22; CHECK-NEXT: add z0.h, z2.h, z0.h23; CHECK-NEXT: ret24 %uzp = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uzp.x2.nxv8i16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)25 %uzp0 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %uzp, 026 %add = add <vscale x 8 x i16> %uzp0, %zn27 ret <vscale x 8 x i16> %add28}29 30define <vscale x 8 x half> @uzp_x2_f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm) nounwind {31; CHECK-LABEL: uzp_x2_f16:32; CHECK: // %bb.0:33; CHECK-NEXT: uzp { z2.h, z3.h }, z0.h, z1.h34; CHECK-NEXT: fadd z0.h, z2.h, z0.h35; CHECK-NEXT: ret36 %uzp = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.uzp.x2.nxv8f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm)37 %uzp0 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %uzp, 038 %add = fadd <vscale x 8 x half> %uzp0, %zn39 ret <vscale x 8 x half> %add40}41 42define { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @uzp_x2_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) nounwind {43; CHECK-LABEL: uzp_x2_bf16:44; CHECK: // %bb.0:45; CHECK-NEXT: uzp { z0.h, z1.h }, z0.h, z1.h46; CHECK-NEXT: ret47 %uzp = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.uzp.x2.nxv8bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm)48 ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %uzp49}50 51define <vscale x 4 x i32> @uzp_x2_i32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) nounwind {52; CHECK-LABEL: uzp_x2_i32:53; CHECK: // %bb.0:54; CHECK-NEXT: uzp { z2.s, z3.s }, z0.s, z1.s55; CHECK-NEXT: add z0.s, z2.s, z0.s56; CHECK-NEXT: ret57 %uzp = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.uzp.x2.nxv4i32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm)58 %uzp0 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %uzp, 059 %add = add <vscale x 4 x i32> %uzp0, %zn60 ret <vscale x 4 x i32> %add61}62 63define <vscale x 4 x float> @uzp_x2_f32(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm) nounwind {64; CHECK-LABEL: uzp_x2_f32:65; CHECK: // %bb.0:66; CHECK-NEXT: uzp { z2.s, z3.s }, z0.s, z1.s67; CHECK-NEXT: fadd z0.s, z2.s, z0.s68; CHECK-NEXT: ret69 %uzp = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.uzp.x2.nxv4f32(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm)70 %uzp0 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %uzp, 071 %add = fadd <vscale x 4 x float> %uzp0, %zn72 ret <vscale x 4 x float> %add73}74 75define <vscale x 2 x i64> @uzp_x2_i64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) nounwind {76; CHECK-LABEL: uzp_x2_i64:77; CHECK: // %bb.0:78; CHECK-NEXT: uzp { z2.d, z3.d }, z0.d, z1.d79; CHECK-NEXT: add z0.d, z2.d, z0.d80; CHECK-NEXT: ret81 %uzp = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.uzp.x2.nxv2i64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm)82 %uzp0 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %uzp, 083 %add = add <vscale x 2 x i64> %uzp0, %zn84 ret <vscale x 2 x i64> %add85}86 87define <vscale x 2 x double> @uzp_x2_f64(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm) nounwind {88; CHECK-LABEL: uzp_x2_f64:89; CHECK: // %bb.0:90; CHECK-NEXT: uzp { z2.d, z3.d }, z0.d, z1.d91; CHECK-NEXT: fadd z0.d, z2.d, z0.d92; CHECK-NEXT: ret93 %uzp = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.uzp.x2.nxv2f64(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm)94 %uzp0 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %uzp, 095 %add = fadd <vscale x 2 x double> %uzp0, %zn96 ret <vscale x 2 x double> %add97}98 99 100; == 128-bit elements ==101 102; NOTE: For the 128-bit case we only need to check the <vscale x 16 x i8> to103; ensure the tuple result starts at the correct register multiple. The other104; variants all test the same code path.105define <vscale x 16 x i8> @uzpq_x2_i8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) nounwind {106; CHECK-LABEL: uzpq_x2_i8:107; CHECK: // %bb.0:108; CHECK-NEXT: uzp { z2.q, z3.q }, z0.q, z1.q109; CHECK-NEXT: add z0.b, z2.b, z0.b110; CHECK-NEXT: ret111 %uzp = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzpq.x2.nxv16i8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)112 %uzp0 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %uzp, 0113 %add = add <vscale x 16 x i8> %uzp0, %zn114 ret <vscale x 16 x i8> %add115}116 117define { <vscale x 8 x i16>, <vscale x 8 x i16> } @uzpq_x2_i16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) nounwind {118; CHECK-LABEL: uzpq_x2_i16:119; CHECK: // %bb.0:120; CHECK-NEXT: uzp { z0.q, z1.q }, z0.q, z1.q121; CHECK-NEXT: ret122 %res = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uzpq.x2.nxv8i16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)123 ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %res124}125 126define { <vscale x 8 x half>, <vscale x 8 x half> } @uzpq_x2_f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm) nounwind {127; CHECK-LABEL: uzpq_x2_f16:128; CHECK: // %bb.0:129; CHECK-NEXT: uzp { z0.q, z1.q }, z0.q, z1.q130; CHECK-NEXT: ret131 %res = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.uzpq.x2.nxv8f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm)132 ret { <vscale x 8 x half>, <vscale x 8 x half> } %res133}134 135define { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @uzpq_x2_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) nounwind {136; CHECK-LABEL: uzpq_x2_bf16:137; CHECK: // %bb.0:138; CHECK-NEXT: uzp { z0.q, z1.q }, z0.q, z1.q139; CHECK-NEXT: ret140 %res = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.uzpq.x2.nxv8bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm)141 ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %res142}143 144define { <vscale x 4 x i32>, <vscale x 4 x i32> } @uzpq_x2_i32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) nounwind {145; CHECK-LABEL: uzpq_x2_i32:146; CHECK: // %bb.0:147; CHECK-NEXT: uzp { z0.q, z1.q }, z0.q, z1.q148; CHECK-NEXT: ret149 %res = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.uzpq.x2.nxv4i32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm)150 ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %res151}152 153define { <vscale x 4 x float>, <vscale x 4 x float> } @uzpq_x2_f32(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm) nounwind {154; CHECK-LABEL: uzpq_x2_f32:155; CHECK: // %bb.0:156; CHECK-NEXT: uzp { z0.q, z1.q }, z0.q, z1.q157; CHECK-NEXT: ret158 %res = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.uzpq.x2.nxv4f32(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm)159 ret { <vscale x 4 x float>, <vscale x 4 x float> } %res160}161 162define { <vscale x 2 x i64>, <vscale x 2 x i64> } @uzpq_x2_i64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) nounwind {163; CHECK-LABEL: uzpq_x2_i64:164; CHECK: // %bb.0:165; CHECK-NEXT: uzp { z0.q, z1.q }, z0.q, z1.q166; CHECK-NEXT: ret167 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.uzpq.x2.nxv2i64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm)168 ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %res169}170 171define { <vscale x 2 x double>, <vscale x 2 x double> } @uzpq_x2_f64(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm) nounwind {172; CHECK-LABEL: uzpq_x2_f64:173; CHECK: // %bb.0:174; CHECK-NEXT: uzp { z0.q, z1.q }, z0.q, z1.q175; CHECK-NEXT: ret176 %res = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.uzpq.x2.nxv2f64(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm)177 ret { <vscale x 2 x double>, <vscale x 2 x double> } %res178}179 180define { <vscale x 16 x i8>, <vscale x 16 x i8> } @uzpq_x2_i8_not_tied(<vscale x 16 x i8> %unused, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) nounwind {181; CHECK-LABEL: uzpq_x2_i8_not_tied:182; CHECK: // %bb.0:183; CHECK-NEXT: uzp { z0.q, z1.q }, z1.q, z2.q184; CHECK-NEXT: ret185 %res = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzpq.x2.nxv16i8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)186 ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %res187}188 189 190; == 8 to 64-bit elements ==191declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzp.x2.nxv16i8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)192declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uzp.x2.nxv8i16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)193declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.uzp.x2.nxv4i32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm)194declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.uzp.x2.nxv2i64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm)195declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.uzp.x2.nxv8f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm)196declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.uzp.x2.nxv8bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm)197declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.uzp.x2.nxv4f32(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm)198declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.uzp.x2.nxv2f64(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm)199 200; == 128-bit elements ==201declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.uzpq.x2.nxv16i8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)202declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.uzpq.x2.nxv8i16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)203declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.uzpq.x2.nxv4i32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm)204declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.uzpq.x2.nxv2i64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm)205declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.uzpq.x2.nxv8f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm)206declare { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.uzpq.x2.nxv8bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm)207declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.uzpq.x2.nxv4f32(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm)208declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.uzpq.x2.nxv2f64(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm)209