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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1,+bf16 < %s | FileCheck %s --check-prefixes=CHECK,SVE3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2p1,+bf16 -force-streaming < %s | FileCheck %s --check-prefixes=CHECK,SME4 5define void @dupq_i8_256b(ptr %addr) #0 {6; CHECK-LABEL: dupq_i8_256b:7; CHECK: // %bb.0:8; CHECK-NEXT: ldr z0, [x0]9; CHECK-NEXT: dupq z0.b, z0.b[15]10; CHECK-NEXT: str z0, [x0]11; CHECK-NEXT: ret12 %load = load <32 x i8>, ptr %addr13 %splat.lanes = shufflevector <32 x i8> %load, <32 x i8> poison, <32 x i32> <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15,14 i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>15 store <32 x i8> %splat.lanes, ptr %addr16 ret void17}18 19define void @dupq_i16_256b(ptr %addr) #0 {20; CHECK-LABEL: dupq_i16_256b:21; CHECK: // %bb.0:22; CHECK-NEXT: ldr z0, [x0]23; CHECK-NEXT: dupq z0.h, z0.h[2]24; CHECK-NEXT: str z0, [x0]25; CHECK-NEXT: ret26 %load = load <16 x i16>, ptr %addr27 %splat.lanes = shufflevector <16 x i16> %load, <16 x i16> poison, <16 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2,28 i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10>29 store <16 x i16> %splat.lanes, ptr %addr30 ret void31}32 33define void @dupq_i32_256b(ptr %addr) #0 {34; CHECK-LABEL: dupq_i32_256b:35; CHECK: // %bb.0:36; CHECK-NEXT: ldr z0, [x0]37; CHECK-NEXT: dupq z0.s, z0.s[3]38; CHECK-NEXT: str z0, [x0]39; CHECK-NEXT: ret40 %load = load <8 x i32>, ptr %addr41 %splat.lanes = shufflevector <8 x i32> %load, <8 x i32> poison, <8 x i32> <i32 3, i32 3, i32 3, i32 3,42 i32 7, i32 7, i32 7, i32 7>43 store <8 x i32> %splat.lanes, ptr %addr44 ret void45}46 47define void @dupq_i64_256b(ptr %addr) #0 {48; CHECK-LABEL: dupq_i64_256b:49; CHECK: // %bb.0:50; CHECK-NEXT: ldr z0, [x0]51; CHECK-NEXT: trn1 z0.d, z0.d, z0.d52; CHECK-NEXT: str z0, [x0]53; CHECK-NEXT: ret54 %load = load <4 x i64>, ptr %addr55 %splat.lanes = shufflevector <4 x i64> %load, <4 x i64> poison, <4 x i32> <i32 0, i32 0, i32 2, i32 2>56 store <4 x i64> %splat.lanes, ptr %addr57 ret void58}59 60define void @dupq_f16_256b(ptr %addr) #0 {61; CHECK-LABEL: dupq_f16_256b:62; CHECK: // %bb.0:63; CHECK-NEXT: ldr z0, [x0]64; CHECK-NEXT: dupq z0.h, z0.h[2]65; CHECK-NEXT: str z0, [x0]66; CHECK-NEXT: ret67 %load = load <16 x half>, ptr %addr68 %splat.lanes = shufflevector <16 x half> %load, <16 x half> poison, <16 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2,69 i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10>70 store <16 x half> %splat.lanes, ptr %addr71 ret void72}73 74define void @dupq_bf16_256b(ptr %addr) #0 {75; SVE-LABEL: dupq_bf16_256b:76; SVE: // %bb.0:77; SVE-NEXT: ldp q0, q1, [x0]78; SVE-NEXT: dup v0.8h, v0.h[2]79; SVE-NEXT: dup v1.8h, v1.h[2]80; SVE-NEXT: stp q0, q1, [x0]81; SVE-NEXT: ret82;83; SME-LABEL: dupq_bf16_256b:84; SME: // %bb.0:85; SME-NEXT: ldp q1, q0, [x0]86; SME-NEXT: str q0, [sp, #-64]!87; SME-NEXT: .cfi_def_cfa_offset 6488; SME-NEXT: ldr h0, [sp, #4]89; SME-NEXT: str q1, [sp, #32]90; SME-NEXT: str h0, [sp, #30]91; SME-NEXT: str h0, [sp, #28]92; SME-NEXT: str h0, [sp, #26]93; SME-NEXT: str h0, [sp, #24]94; SME-NEXT: str h0, [sp, #22]95; SME-NEXT: str h0, [sp, #20]96; SME-NEXT: str h0, [sp, #18]97; SME-NEXT: str h0, [sp, #16]98; SME-NEXT: ldr h0, [sp, #36]99; SME-NEXT: ldr q1, [sp, #16]100; SME-NEXT: str h0, [sp, #62]101; SME-NEXT: str h0, [sp, #60]102; SME-NEXT: str h0, [sp, #58]103; SME-NEXT: str h0, [sp, #56]104; SME-NEXT: str h0, [sp, #54]105; SME-NEXT: str h0, [sp, #52]106; SME-NEXT: str h0, [sp, #50]107; SME-NEXT: str h0, [sp, #48]108; SME-NEXT: ldr q0, [sp, #48]109; SME-NEXT: stp q0, q1, [x0]110; SME-NEXT: add sp, sp, #64111; SME-NEXT: ret112 %load = load <16 x bfloat>, ptr %addr113 %splat.lanes = shufflevector <16 x bfloat> %load, <16 x bfloat> poison, <16 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2,114 i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10>115 store <16 x bfloat> %splat.lanes, ptr %addr116 ret void117}118 119define void @dupq_f32_256b(ptr %addr) #0 {120; CHECK-LABEL: dupq_f32_256b:121; CHECK: // %bb.0:122; CHECK-NEXT: ldr z0, [x0]123; CHECK-NEXT: dupq z0.s, z0.s[3]124; CHECK-NEXT: str z0, [x0]125; CHECK-NEXT: ret126 %load = load <8 x float>, ptr %addr127 %splat.lanes = shufflevector <8 x float> %load, <8 x float> poison, <8 x i32> <i32 3, i32 3, i32 3, i32 3,128 i32 7, i32 7, i32 7, i32 7>129 store <8 x float> %splat.lanes, ptr %addr130 ret void131}132 133define void @dupq_f64_256b(ptr %addr) #0 {134; CHECK-LABEL: dupq_f64_256b:135; CHECK: // %bb.0:136; CHECK-NEXT: ldr z0, [x0]137; CHECK-NEXT: trn1 z0.d, z0.d, z0.d138; CHECK-NEXT: str z0, [x0]139; CHECK-NEXT: ret140 %load = load <4 x double>, ptr %addr141 %splat.lanes = shufflevector <4 x double> %load, <4 x double> poison, <4 x i32> <i32 0, i32 0, i32 2, i32 2>142 store <4 x double> %splat.lanes, ptr %addr143 ret void144}145 146define void @dupq_f32_256b_with_poison(ptr %addr) #0 {147; CHECK-LABEL: dupq_f32_256b_with_poison:148; CHECK: // %bb.0:149; CHECK-NEXT: ldr z0, [x0]150; CHECK-NEXT: dupq z0.s, z0.s[3]151; CHECK-NEXT: str z0, [x0]152; CHECK-NEXT: ret153 %load = load <8 x float>, ptr %addr154 %splat.lanes = shufflevector <8 x float> %load, <8 x float> poison, <8 x i32> <i32 3, i32 poison, i32 3, i32 3,155 i32 7, i32 7, i32 7, i32 poison>156 store <8 x float> %splat.lanes, ptr %addr157 ret void158}159 160attributes #0 = { noinline vscale_range(2,2) }161