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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple aarch64-none-linux-gnu -mattr=+fullfp16 < %s | FileCheck %s3 4define half @scvtf_f16_2(i32 %state) {5; CHECK-LABEL: scvtf_f16_2:6; CHECK: // %bb.0: // %entry7; CHECK-NEXT: scvtf h0, w0, #18; CHECK-NEXT: ret9entry:10 %conv = sitofp i32 %state to half11 %div = fmul half %conv, 5.000000e-0112 ret half %div13}14 15define half @scvtf_f16_4(i32 %state) {16; CHECK-LABEL: scvtf_f16_4:17; CHECK: // %bb.0: // %entry18; CHECK-NEXT: scvtf h0, w0, #219; CHECK-NEXT: ret20entry:21 %conv = sitofp i32 %state to half22 %div = fmul half %conv, 2.500000e-0123 ret half %div24}25 26define half @scvtf_f16_8(i32 %state) {27; CHECK-LABEL: scvtf_f16_8:28; CHECK: // %bb.0: // %entry29; CHECK-NEXT: scvtf h0, w0, #330; CHECK-NEXT: ret31entry:32 %conv = sitofp i32 %state to half33 %div = fmul half %conv, 1.250000e-0134 ret half %div35}36 37define half @scvtf_f16_16(i32 %state) {38; CHECK-LABEL: scvtf_f16_16:39; CHECK: // %bb.0: // %entry40; CHECK-NEXT: scvtf h0, w0, #441; CHECK-NEXT: ret42entry:43 %conv = sitofp i32 %state to half44 %div = fmul half %conv, 6.250000e-0245 ret half %div46}47 48define half @scvtf_f16_32(i32 %state) {49; CHECK-LABEL: scvtf_f16_32:50; CHECK: // %bb.0: // %entry51; CHECK-NEXT: scvtf h0, w0, #552; CHECK-NEXT: ret53entry:54 %conv = sitofp i32 %state to half55 %div = fmul half %conv, 3.125000e-0256 ret half %div57}58 59define float @scvtf_f32_2(i32 %state) {60; CHECK-LABEL: scvtf_f32_2:61; CHECK: // %bb.0: // %entry62; CHECK-NEXT: scvtf s0, w0, #163; CHECK-NEXT: ret64entry:65 %conv = sitofp i32 %state to float66 %div = fmul float %conv, 5.000000e-0167 ret float %div68}69 70define float @scvtf_f32_4(i32 %state) {71; CHECK-LABEL: scvtf_f32_4:72; CHECK: // %bb.0: // %entry73; CHECK-NEXT: scvtf s0, w0, #274; CHECK-NEXT: ret75entry:76 %conv = sitofp i32 %state to float77 %div = fmul float %conv, 2.500000e-0178 ret float %div79}80 81define float @scvtf_f32_8(i32 %state) {82; CHECK-LABEL: scvtf_f32_8:83; CHECK: // %bb.0: // %entry84; CHECK-NEXT: scvtf s0, w0, #385; CHECK-NEXT: ret86entry:87 %conv = sitofp i32 %state to float88 %div = fmul float %conv, 1.250000e-0189 ret float %div90}91 92define float @scvtf_f32_16(i32 %state) {93; CHECK-LABEL: scvtf_f32_16:94; CHECK: // %bb.0: // %entry95; CHECK-NEXT: scvtf s0, w0, #496; CHECK-NEXT: ret97entry:98 %conv = sitofp i32 %state to float99 %div = fmul float %conv, 6.250000e-02100 ret float %div101}102 103define float @scvtf_f32_32(i32 %state) {104; CHECK-LABEL: scvtf_f32_32:105; CHECK: // %bb.0: // %entry106; CHECK-NEXT: scvtf s0, w0, #5107; CHECK-NEXT: ret108entry:109 %conv = sitofp i32 %state to float110 %div = fmul float %conv, 3.125000e-02111 ret float %div112}113 114define double @scvtf_f64_2(i64 %state) {115; CHECK-LABEL: scvtf_f64_2:116; CHECK: // %bb.0: // %entry117; CHECK-NEXT: scvtf d0, x0, #1118; CHECK-NEXT: ret119entry:120 %conv = sitofp i64 %state to double121 %div = fmul double %conv, 5.000000e-01122 ret double %div123}124 125define double @scvtf_f64_4(i64 %state) {126; CHECK-LABEL: scvtf_f64_4:127; CHECK: // %bb.0: // %entry128; CHECK-NEXT: scvtf d0, x0, #2129; CHECK-NEXT: ret130entry:131 %conv = sitofp i64 %state to double132 %div = fmul double %conv, 2.500000e-01133 ret double %div134}135 136define double @scvtf_f64_8(i64 %state) {137; CHECK-LABEL: scvtf_f64_8:138; CHECK: // %bb.0: // %entry139; CHECK-NEXT: scvtf d0, x0, #3140; CHECK-NEXT: ret141entry:142 %conv = sitofp i64 %state to double143 %div = fmul double %conv, 1.250000e-01144 ret double %div145}146 147define double @scvtf_f64_16(i64 %state) {148; CHECK-LABEL: scvtf_f64_16:149; CHECK: // %bb.0: // %entry150; CHECK-NEXT: scvtf d0, x0, #4151; CHECK-NEXT: ret152entry:153 %conv = sitofp i64 %state to double154 %div = fmul double %conv, 6.250000e-02155 ret double %div156}157 158define double @scvtf_f64_32(i64 %state) {159; CHECK-LABEL: scvtf_f64_32:160; CHECK: // %bb.0: // %entry161; CHECK-NEXT: scvtf d0, x0, #5162; CHECK-NEXT: ret163entry:164 %conv = sitofp i64 %state to double165 %div = fmul double %conv, 3.125000e-02166 ret double %div167}168