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1; RUN: llc < %s -mtriple=arm64 | FileCheck %s2 3define i1 @testSwapCmpWithLSL64_1(i64 %a, i64 %b) {4; CHECK-LABEL: testSwapCmpWithLSL64_1:5; CHECK: cmp x1, x0, lsl #16; CHECK-NEXT: cset w0, gt7entry:8 %shl = shl i64 %a, 19 %cmp = icmp slt i64 %shl, %b10 ret i1 %cmp11}12 13define i1 @testSwapCmpWithLSL64_63(i64 %a, i64 %b) {14; CHECK-LABEL: testSwapCmpWithLSL64_63:15; CHECK: cmp x1, x0, lsl #6316; CHECK-NEXT: cset w0, gt17entry:18 %shl = shl i64 %a, 6319 %cmp = icmp slt i64 %shl, %b20 ret i1 %cmp21}22 23define i1 @testSwapCmpWithLSL32_1(i32 %a, i32 %b) {24; CHECK-LABEL: testSwapCmpWithLSL32_1:25; CHECK: cmp w1, w0, lsl #126; CHECK-NEXT: cset w0, gt27entry:28 %shl = shl i32 %a, 129 %cmp = icmp slt i32 %shl, %b30 ret i1 %cmp31}32 33define i1 @testSwapCmpWithLSL32_31(i32 %a, i32 %b) {34; CHECK-LABEL: testSwapCmpWithLSL32_31:35; CHECK: cmp w1, w0, lsl #3136; CHECK-NEXT: cset w0, gt37entry:38 %shl = shl i32 %a, 3139 %cmp = icmp slt i32 %shl, %b40 ret i1 %cmp41}42 43define i1 @testSwapCmpWithLSR64_1(i64 %a, i64 %b) {44; CHECK-LABEL: testSwapCmpWithLSR64_1:45; CHECK: cmp x1, x0, lsr #146; CHECK-NEXT: cset w0, gt47entry:48 %lshr = lshr i64 %a, 149 %cmp = icmp slt i64 %lshr, %b50 ret i1 %cmp51}52 53define i1 @testSwapCmpWithLSR64_63(i64 %a, i64 %b) {54; CHECK-LABEL: testSwapCmpWithLSR64_63:55; CHECK: cmp x1, x0, lsr #6356; CHECK-NEXT: cset w0, gt57entry:58 %lshr = lshr i64 %a, 6359 %cmp = icmp slt i64 %lshr, %b60 ret i1 %cmp61}62 63define i1 @testSwapCmpWithLSR32_1(i32 %a, i32 %b) {64; CHECK-LABEL: testSwapCmpWithLSR32_1:65; CHECK: cmp w1, w0, lsr #166; CHECK-NEXT: cset w0, gt67entry:68 %lshr = lshr i32 %a, 169 %cmp = icmp slt i32 %lshr, %b70 ret i1 %cmp71}72 73define i1 @testSwapCmpWithLSR32_31(i32 %a, i32 %b) {74; CHECK-LABEL: testSwapCmpWithLSR32_31:75; CHECK: cmp w1, w0, lsr #3176; CHECK-NEXT: cset w0, gt77entry:78 %lshr = lshr i32 %a, 3179 %cmp = icmp slt i32 %lshr, %b80 ret i1 %cmp81}82 83define i1 @testSwapCmpWithASR64_1(i64 %a, i64 %b) {84; CHECK-LABEL: testSwapCmpWithASR64_1:85; CHECK: cmp x1, x0, asr #186; CHECK-NEXT: cset w0, gt87entry:88 %ashr = ashr i64 %a, 189 %cmp = icmp slt i64 %ashr, %b90 ret i1 %cmp91}92 93define i1 @testSwapCmpWithASR64_63(i64 %a, i64 %b) {94; CHECK-LABEL: testSwapCmpWithASR64_63:95; CHECK: cmp x1, x0, asr #6396; CHECK-NEXT: cset w0, gt97entry:98 %ashr = ashr i64 %a, 6399 %cmp = icmp slt i64 %ashr, %b100 ret i1 %cmp101}102 103define i1 @testSwapCmpWithASR32_1(i32 %a, i32 %b) {104; CHECK-LABEL: testSwapCmpWithASR32_1:105; CHECK: cmp w1, w0, asr #1106; CHECK-NEXT: cset w0, gt107entry:108 %ashr = ashr i32 %a, 1109 %cmp = icmp slt i32 %ashr, %b110 ret i1 %cmp111}112 113define i1 @testSwapCmpWithASR32_31(i32 %a, i32 %b) {114; CHECK-LABEL: testSwapCmpWithASR32_31:115; CHECK: cmp w1, w0, asr #31116; CHECK-NEXT: cset w0, gt117entry:118 %ashr = ashr i32 %a, 31119 %cmp = icmp slt i32 %ashr, %b120 ret i1 %cmp121}122 123define i1 @testSwapCmpWithShiftedZeroExtend32_64(i32 %a, i64 %b) {124; CHECK-LABEL: testSwapCmpWithShiftedZeroExtend32_64125; CHECK: cmp x1, w0, uxtw #2126; CHECK-NEXT: cset w0, lo127entry:128 %a64 = zext i32 %a to i64129 %shl.0 = shl i64 %a64, 2130 %cmp = icmp ugt i64 %shl.0, %b131 ret i1 %cmp132}133 134define i1 @testSwapCmpWithShiftedZeroExtend16_64(i16 %a, i64 %b) {135; CHECK-LABEL: testSwapCmpWithShiftedZeroExtend16_64136; CHECK: cmp x1, w0, uxth #2137; CHECK-NEXT: cset w0, lo138entry:139 %a64 = zext i16 %a to i64140 %shl.0 = shl i64 %a64, 2141 %cmp = icmp ugt i64 %shl.0, %b142 ret i1 %cmp143}144 145define i1 @testSwapCmpWithShiftedZeroExtend8_64(i8 %a, i64 %b) {146; CHECK-LABEL: testSwapCmpWithShiftedZeroExtend8_64147; CHECK: cmp x1, w0, uxtb #4148; CHECK-NEXT: cset w0, lo149entry:150 %a64 = zext i8 %a to i64151 %shl.2 = shl i64 %a64, 4152 %cmp = icmp ugt i64 %shl.2, %b153 ret i1 %cmp154}155 156define i1 @testSwapCmpWithShiftedZeroExtend16_32(i16 %a, i32 %b) {157; CHECK-LABEL: testSwapCmpWithShiftedZeroExtend16_32158; CHECK: cmp w1, w0, uxth #3159; CHECK-NEXT: cset w0, lo160entry:161 %a32 = zext i16 %a to i32162 %shl = shl i32 %a32, 3163 %cmp = icmp ugt i32 %shl, %b164 ret i1 %cmp165}166 167define i1 @testSwapCmpWithShiftedZeroExtend8_32(i8 %a, i32 %b) {168; CHECK-LABEL: testSwapCmpWithShiftedZeroExtend8_32169; CHECK: cmp w1, w0, uxtb #4170; CHECK-NEXT: cset w0, lo171entry:172 %a32 = zext i8 %a to i32173 %shl = shl i32 %a32, 4174 %cmp = icmp ugt i32 %shl, %b175 ret i1 %cmp176}177 178define i1 @testSwapCmpWithTooLargeShiftedZeroExtend8_32(i8 %a, i32 %b) {179; CHECK-LABEL: testSwapCmpWithTooLargeShiftedZeroExtend8_32180; CHECK: and [[REG:w[0-9]+]], w0, #0xff181; CHECK: cmp w1, [[REG]], lsl #5182; CHECK-NEXT: cset w0, lo183entry:184 %a32 = zext i8 %a to i32185 %shl = shl i32 %a32, 5186 %cmp = icmp ugt i32 %shl, %b187 ret i1 %cmp188}189 190define i1 @testSwapCmpWithZeroExtend8_32(i8 %a, i32 %b) {191; CHECK-LABEL: testSwapCmpWithZeroExtend8_32192; CHECK: cmp w1, w0, uxtb193; CHECK-NEXT: cset w0, lo194entry:195 %a32 = zext i8 %a to i32196 %cmp = icmp ugt i32 %a32, %b197 ret i1 %cmp198}199 200define i1 @testSwapCmpWithShiftedSignExtend32_64(i32 %a, i64 %b) {201; CHECK-LABEL: testSwapCmpWithShiftedSignExtend32_64202; CHECK: cmp x1, w0, sxtw #2203; CHECK-NEXT: cset w0, lo204entry:205 %a64 = sext i32 %a to i64206 %shl.0 = shl i64 %a64, 2207 %cmp = icmp ugt i64 %shl.0, %b208 ret i1 %cmp209}210 211define i1 @testSwapCmpWithShiftedSignExtend16_64(i16 %a, i64 %b) {212; CHECK-LABEL: testSwapCmpWithShiftedSignExtend16_64213; CHECK: cmp x1, w0, sxth #2214; CHECK-NEXT: cset w0, lo215entry:216 %a64 = sext i16 %a to i64217 %shl.0 = shl i64 %a64, 2218 %cmp = icmp ugt i64 %shl.0, %b219 ret i1 %cmp220}221 222define i1 @testSwapCmpWithShiftedSignExtend8_64(i8 %a, i64 %b) {223; CHECK-LABEL: testSwapCmpWithShiftedSignExtend8_64224; CHECK: cmp x1, w0, sxtb #4225; CHECK-NEXT: cset w0, lo226entry:227 %a64 = sext i8 %a to i64228 %shl.2 = shl i64 %a64, 4229 %cmp = icmp ugt i64 %shl.2, %b230 ret i1 %cmp231}232 233define i1 @testSwapCmpWithShiftedSignExtend16_32(i16 %a, i32 %b) {234; CHECK-LABEL: testSwapCmpWithShiftedSignExtend16_32235; CHECK: cmp w1, w0, sxth #3236; CHECK-NEXT: cset w0, lo237entry:238 %a32 = sext i16 %a to i32239 %shl = shl i32 %a32, 3240 %cmp = icmp ugt i32 %shl, %b241 ret i1 %cmp242}243 244define i1 @testSwapCmpWithShiftedSignExtend8_32(i8 %a, i32 %b) {245; CHECK-LABEL: testSwapCmpWithShiftedSignExtend8_32246; CHECK: cmp w1, w0, sxtb #4247; CHECK-NEXT: cset w0, lo248entry:249 %a32 = sext i8 %a to i32250 %shl = shl i32 %a32, 4251 %cmp = icmp ugt i32 %shl, %b252 ret i1 %cmp253}254 255define i1 @testSwapCmpWithTooLargeShiftedSignExtend8_32(i8 %a, i32 %b) {256; CHECK-LABEL: testSwapCmpWithTooLargeShiftedSignExtend8_32257; CHECK: sxtb [[REG:w[0-9]+]], w0258; CHECK-NEXT: cmp w1, [[REG]], lsl #5259; CHECK-NEXT: cset w0, lo260entry:261 %a32 = sext i8 %a to i32262 %shl = shl i32 %a32, 5263 %cmp = icmp ugt i32 %shl, %b264 ret i1 %cmp265}266 267define i1 @testSwapCmpWithSignExtend8_32(i8 %a, i32 %b) {268; CHECK-LABEL: testSwapCmpWithSignExtend8_32269; CHECK: cmp w1, w0, sxtb270; CHECK-NEXT: cset w0, lo271entry:272 %a32 = sext i8 %a to i32273 %cmp = icmp ugt i32 %a32, %b274 ret i1 %cmp275}276 277define i1 @testSwapCmnWithLSL64_1(i64 %a, i64 %b) {278; CHECK-LABEL: testSwapCmnWithLSL64_1:279; CHECK: cmn x1, x0, lsl #1280; CHECK-NEXT: cset w0, ne281entry:282 %shl = shl i64 %a, 1283 %na = sub i64 0, %shl284 %cmp = icmp ne i64 %na, %b285 ret i1 %cmp286}287 288; Note: testing with a 62 bits shift as 63 has another optimization kicking in.289define i1 @testSwapCmnWithLSL64_62(i64 %a, i64 %b) {290; CHECK-LABEL: testSwapCmnWithLSL64_62:291; CHECK: cmn x1, x0, lsl #62292; CHECK-NEXT: cset w0, ne293entry:294 %shl = shl i64 %a, 62295 %na = sub i64 0, %shl296 %cmp = icmp ne i64 %na, %b297 ret i1 %cmp298}299 300; Note: the 63 bits shift triggers a different optimization path, which leads301; to a similar result in terms of performances. We try to catch here any change302; so that this test can be adapted should the optimization be done with the303; operand swap.304define i1 @testSwapCmnWithLSL64_63(i64 %a, i64 %b) {305; CHECK-LABEL: testSwapCmnWithLSL64_63:306; CHECK: cmp x1, x0, lsl #63307; CHECK-NEXT: cset w0, ne308entry:309 %shl = shl i64 %a, 63310 %na = sub i64 0, %shl311 %cmp = icmp ne i64 %na, %b312 ret i1 %cmp313}314 315define i1 @testSwapCmnWithLSL32_1(i32 %a, i32 %b) {316; CHECK-LABEL: testSwapCmnWithLSL32_1:317; CHECK: cmn w1, w0, lsl #1318; CHECK-NEXT: cset w0, ne319entry:320 %shl = shl i32 %a, 1321 %na = sub i32 0, %shl322 %cmp = icmp ne i32 %na, %b323 ret i1 %cmp324}325 326; Note: testing with a 30 bits shift as 30 has another optimization kicking in.327define i1 @testSwapCmnWithLSL32_30(i32 %a, i32 %b) {328; CHECK-LABEL: testSwapCmnWithLSL32_30:329; CHECK: cmn w1, w0, lsl #30330; CHECK-NEXT: cset w0, ne331entry:332 %shl = shl i32 %a, 30333 %na = sub i32 0, %shl334 %cmp = icmp ne i32 %na, %b335 ret i1 %cmp336}337 338; Note: the 31 bits shift triggers a different optimization path, which leads339; to a similar result in terms of performances. We try to catch here any change340; so that this test can be adapted should the optimization be done with the341; operand swap.342define i1 @testSwapCmnWithLSL32_31(i32 %a, i32 %b) {343; CHECK-LABEL: testSwapCmnWithLSL32_31:344; CHECK: cmp w1, w0, lsl #31345; CHECK-NEXT: cset w0, ne346entry:347 %shl = shl i32 %a, 31348 %na = sub i32 0, %shl349 %cmp = icmp ne i32 %na, %b350 ret i1 %cmp351}352 353define i1 @testSwapCmnWithLSR64_1(i64 %a, i64 %b) {354; CHECK-LABEL: testSwapCmnWithLSR64_1:355; CHECK: cmn x1, x0, lsr #1356; CHECK-NEXT: cset w0, ne357entry:358 %lshr = lshr i64 %a, 1359 %na = sub i64 0, %lshr360 %cmp = icmp ne i64 %na, %b361 ret i1 %cmp362}363 364; Note: testing with a 62 bits shift as 63 has another optimization kicking in.365define i1 @testSwapCmnWithLSR64_62(i64 %a, i64 %b) {366; CHECK-LABEL: testSwapCmnWithLSR64_62:367; CHECK: cmn x1, x0, lsr #62368; CHECK-NEXT: cset w0, ne369entry:370 %lshr = lshr i64 %a, 62371 %na = sub i64 0, %lshr372 %cmp = icmp ne i64 %na, %b373 ret i1 %cmp374}375 376; Note: the 63 bits shift triggers a different optimization path, which leads377; to a similar result in terms of performances. We try to catch here any change378; so that this test can be adapted should the optimization be done with the379; operand swap.380define i1 @testSwapCmnWithLSR64_63(i64 %a, i64 %b) {381; CHECK-LABEL: testSwapCmnWithLSR64_63:382; CHECK: cmp x1, x0, asr #63383; CHECK-NEXT: cset w0, ne384entry:385 %lshr = lshr i64 %a, 63386 %na = sub i64 0, %lshr387 %cmp = icmp ne i64 %na, %b388 ret i1 %cmp389}390 391define i1 @testSwapCmnWithLSR32_1(i32 %a, i32 %b) {392; CHECK-LABEL: testSwapCmnWithLSR32_1:393; CHECK: cmn w1, w0, lsr #1394; CHECK-NEXT: cset w0, ne395entry:396 %lshr = lshr i32 %a, 1397 %na = sub i32 0, %lshr398 %cmp = icmp ne i32 %na, %b399 ret i1 %cmp400}401 402; Note: testing with a 30 bits shift as 31 has another optimization kicking in.403define i1 @testSwapCmnWithLSR32_30(i32 %a, i32 %b) {404; CHECK-LABEL: testSwapCmnWithLSR32_30:405; CHECK: cmn w1, w0, lsr #30406; CHECK-NEXT: cset w0, ne407entry:408 %lshr = lshr i32 %a, 30409 %na = sub i32 0, %lshr410 %cmp = icmp ne i32 %na, %b411 ret i1 %cmp412}413 414; Note: the 31 bits shift triggers a different optimization path, which leads415; to a similar result in terms of performances. We try to catch here any change416; so that this test can be adapted should the optimization be done with the417; operand swap.418define i1 @testSwapCmnWithLSR32_31(i32 %a, i32 %b) {419; CHECK-LABEL: testSwapCmnWithLSR32_31:420; CHECK: cmp w1, w0, asr #31421; CHECK-NEXT: cset w0, ne422entry:423 %lshr = lshr i32 %a, 31424 %na = sub i32 0, %lshr425 %cmp = icmp ne i32 %na, %b426 ret i1 %cmp427}428 429define i1 @testSwapCmnWithASR64_1(i64 %a, i64 %b) {430; CHECK-LABEL: testSwapCmnWithASR64_1:431; CHECK: cmn x1, x0, asr #3432; CHECK-NEXT: cset w0, ne433entry:434 %lshr = ashr i64 %a, 3435 %na = sub i64 0, %lshr436 %cmp = icmp ne i64 %na, %b437 ret i1 %cmp438}439 440; Note: testing with a 62 bits shift as 63 has another optimization kicking in.441define i1 @testSwapCmnWithASR64_62(i64 %a, i64 %b) {442; CHECK-LABEL: testSwapCmnWithASR64_62:443; CHECK: cmn x1, x0, asr #62444; CHECK-NEXT: cset w0, ne445entry:446 %lshr = ashr i64 %a, 62447 %na = sub i64 0, %lshr448 %cmp = icmp ne i64 %na, %b449 ret i1 %cmp450}451 452; Note: the 63 bits shift triggers a different optimization path, which leads453; to a similar result in terms of performances. We try to catch here any change454; so that this test can be adapted should the optimization be done with the455; operand swap.456define i1 @testSwapCmnWithASR64_63(i64 %a, i64 %b) {457; CHECK-LABEL: testSwapCmnWithASR64_63:458; CHECK: cmp x1, x0, lsr #63459; CHECK-NEXT: cset w0, ne460entry:461 %lshr = ashr i64 %a, 63462 %na = sub i64 0, %lshr463 %cmp = icmp ne i64 %na, %b464 ret i1 %cmp465}466 467define i1 @testSwapCmnWithASR32_1(i32 %a, i32 %b) {468; CHECK-LABEL: testSwapCmnWithASR32_1:469; CHECK: cmn w1, w0, asr #1470; CHECK-NEXT: cset w0, eq471entry:472 %lshr = ashr i32 %a, 1473 %na = sub i32 0, %lshr474 %cmp = icmp eq i32 %na, %b475 ret i1 %cmp476}477 478; Note: testing with a 30 bits shift as 31 has another optimization kicking in.479define i1 @testSwapCmnWithASR32_30(i32 %a, i32 %b) {480; CHECK-LABEL: testSwapCmnWithASR32_30:481; CHECK: cmn w1, w0, asr #30482; CHECK-NEXT: cset w0, ne483entry:484 %lshr = ashr i32 %a, 30485 %na = sub i32 0, %lshr486 %cmp = icmp ne i32 %na, %b487 ret i1 %cmp488}489 490; Note: the 31 bits shift triggers a different optimization path, which leads491; to a similar result in terms of performances. We try to catch here any change492; so that this test can be adapted should the optimization be done with the493; operand swap.494define i1 @testSwapCmnWithASR32_31(i32 %a, i32 %b) {495; CHECK-LABEL: testSwapCmnWithASR32_31:496; CHECK: cmp w1, w0, lsr #31497; CHECK-NEXT: cset w0, ne498entry:499 %lshr = ashr i32 %a, 31500 %na = sub i32 0, %lshr501 %cmp = icmp ne i32 %na, %b502 ret i1 %cmp503}504 505define i64 @testSwapCmpToCmnWithZeroExtend(i32 %a32, i16 %a16, i8 %a8, i64 %b64, i32 %b32) {506; CHECK-LABEL: testSwapCmpToCmnWithZeroExtend:507t0:508 %conv0 = zext i32 %a32 to i64509 %shl0 = shl i64 %conv0, 1510 %na0 = sub i64 0, %shl0511 %cmp0 = icmp ne i64 %na0, %b64512; CHECK: cmn x3, w0, uxtw #1513 br i1 %cmp0, label %t1, label %end514 515t1:516 %conv1 = zext i16 %a16 to i64517 %shl1 = shl i64 %conv1, 4518 %na1 = sub i64 0, %shl1519 %cmp1 = icmp ne i64 %na1, %b64520; CHECK: cmn x3, w1, uxth #4521 br i1 %cmp1, label %t2, label %end522 523t2:524 %conv2 = zext i8 %a8 to i64525 %shl2 = shl i64 %conv2, 3526 %na2 = sub i64 0, %shl2527 %cmp2 = icmp ne i64 %na2, %b64528; CHECK: cmn x3, w2, uxtb #3529 br i1 %cmp2, label %t3, label %end530 531t3:532 %conv3 = zext i16 %a16 to i32533 %shl3 = shl i32 %conv3, 2534 %na3 = sub i32 0, %shl3535 %cmp3 = icmp ne i32 %na3, %b32536; CHECK: cmn w4, w1, uxth #2537 br i1 %cmp3, label %t4, label %end538 539t4:540 %conv4 = zext i8 %a8 to i32541 %shl4 = shl i32 %conv4, 1542 %na4 = sub i32 0, %shl4543 %cmp4 = icmp ne i32 %na4, %b32544; CHECK: cmn w4, w2, uxtb #1545 br i1 %cmp4, label %t5, label %end546 547t5:548 %conv5 = zext i8 %a8 to i32549 %shl5 = shl i32 %conv5, 5550 %na5 = sub i32 0, %shl5551 %cmp5 = icmp ne i32 %na5, %b32552; CHECK: and [[REG:w[0-9]+]], w2, #0xff553; CHECK: cmn w4, [[REG]], lsl #5554 br i1 %cmp5, label %t6, label %end555 556t6:557 %conv6 = zext i8 %a8 to i32558 %na6 = sub i32 0, %conv6559 %cmp6 = icmp ne i32 %na6, %b32560; CHECK: cmn w4, w2, uxtb561 br i1 %cmp6, label %t7, label %end562 563t7:564 ret i64 0565 566end:567 ret i64 1568}569define i64 @testSwapCmpToCmnWithSignExtend(i32 %a32, i16 %a16, i8 %a8, i64 %b64, i32 %b32) {570; CHECK-LABEL: testSwapCmpToCmnWithSignExtend:571t0:572 %conv0 = sext i32 %a32 to i64573 %shl0 = shl i64 %conv0, 1574 %na0 = sub i64 0, %shl0575 %cmp0 = icmp ne i64 %na0, %b64576; CHECK: cmn x3, w0, sxtw #1577 br i1 %cmp0, label %t1, label %end578 579t1:580 %conv1 = sext i16 %a16 to i64581 %shl1 = shl i64 %conv1, 4582 %na1 = sub i64 0, %shl1583 %cmp1 = icmp ne i64 %na1, %b64584; CHECK: cmn x3, w1, sxth #4585 br i1 %cmp1, label %t2, label %end586 587t2:588 %conv2 = sext i8 %a8 to i64589 %shl2 = shl i64 %conv2, 3590 %na2 = sub i64 0, %shl2591 %cmp2 = icmp ne i64 %na2, %b64592; CHECK: cmn x3, w2, sxtb #3593 br i1 %cmp2, label %t3, label %end594 595t3:596 %conv3 = sext i16 %a16 to i32597 %shl3 = shl i32 %conv3, 2598 %na3 = sub i32 0, %shl3599 %cmp3 = icmp ne i32 %na3, %b32600; CHECK: cmn w4, w1, sxth #2601 br i1 %cmp3, label %t4, label %end602 603t4:604 %conv4 = sext i8 %a8 to i32605 %shl4 = shl i32 %conv4, 1606 %na4 = sub i32 0, %shl4607 %cmp4 = icmp ne i32 %na4, %b32608; CHECK: cmn w4, w2, sxtb #1609 br i1 %cmp4, label %t5, label %end610 611t5:612 %conv5 = sext i8 %a8 to i32613 %shl5 = shl i32 %conv5, 5614 %na5 = sub i32 0, %shl5615 %cmp5 = icmp ne i32 %na5, %b32616; CHECK: sxtb [[REG:w[0-9]+]], w2617; CHECK: cmn w4, [[REG]], lsl #5618 br i1 %cmp5, label %t6, label %end619 620t6:621 %conv6 = sext i8 %a8 to i32622 %na6 = sub i32 0, %conv6623 %cmp6 = icmp ne i32 %na6, %b32624; CHECK: cmn w4, w2, sxtb625 br i1 %cmp6, label %t7, label %end626 627t7:628 ret i64 0629 630end:631 ret i64 1632}633