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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s3 4; We've got the usual issues with LLVM reordering blocks here. The5; tests are correct for the current order, but who knows when that6; will change. Beware!7@var32 = global i32 08@var64 = global i64 09 10define i32 @test_tbz() {11; CHECK-LABEL: test_tbz:12; CHECK: ; %bb.0:13; CHECK-NEXT: Lloh0:14; CHECK-NEXT: adrp x8, _var32@PAGE15; CHECK-NEXT: Lloh1:16; CHECK-NEXT: ldr w8, [x8, _var32@PAGEOFF]17; CHECK-NEXT: tbz w8, #15, LBB0_518; CHECK-NEXT: ; %bb.1: ; %test119; CHECK-NEXT: tbz w8, #12, LBB0_520; CHECK-NEXT: ; %bb.2: ; %test221; CHECK-NEXT: Lloh2:22; CHECK-NEXT: adrp x8, _var64@PAGE23; CHECK-NEXT: Lloh3:24; CHECK-NEXT: ldr x8, [x8, _var64@PAGEOFF]25; CHECK-NEXT: tbz w8, #15, LBB0_526; CHECK-NEXT: ; %bb.3: ; %test327; CHECK-NEXT: tbz w8, #12, LBB0_528; CHECK-NEXT: ; %bb.4: ; %end229; CHECK-NEXT: mov w0, #130; CHECK-NEXT: ret31; CHECK-NEXT: LBB0_5: ; %end132; CHECK-NEXT: mov w0, wzr33; CHECK-NEXT: ret34; CHECK-NEXT: .loh AdrpLdr Lloh0, Lloh135; CHECK-NEXT: .loh AdrpLdr Lloh2, Lloh336 37 %val = load i32, ptr @var3238 %val64 = load i64, ptr @var6439 40 %tbit0 = and i32 %val, 3276841 %tst0 = icmp ne i32 %tbit0, 042 br i1 %tst0, label %test1, label %end143 44test1:45 %tbit1 = and i32 %val, 409646 %tst1 = icmp ne i32 %tbit1, 047 br i1 %tst1, label %test2, label %end148 49test2:50 %tbit2 = and i64 %val64, 3276851 %tst2 = icmp ne i64 %tbit2, 052 br i1 %tst2, label %test3, label %end153 54test3:55 %tbit3 = and i64 %val64, 409656 %tst3 = icmp ne i64 %tbit3, 057 br i1 %tst3, label %end2, label %end158 59end2:60 ret i32 161 62end1:63 ret i32 064}65