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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc < %s -mtriple=aarch64-- -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5declare i4 @llvm.uadd.sat.i4(i4, i4)6declare i8 @llvm.uadd.sat.i8(i8, i8)7declare i16 @llvm.uadd.sat.i16(i16, i16)8declare i32 @llvm.uadd.sat.i32(i32, i32)9declare i64 @llvm.uadd.sat.i64(i64, i64)10 11define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {12; CHECK-SD-LABEL: func32:13; CHECK-SD: // %bb.0:14; CHECK-SD-NEXT: mul w8, w1, w215; CHECK-SD-NEXT: adds w8, w0, w816; CHECK-SD-NEXT: csinv w0, w8, wzr, lo17; CHECK-SD-NEXT: ret18;19; CHECK-GI-LABEL: func32:20; CHECK-GI: // %bb.0:21; CHECK-GI-NEXT: mul w8, w1, w222; CHECK-GI-NEXT: adds w8, w0, w823; CHECK-GI-NEXT: cset w9, hs24; CHECK-GI-NEXT: tst w9, #0x125; CHECK-GI-NEXT: csinv w0, w8, wzr, eq26; CHECK-GI-NEXT: ret27 %a = mul i32 %y, %z28 %tmp = call i32 @llvm.uadd.sat.i32(i32 %x, i32 %a)29 ret i32 %tmp30}31 32define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {33; CHECK-SD-LABEL: func64:34; CHECK-SD: // %bb.0:35; CHECK-SD-NEXT: adds x8, x0, x236; CHECK-SD-NEXT: csinv x0, x8, xzr, lo37; CHECK-SD-NEXT: ret38;39; CHECK-GI-LABEL: func64:40; CHECK-GI: // %bb.0:41; CHECK-GI-NEXT: adds x8, x0, x242; CHECK-GI-NEXT: cset w9, hs43; CHECK-GI-NEXT: tst w9, #0x144; CHECK-GI-NEXT: csinv x0, x8, xzr, eq45; CHECK-GI-NEXT: ret46 %a = mul i64 %y, %z47 %tmp = call i64 @llvm.uadd.sat.i64(i64 %x, i64 %z)48 ret i64 %tmp49}50 51define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {52; CHECK-SD-LABEL: func16:53; CHECK-SD: // %bb.0:54; CHECK-SD-NEXT: mul w8, w1, w255; CHECK-SD-NEXT: and w9, w0, #0xffff56; CHECK-SD-NEXT: add w8, w9, w8, uxth57; CHECK-SD-NEXT: mov w9, #65535 // =0xffff58; CHECK-SD-NEXT: cmp w8, w959; CHECK-SD-NEXT: csel w0, w8, w9, lo60; CHECK-SD-NEXT: ret61;62; CHECK-GI-LABEL: func16:63; CHECK-GI: // %bb.0:64; CHECK-GI-NEXT: mul w8, w1, w265; CHECK-GI-NEXT: and w8, w8, #0xffff66; CHECK-GI-NEXT: add w8, w8, w0, uxth67; CHECK-GI-NEXT: cmp w8, w8, uxth68; CHECK-GI-NEXT: csinv w0, w8, wzr, eq69; CHECK-GI-NEXT: ret70 %a = mul i16 %y, %z71 %tmp = call i16 @llvm.uadd.sat.i16(i16 %x, i16 %a)72 ret i16 %tmp73}74 75define i8 @func8(i8 %x, i8 %y, i8 %z) nounwind {76; CHECK-SD-LABEL: func8:77; CHECK-SD: // %bb.0:78; CHECK-SD-NEXT: mul w8, w1, w279; CHECK-SD-NEXT: and w9, w0, #0xff80; CHECK-SD-NEXT: add w8, w9, w8, uxtb81; CHECK-SD-NEXT: mov w9, #255 // =0xff82; CHECK-SD-NEXT: cmp w8, #25583; CHECK-SD-NEXT: csel w0, w8, w9, lo84; CHECK-SD-NEXT: ret85;86; CHECK-GI-LABEL: func8:87; CHECK-GI: // %bb.0:88; CHECK-GI-NEXT: mul w8, w1, w289; CHECK-GI-NEXT: and w8, w8, #0xff90; CHECK-GI-NEXT: add w8, w8, w0, uxtb91; CHECK-GI-NEXT: cmp w8, w8, uxtb92; CHECK-GI-NEXT: csinv w0, w8, wzr, eq93; CHECK-GI-NEXT: ret94 %a = mul i8 %y, %z95 %tmp = call i8 @llvm.uadd.sat.i8(i8 %x, i8 %a)96 ret i8 %tmp97}98 99define i4 @func4(i4 %x, i4 %y, i4 %z) nounwind {100; CHECK-SD-LABEL: func4:101; CHECK-SD: // %bb.0:102; CHECK-SD-NEXT: mul w8, w1, w2103; CHECK-SD-NEXT: and w9, w0, #0xf104; CHECK-SD-NEXT: and w8, w8, #0xf105; CHECK-SD-NEXT: add w8, w9, w8106; CHECK-SD-NEXT: mov w9, #15 // =0xf107; CHECK-SD-NEXT: cmp w8, #15108; CHECK-SD-NEXT: csel w0, w8, w9, lo109; CHECK-SD-NEXT: ret110;111; CHECK-GI-LABEL: func4:112; CHECK-GI: // %bb.0:113; CHECK-GI-NEXT: mul w8, w1, w2114; CHECK-GI-NEXT: and w9, w0, #0xf115; CHECK-GI-NEXT: mov w10, #15 // =0xf116; CHECK-GI-NEXT: and w8, w8, #0xf117; CHECK-GI-NEXT: add w8, w9, w8118; CHECK-GI-NEXT: and w9, w8, #0xf119; CHECK-GI-NEXT: cmp w8, w9120; CHECK-GI-NEXT: csel w0, w10, w8, ne121; CHECK-GI-NEXT: ret122 %a = mul i4 %y, %z123 %tmp = call i4 @llvm.uadd.sat.i4(i4 %x, i4 %a)124 ret i4 %tmp125}126;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:127; CHECK: {{.*}}128