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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc < %s -mtriple=aarch64-- -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5; CHECK-GI: warning: Instruction selection used fallback path for v16i46; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v16i17 8define <16 x i8> @v16i8(<16 x i8> %x, <16 x i8> %y) nounwind {9; CHECK-LABEL: v16i8:10; CHECK: // %bb.0:11; CHECK-NEXT: uqadd v0.16b, v0.16b, v1.16b12; CHECK-NEXT: ret13 %z = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y)14 ret <16 x i8> %z15}16 17define <32 x i8> @v32i8(<32 x i8> %x, <32 x i8> %y) nounwind {18; CHECK-SD-LABEL: v32i8:19; CHECK-SD: // %bb.0:20; CHECK-SD-NEXT: uqadd v1.16b, v1.16b, v3.16b21; CHECK-SD-NEXT: uqadd v0.16b, v0.16b, v2.16b22; CHECK-SD-NEXT: ret23;24; CHECK-GI-LABEL: v32i8:25; CHECK-GI: // %bb.0:26; CHECK-GI-NEXT: uqadd v0.16b, v0.16b, v2.16b27; CHECK-GI-NEXT: uqadd v1.16b, v1.16b, v3.16b28; CHECK-GI-NEXT: ret29 %z = call <32 x i8> @llvm.uadd.sat.v32i8(<32 x i8> %x, <32 x i8> %y)30 ret <32 x i8> %z31}32 33define <64 x i8> @v64i8(<64 x i8> %x, <64 x i8> %y) nounwind {34; CHECK-SD-LABEL: v64i8:35; CHECK-SD: // %bb.0:36; CHECK-SD-NEXT: uqadd v2.16b, v2.16b, v6.16b37; CHECK-SD-NEXT: uqadd v0.16b, v0.16b, v4.16b38; CHECK-SD-NEXT: uqadd v1.16b, v1.16b, v5.16b39; CHECK-SD-NEXT: uqadd v3.16b, v3.16b, v7.16b40; CHECK-SD-NEXT: ret41;42; CHECK-GI-LABEL: v64i8:43; CHECK-GI: // %bb.0:44; CHECK-GI-NEXT: uqadd v0.16b, v0.16b, v4.16b45; CHECK-GI-NEXT: uqadd v1.16b, v1.16b, v5.16b46; CHECK-GI-NEXT: uqadd v2.16b, v2.16b, v6.16b47; CHECK-GI-NEXT: uqadd v3.16b, v3.16b, v7.16b48; CHECK-GI-NEXT: ret49 %z = call <64 x i8> @llvm.uadd.sat.v64i8(<64 x i8> %x, <64 x i8> %y)50 ret <64 x i8> %z51}52 53define <8 x i16> @v8i16(<8 x i16> %x, <8 x i16> %y) nounwind {54; CHECK-LABEL: v8i16:55; CHECK: // %bb.0:56; CHECK-NEXT: uqadd v0.8h, v0.8h, v1.8h57; CHECK-NEXT: ret58 %z = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y)59 ret <8 x i16> %z60}61 62define <16 x i16> @v16i16(<16 x i16> %x, <16 x i16> %y) nounwind {63; CHECK-SD-LABEL: v16i16:64; CHECK-SD: // %bb.0:65; CHECK-SD-NEXT: uqadd v1.8h, v1.8h, v3.8h66; CHECK-SD-NEXT: uqadd v0.8h, v0.8h, v2.8h67; CHECK-SD-NEXT: ret68;69; CHECK-GI-LABEL: v16i16:70; CHECK-GI: // %bb.0:71; CHECK-GI-NEXT: uqadd v0.8h, v0.8h, v2.8h72; CHECK-GI-NEXT: uqadd v1.8h, v1.8h, v3.8h73; CHECK-GI-NEXT: ret74 %z = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> %x, <16 x i16> %y)75 ret <16 x i16> %z76}77 78define <32 x i16> @v32i16(<32 x i16> %x, <32 x i16> %y) nounwind {79; CHECK-SD-LABEL: v32i16:80; CHECK-SD: // %bb.0:81; CHECK-SD-NEXT: uqadd v2.8h, v2.8h, v6.8h82; CHECK-SD-NEXT: uqadd v0.8h, v0.8h, v4.8h83; CHECK-SD-NEXT: uqadd v1.8h, v1.8h, v5.8h84; CHECK-SD-NEXT: uqadd v3.8h, v3.8h, v7.8h85; CHECK-SD-NEXT: ret86;87; CHECK-GI-LABEL: v32i16:88; CHECK-GI: // %bb.0:89; CHECK-GI-NEXT: uqadd v0.8h, v0.8h, v4.8h90; CHECK-GI-NEXT: uqadd v1.8h, v1.8h, v5.8h91; CHECK-GI-NEXT: uqadd v2.8h, v2.8h, v6.8h92; CHECK-GI-NEXT: uqadd v3.8h, v3.8h, v7.8h93; CHECK-GI-NEXT: ret94 %z = call <32 x i16> @llvm.uadd.sat.v32i16(<32 x i16> %x, <32 x i16> %y)95 ret <32 x i16> %z96}97 98define void @v8i8(ptr %px, ptr %py, ptr %pz) nounwind {99; CHECK-LABEL: v8i8:100; CHECK: // %bb.0:101; CHECK-NEXT: ldr d0, [x0]102; CHECK-NEXT: ldr d1, [x1]103; CHECK-NEXT: uqadd v0.8b, v0.8b, v1.8b104; CHECK-NEXT: str d0, [x2]105; CHECK-NEXT: ret106 %x = load <8 x i8>, ptr %px107 %y = load <8 x i8>, ptr %py108 %z = call <8 x i8> @llvm.uadd.sat.v8i8(<8 x i8> %x, <8 x i8> %y)109 store <8 x i8> %z, ptr %pz110 ret void111}112 113define void @v4i8(ptr %px, ptr %py, ptr %pz) nounwind {114; CHECK-SD-LABEL: v4i8:115; CHECK-SD: // %bb.0:116; CHECK-SD-NEXT: ldr s0, [x0]117; CHECK-SD-NEXT: ldr s1, [x1]118; CHECK-SD-NEXT: movi d2, #0xff00ff00ff00ff119; CHECK-SD-NEXT: uaddl v0.8h, v0.8b, v1.8b120; CHECK-SD-NEXT: umin v0.4h, v0.4h, v2.4h121; CHECK-SD-NEXT: uzp1 v0.8b, v0.8b, v0.8b122; CHECK-SD-NEXT: str s0, [x2]123; CHECK-SD-NEXT: ret124;125; CHECK-GI-LABEL: v4i8:126; CHECK-GI: // %bb.0:127; CHECK-GI-NEXT: ldr w8, [x0]128; CHECK-GI-NEXT: ldr w9, [x1]129; CHECK-GI-NEXT: fmov s0, w8130; CHECK-GI-NEXT: fmov s1, w9131; CHECK-GI-NEXT: mov b2, v0.b[1]132; CHECK-GI-NEXT: mov v3.b[0], v0.b[0]133; CHECK-GI-NEXT: mov b4, v1.b[1]134; CHECK-GI-NEXT: mov v5.b[0], v1.b[0]135; CHECK-GI-NEXT: mov v3.b[1], v2.b[0]136; CHECK-GI-NEXT: mov b2, v0.b[2]137; CHECK-GI-NEXT: mov b0, v0.b[3]138; CHECK-GI-NEXT: mov v5.b[1], v4.b[0]139; CHECK-GI-NEXT: mov b4, v1.b[2]140; CHECK-GI-NEXT: mov b1, v1.b[3]141; CHECK-GI-NEXT: mov v3.b[2], v2.b[0]142; CHECK-GI-NEXT: mov v5.b[2], v4.b[0]143; CHECK-GI-NEXT: mov v3.b[3], v0.b[0]144; CHECK-GI-NEXT: mov v5.b[3], v1.b[0]145; CHECK-GI-NEXT: uqadd v0.8b, v3.8b, v5.8b146; CHECK-GI-NEXT: fmov w8, s0147; CHECK-GI-NEXT: str w8, [x2]148; CHECK-GI-NEXT: ret149 %x = load <4 x i8>, ptr %px150 %y = load <4 x i8>, ptr %py151 %z = call <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8> %x, <4 x i8> %y)152 store <4 x i8> %z, ptr %pz153 ret void154}155 156define void @v2i8(ptr %px, ptr %py, ptr %pz) nounwind {157; CHECK-SD-LABEL: v2i8:158; CHECK-SD: // %bb.0:159; CHECK-SD-NEXT: ldr h0, [x0]160; CHECK-SD-NEXT: ldr h1, [x1]161; CHECK-SD-NEXT: movi d2, #0x0000ff000000ff162; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0163; CHECK-SD-NEXT: ushll v1.8h, v1.8b, #0164; CHECK-SD-NEXT: uaddl v0.4s, v0.4h, v1.4h165; CHECK-SD-NEXT: umin v0.2s, v0.2s, v2.2s166; CHECK-SD-NEXT: mov s1, v0.s[1]167; CHECK-SD-NEXT: str b0, [x2]168; CHECK-SD-NEXT: stur b1, [x2, #1]169; CHECK-SD-NEXT: ret170;171; CHECK-GI-LABEL: v2i8:172; CHECK-GI: // %bb.0:173; CHECK-GI-NEXT: ldr b0, [x0]174; CHECK-GI-NEXT: ldr b1, [x1]175; CHECK-GI-NEXT: add x8, x0, #1176; CHECK-GI-NEXT: add x9, x1, #1177; CHECK-GI-NEXT: ld1 { v0.b }[1], [x8]178; CHECK-GI-NEXT: ld1 { v1.b }[1], [x9]179; CHECK-GI-NEXT: add x8, x2, #1180; CHECK-GI-NEXT: uqadd v0.8b, v0.8b, v1.8b181; CHECK-GI-NEXT: st1 { v0.b }[0], [x2]182; CHECK-GI-NEXT: st1 { v0.b }[1], [x8]183; CHECK-GI-NEXT: ret184 %x = load <2 x i8>, ptr %px185 %y = load <2 x i8>, ptr %py186 %z = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %x, <2 x i8> %y)187 store <2 x i8> %z, ptr %pz188 ret void189}190 191define void @v4i16(ptr %px, ptr %py, ptr %pz) nounwind {192; CHECK-LABEL: v4i16:193; CHECK: // %bb.0:194; CHECK-NEXT: ldr d0, [x0]195; CHECK-NEXT: ldr d1, [x1]196; CHECK-NEXT: uqadd v0.4h, v0.4h, v1.4h197; CHECK-NEXT: str d0, [x2]198; CHECK-NEXT: ret199 %x = load <4 x i16>, ptr %px200 %y = load <4 x i16>, ptr %py201 %z = call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> %x, <4 x i16> %y)202 store <4 x i16> %z, ptr %pz203 ret void204}205 206define void @v2i16(ptr %px, ptr %py, ptr %pz) nounwind {207; CHECK-SD-LABEL: v2i16:208; CHECK-SD: // %bb.0:209; CHECK-SD-NEXT: ldr s0, [x0]210; CHECK-SD-NEXT: ldr s1, [x1]211; CHECK-SD-NEXT: movi d2, #0x00ffff0000ffff212; CHECK-SD-NEXT: uaddl v0.4s, v0.4h, v1.4h213; CHECK-SD-NEXT: umin v0.2s, v0.2s, v2.2s214; CHECK-SD-NEXT: mov s1, v0.s[1]215; CHECK-SD-NEXT: str h0, [x2]216; CHECK-SD-NEXT: str h1, [x2, #2]217; CHECK-SD-NEXT: ret218;219; CHECK-GI-LABEL: v2i16:220; CHECK-GI: // %bb.0:221; CHECK-GI-NEXT: ldr h0, [x0]222; CHECK-GI-NEXT: ldr h1, [x1]223; CHECK-GI-NEXT: add x8, x0, #2224; CHECK-GI-NEXT: add x9, x1, #2225; CHECK-GI-NEXT: ld1 { v0.h }[1], [x8]226; CHECK-GI-NEXT: ld1 { v1.h }[1], [x9]227; CHECK-GI-NEXT: add x8, x2, #2228; CHECK-GI-NEXT: uqadd v0.4h, v0.4h, v1.4h229; CHECK-GI-NEXT: str h0, [x2]230; CHECK-GI-NEXT: st1 { v0.h }[1], [x8]231; CHECK-GI-NEXT: ret232 %x = load <2 x i16>, ptr %px233 %y = load <2 x i16>, ptr %py234 %z = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %x, <2 x i16> %y)235 store <2 x i16> %z, ptr %pz236 ret void237}238 239define <12 x i8> @v12i8(<12 x i8> %x, <12 x i8> %y) nounwind {240; CHECK-LABEL: v12i8:241; CHECK: // %bb.0:242; CHECK-NEXT: uqadd v0.16b, v0.16b, v1.16b243; CHECK-NEXT: ret244 %z = call <12 x i8> @llvm.uadd.sat.v12i8(<12 x i8> %x, <12 x i8> %y)245 ret <12 x i8> %z246}247 248define void @v12i16(ptr %px, ptr %py, ptr %pz) nounwind {249; CHECK-SD-LABEL: v12i16:250; CHECK-SD: // %bb.0:251; CHECK-SD-NEXT: ldp q0, q3, [x1]252; CHECK-SD-NEXT: ldp q1, q2, [x0]253; CHECK-SD-NEXT: uqadd v0.8h, v1.8h, v0.8h254; CHECK-SD-NEXT: uqadd v1.8h, v2.8h, v3.8h255; CHECK-SD-NEXT: str q0, [x2]256; CHECK-SD-NEXT: str d1, [x2, #16]257; CHECK-SD-NEXT: ret258;259; CHECK-GI-LABEL: v12i16:260; CHECK-GI: // %bb.0:261; CHECK-GI-NEXT: ldr q0, [x0]262; CHECK-GI-NEXT: ldr q1, [x1]263; CHECK-GI-NEXT: ldr d2, [x0, #16]264; CHECK-GI-NEXT: ldr d3, [x1, #16]265; CHECK-GI-NEXT: uqadd v0.8h, v0.8h, v1.8h266; CHECK-GI-NEXT: uqadd v1.4h, v2.4h, v3.4h267; CHECK-GI-NEXT: str q0, [x2]268; CHECK-GI-NEXT: str d1, [x2, #16]269; CHECK-GI-NEXT: ret270 %x = load <12 x i16>, ptr %px271 %y = load <12 x i16>, ptr %py272 %z = call <12 x i16> @llvm.uadd.sat.v12i16(<12 x i16> %x, <12 x i16> %y)273 store <12 x i16> %z, ptr %pz274 ret void275}276 277define void @v1i8(ptr %px, ptr %py, ptr %pz) nounwind {278; CHECK-SD-LABEL: v1i8:279; CHECK-SD: // %bb.0:280; CHECK-SD-NEXT: ldr b0, [x0]281; CHECK-SD-NEXT: ldr b1, [x1]282; CHECK-SD-NEXT: uqadd v0.8b, v0.8b, v1.8b283; CHECK-SD-NEXT: str b0, [x2]284; CHECK-SD-NEXT: ret285;286; CHECK-GI-LABEL: v1i8:287; CHECK-GI: // %bb.0:288; CHECK-GI-NEXT: ldrb w8, [x0]289; CHECK-GI-NEXT: ldrb w9, [x1]290; CHECK-GI-NEXT: add w8, w8, w9291; CHECK-GI-NEXT: cmp w8, w8, uxtb292; CHECK-GI-NEXT: csinv w8, w8, wzr, eq293; CHECK-GI-NEXT: strb w8, [x2]294; CHECK-GI-NEXT: ret295 %x = load <1 x i8>, ptr %px296 %y = load <1 x i8>, ptr %py297 %z = call <1 x i8> @llvm.uadd.sat.v1i8(<1 x i8> %x, <1 x i8> %y)298 store <1 x i8> %z, ptr %pz299 ret void300}301 302define void @v1i16(ptr %px, ptr %py, ptr %pz) nounwind {303; CHECK-SD-LABEL: v1i16:304; CHECK-SD: // %bb.0:305; CHECK-SD-NEXT: ldr h0, [x0]306; CHECK-SD-NEXT: ldr h1, [x1]307; CHECK-SD-NEXT: uqadd v0.4h, v0.4h, v1.4h308; CHECK-SD-NEXT: str h0, [x2]309; CHECK-SD-NEXT: ret310;311; CHECK-GI-LABEL: v1i16:312; CHECK-GI: // %bb.0:313; CHECK-GI-NEXT: ldrh w8, [x0]314; CHECK-GI-NEXT: ldrh w9, [x1]315; CHECK-GI-NEXT: add w8, w8, w9316; CHECK-GI-NEXT: cmp w8, w8, uxth317; CHECK-GI-NEXT: csinv w8, w8, wzr, eq318; CHECK-GI-NEXT: strh w8, [x2]319; CHECK-GI-NEXT: ret320 %x = load <1 x i16>, ptr %px321 %y = load <1 x i16>, ptr %py322 %z = call <1 x i16> @llvm.uadd.sat.v1i16(<1 x i16> %x, <1 x i16> %y)323 store <1 x i16> %z, ptr %pz324 ret void325}326 327define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind {328; CHECK-LABEL: v16i4:329; CHECK: // %bb.0:330; CHECK-NEXT: movi v2.16b, #15331; CHECK-NEXT: and v1.16b, v1.16b, v2.16b332; CHECK-NEXT: and v0.16b, v0.16b, v2.16b333; CHECK-NEXT: add v0.16b, v0.16b, v1.16b334; CHECK-NEXT: umin v0.16b, v0.16b, v2.16b335; CHECK-NEXT: ret336 %z = call <16 x i4> @llvm.uadd.sat.v16i4(<16 x i4> %x, <16 x i4> %y)337 ret <16 x i4> %z338}339 340define <16 x i1> @v16i1(<16 x i1> %x, <16 x i1> %y) nounwind {341; CHECK-LABEL: v16i1:342; CHECK: // %bb.0:343; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b344; CHECK-NEXT: ret345 %z = call <16 x i1> @llvm.uadd.sat.v16i1(<16 x i1> %x, <16 x i1> %y)346 ret <16 x i1> %z347}348 349define void @v1i32(ptr %px, ptr %py, ptr %pz) nounwind {350; CHECK-SD-LABEL: v1i32:351; CHECK-SD: // %bb.0:352; CHECK-SD-NEXT: ldr s0, [x0]353; CHECK-SD-NEXT: ldr s1, [x1]354; CHECK-SD-NEXT: uqadd v0.2s, v0.2s, v1.2s355; CHECK-SD-NEXT: str s0, [x2]356; CHECK-SD-NEXT: ret357;358; CHECK-GI-LABEL: v1i32:359; CHECK-GI: // %bb.0:360; CHECK-GI-NEXT: ldr w8, [x0]361; CHECK-GI-NEXT: ldr w9, [x1]362; CHECK-GI-NEXT: adds w8, w8, w9363; CHECK-GI-NEXT: cset w9, hs364; CHECK-GI-NEXT: tst w9, #0x1365; CHECK-GI-NEXT: csinv w8, w8, wzr, eq366; CHECK-GI-NEXT: str w8, [x2]367; CHECK-GI-NEXT: ret368 %x = load <1 x i32>, ptr %px369 %y = load <1 x i32>, ptr %py370 %z = call <1 x i32> @llvm.uadd.sat.v1i32(<1 x i32> %x, <1 x i32> %y)371 store <1 x i32> %z, ptr %pz372 ret void373}374 375define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind {376; CHECK-LABEL: v2i32:377; CHECK: // %bb.0:378; CHECK-NEXT: uqadd v0.2s, v0.2s, v1.2s379; CHECK-NEXT: ret380 %z = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %x, <2 x i32> %y)381 ret <2 x i32> %z382}383 384define <4 x i32> @v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {385; CHECK-LABEL: v4i32:386; CHECK: // %bb.0:387; CHECK-NEXT: uqadd v0.4s, v0.4s, v1.4s388; CHECK-NEXT: ret389 %z = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y)390 ret <4 x i32> %z391}392 393define <8 x i32> @v8i32(<8 x i32> %x, <8 x i32> %y) nounwind {394; CHECK-SD-LABEL: v8i32:395; CHECK-SD: // %bb.0:396; CHECK-SD-NEXT: uqadd v1.4s, v1.4s, v3.4s397; CHECK-SD-NEXT: uqadd v0.4s, v0.4s, v2.4s398; CHECK-SD-NEXT: ret399;400; CHECK-GI-LABEL: v8i32:401; CHECK-GI: // %bb.0:402; CHECK-GI-NEXT: uqadd v0.4s, v0.4s, v2.4s403; CHECK-GI-NEXT: uqadd v1.4s, v1.4s, v3.4s404; CHECK-GI-NEXT: ret405 %z = call <8 x i32> @llvm.uadd.sat.v8i32(<8 x i32> %x, <8 x i32> %y)406 ret <8 x i32> %z407}408 409define <16 x i32> @v16i32(<16 x i32> %x, <16 x i32> %y) nounwind {410; CHECK-SD-LABEL: v16i32:411; CHECK-SD: // %bb.0:412; CHECK-SD-NEXT: uqadd v2.4s, v2.4s, v6.4s413; CHECK-SD-NEXT: uqadd v0.4s, v0.4s, v4.4s414; CHECK-SD-NEXT: uqadd v1.4s, v1.4s, v5.4s415; CHECK-SD-NEXT: uqadd v3.4s, v3.4s, v7.4s416; CHECK-SD-NEXT: ret417;418; CHECK-GI-LABEL: v16i32:419; CHECK-GI: // %bb.0:420; CHECK-GI-NEXT: uqadd v0.4s, v0.4s, v4.4s421; CHECK-GI-NEXT: uqadd v1.4s, v1.4s, v5.4s422; CHECK-GI-NEXT: uqadd v2.4s, v2.4s, v6.4s423; CHECK-GI-NEXT: uqadd v3.4s, v3.4s, v7.4s424; CHECK-GI-NEXT: ret425 %z = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %x, <16 x i32> %y)426 ret <16 x i32> %z427}428 429define void @v1i64(ptr %px, ptr %py, ptr %pz) nounwind {430; CHECK-SD-LABEL: v1i64:431; CHECK-SD: // %bb.0:432; CHECK-SD-NEXT: ldr d0, [x0]433; CHECK-SD-NEXT: ldr d1, [x1]434; CHECK-SD-NEXT: uqadd d0, d0, d1435; CHECK-SD-NEXT: str d0, [x2]436; CHECK-SD-NEXT: ret437;438; CHECK-GI-LABEL: v1i64:439; CHECK-GI: // %bb.0:440; CHECK-GI-NEXT: ldr x8, [x0]441; CHECK-GI-NEXT: ldr x9, [x1]442; CHECK-GI-NEXT: adds x8, x8, x9443; CHECK-GI-NEXT: cset w9, hs444; CHECK-GI-NEXT: tst w9, #0x1445; CHECK-GI-NEXT: csinv x8, x8, xzr, eq446; CHECK-GI-NEXT: str x8, [x2]447; CHECK-GI-NEXT: ret448 %x = load <1 x i64>, ptr %px449 %y = load <1 x i64>, ptr %py450 %z = call <1 x i64> @llvm.uadd.sat.v1i64(<1 x i64> %x, <1 x i64> %y)451 store <1 x i64> %z, ptr %pz452 ret void453}454 455define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {456; CHECK-LABEL: v2i64:457; CHECK: // %bb.0:458; CHECK-NEXT: uqadd v0.2d, v0.2d, v1.2d459; CHECK-NEXT: ret460 %z = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> %x, <2 x i64> %y)461 ret <2 x i64> %z462}463 464define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind {465; CHECK-SD-LABEL: v4i64:466; CHECK-SD: // %bb.0:467; CHECK-SD-NEXT: uqadd v1.2d, v1.2d, v3.2d468; CHECK-SD-NEXT: uqadd v0.2d, v0.2d, v2.2d469; CHECK-SD-NEXT: ret470;471; CHECK-GI-LABEL: v4i64:472; CHECK-GI: // %bb.0:473; CHECK-GI-NEXT: uqadd v0.2d, v0.2d, v2.2d474; CHECK-GI-NEXT: uqadd v1.2d, v1.2d, v3.2d475; CHECK-GI-NEXT: ret476 %z = call <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64> %x, <4 x i64> %y)477 ret <4 x i64> %z478}479 480define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind {481; CHECK-SD-LABEL: v8i64:482; CHECK-SD: // %bb.0:483; CHECK-SD-NEXT: uqadd v2.2d, v2.2d, v6.2d484; CHECK-SD-NEXT: uqadd v0.2d, v0.2d, v4.2d485; CHECK-SD-NEXT: uqadd v1.2d, v1.2d, v5.2d486; CHECK-SD-NEXT: uqadd v3.2d, v3.2d, v7.2d487; CHECK-SD-NEXT: ret488;489; CHECK-GI-LABEL: v8i64:490; CHECK-GI: // %bb.0:491; CHECK-GI-NEXT: uqadd v0.2d, v0.2d, v4.2d492; CHECK-GI-NEXT: uqadd v1.2d, v1.2d, v5.2d493; CHECK-GI-NEXT: uqadd v2.2d, v2.2d, v6.2d494; CHECK-GI-NEXT: uqadd v3.2d, v3.2d, v7.2d495; CHECK-GI-NEXT: ret496 %z = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> %x, <8 x i64> %y)497 ret <8 x i64> %z498}499 500define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {501; CHECK-SD-LABEL: v2i128:502; CHECK-SD: // %bb.0:503; CHECK-SD-NEXT: adds x8, x0, x4504; CHECK-SD-NEXT: adcs x9, x1, x5505; CHECK-SD-NEXT: csinv x0, x8, xzr, lo506; CHECK-SD-NEXT: csinv x1, x9, xzr, lo507; CHECK-SD-NEXT: adds x8, x2, x6508; CHECK-SD-NEXT: adcs x9, x3, x7509; CHECK-SD-NEXT: csinv x2, x8, xzr, lo510; CHECK-SD-NEXT: csinv x3, x9, xzr, lo511; CHECK-SD-NEXT: ret512;513; CHECK-GI-LABEL: v2i128:514; CHECK-GI: // %bb.0:515; CHECK-GI-NEXT: adds x8, x0, x4516; CHECK-GI-NEXT: adcs x9, x1, x5517; CHECK-GI-NEXT: cset w10, hs518; CHECK-GI-NEXT: tst w10, #0x1519; CHECK-GI-NEXT: csinv x0, x8, xzr, eq520; CHECK-GI-NEXT: csinv x1, x9, xzr, eq521; CHECK-GI-NEXT: adds x8, x2, x6522; CHECK-GI-NEXT: adcs x9, x3, x7523; CHECK-GI-NEXT: cset w10, hs524; CHECK-GI-NEXT: tst w10, #0x1525; CHECK-GI-NEXT: csinv x2, x8, xzr, eq526; CHECK-GI-NEXT: csinv x3, x9, xzr, eq527; CHECK-GI-NEXT: ret528 %z = call <2 x i128> @llvm.uadd.sat.v2i128(<2 x i128> %x, <2 x i128> %y)529 ret <2 x i128> %z530}531