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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s3 4; https://bugs.llvm.org/show_bug.cgi?id=371045 6; All the advanced stuff (negative tests, commutativity) is handled in the7; scalar version of the test only.8 9; ============================================================================ ;10; 8-bit vector width11; ============================================================================ ;12 13define <1 x i8> @out_v1i8(<1 x i8> %x, <1 x i8> %y, <1 x i8> %mask) nounwind {14; CHECK-LABEL: out_v1i8:15; CHECK: // %bb.0:16; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b17; CHECK-NEXT: ret18 %mx = and <1 x i8> %x, %mask19 %notmask = xor <1 x i8> %mask, <i8 -1>20 %my = and <1 x i8> %y, %notmask21 %r = or <1 x i8> %mx, %my22 ret <1 x i8> %r23}24 25; ============================================================================ ;26; 16-bit vector width27; ============================================================================ ;28 29define <2 x i8> @out_v2i8(<2 x i8> %x, <2 x i8> %y, <2 x i8> %mask) nounwind {30; CHECK-LABEL: out_v2i8:31; CHECK: // %bb.0:32; CHECK-NEXT: movi d3, #0x0000ff000000ff33; CHECK-NEXT: and v0.8b, v0.8b, v2.8b34; CHECK-NEXT: eor v3.8b, v2.8b, v3.8b35; CHECK-NEXT: and v1.8b, v1.8b, v3.8b36; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b37; CHECK-NEXT: ret38 %mx = and <2 x i8> %x, %mask39 %notmask = xor <2 x i8> %mask, <i8 -1, i8 -1>40 %my = and <2 x i8> %y, %notmask41 %r = or <2 x i8> %mx, %my42 ret <2 x i8> %r43}44 45define <1 x i16> @out_v1i16(<1 x i16> %x, <1 x i16> %y, <1 x i16> %mask) nounwind {46; CHECK-LABEL: out_v1i16:47; CHECK: // %bb.0:48; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b49; CHECK-NEXT: ret50 %mx = and <1 x i16> %x, %mask51 %notmask = xor <1 x i16> %mask, <i16 -1>52 %my = and <1 x i16> %y, %notmask53 %r = or <1 x i16> %mx, %my54 ret <1 x i16> %r55}56 57; ============================================================================ ;58; 32-bit vector width59; ============================================================================ ;60 61define <4 x i8> @out_v4i8(<4 x i8> %x, <4 x i8> %y, <4 x i8> %mask) nounwind {62; CHECK-LABEL: out_v4i8:63; CHECK: // %bb.0:64; CHECK-NEXT: movi d3, #0xff00ff00ff00ff65; CHECK-NEXT: and v0.8b, v0.8b, v2.8b66; CHECK-NEXT: eor v3.8b, v2.8b, v3.8b67; CHECK-NEXT: and v1.8b, v1.8b, v3.8b68; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b69; CHECK-NEXT: ret70 %mx = and <4 x i8> %x, %mask71 %notmask = xor <4 x i8> %mask, <i8 -1, i8 -1, i8 -1, i8 -1>72 %my = and <4 x i8> %y, %notmask73 %r = or <4 x i8> %mx, %my74 ret <4 x i8> %r75}76 77define <4 x i8> @out_v4i8_undef(<4 x i8> %x, <4 x i8> %y, <4 x i8> %mask) nounwind {78; CHECK-LABEL: out_v4i8_undef:79; CHECK: // %bb.0:80; CHECK-NEXT: movi d3, #0xff00ff00ff00ff81; CHECK-NEXT: and v0.8b, v0.8b, v2.8b82; CHECK-NEXT: eor v3.8b, v2.8b, v3.8b83; CHECK-NEXT: and v1.8b, v1.8b, v3.8b84; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b85; CHECK-NEXT: ret86 %mx = and <4 x i8> %x, %mask87 %notmask = xor <4 x i8> %mask, <i8 -1, i8 -1, i8 undef, i8 -1>88 %my = and <4 x i8> %y, %notmask89 %r = or <4 x i8> %mx, %my90 ret <4 x i8> %r91}92 93define <2 x i16> @out_v2i16(<2 x i16> %x, <2 x i16> %y, <2 x i16> %mask) nounwind {94; CHECK-LABEL: out_v2i16:95; CHECK: // %bb.0:96; CHECK-NEXT: movi d3, #0x00ffff0000ffff97; CHECK-NEXT: and v0.8b, v0.8b, v2.8b98; CHECK-NEXT: eor v3.8b, v2.8b, v3.8b99; CHECK-NEXT: and v1.8b, v1.8b, v3.8b100; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b101; CHECK-NEXT: ret102 %mx = and <2 x i16> %x, %mask103 %notmask = xor <2 x i16> %mask, <i16 -1, i16 -1>104 %my = and <2 x i16> %y, %notmask105 %r = or <2 x i16> %mx, %my106 ret <2 x i16> %r107}108 109define <1 x i32> @out_v1i32(<1 x i32> %x, <1 x i32> %y, <1 x i32> %mask) nounwind {110; CHECK-LABEL: out_v1i32:111; CHECK: // %bb.0:112; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b113; CHECK-NEXT: ret114 %mx = and <1 x i32> %x, %mask115 %notmask = xor <1 x i32> %mask, <i32 -1>116 %my = and <1 x i32> %y, %notmask117 %r = or <1 x i32> %mx, %my118 ret <1 x i32> %r119}120 121; ============================================================================ ;122; 64-bit vector width123; ============================================================================ ;124 125define <8 x i8> @out_v8i8(<8 x i8> %x, <8 x i8> %y, <8 x i8> %mask) nounwind {126; CHECK-LABEL: out_v8i8:127; CHECK: // %bb.0:128; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b129; CHECK-NEXT: ret130 %mx = and <8 x i8> %x, %mask131 %notmask = xor <8 x i8> %mask, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>132 %my = and <8 x i8> %y, %notmask133 %r = or <8 x i8> %mx, %my134 ret <8 x i8> %r135}136 137define <4 x i16> @out_v4i16(<4 x i16> %x, <4 x i16> %y, <4 x i16> %mask) nounwind {138; CHECK-LABEL: out_v4i16:139; CHECK: // %bb.0:140; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b141; CHECK-NEXT: ret142 %mx = and <4 x i16> %x, %mask143 %notmask = xor <4 x i16> %mask, <i16 -1, i16 -1, i16 -1, i16 -1>144 %my = and <4 x i16> %y, %notmask145 %r = or <4 x i16> %mx, %my146 ret <4 x i16> %r147}148 149define <4 x i16> @out_v4i16_undef(<4 x i16> %x, <4 x i16> %y, <4 x i16> %mask) nounwind {150; CHECK-LABEL: out_v4i16_undef:151; CHECK: // %bb.0:152; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b153; CHECK-NEXT: ret154 %mx = and <4 x i16> %x, %mask155 %notmask = xor <4 x i16> %mask, <i16 -1, i16 -1, i16 undef, i16 -1>156 %my = and <4 x i16> %y, %notmask157 %r = or <4 x i16> %mx, %my158 ret <4 x i16> %r159}160 161define <2 x i32> @out_v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %mask) nounwind {162; CHECK-LABEL: out_v2i32:163; CHECK: // %bb.0:164; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b165; CHECK-NEXT: ret166 %mx = and <2 x i32> %x, %mask167 %notmask = xor <2 x i32> %mask, <i32 -1, i32 -1>168 %my = and <2 x i32> %y, %notmask169 %r = or <2 x i32> %mx, %my170 ret <2 x i32> %r171}172 173define <1 x i64> @out_v1i64(<1 x i64> %x, <1 x i64> %y, <1 x i64> %mask) nounwind {174; CHECK-LABEL: out_v1i64:175; CHECK: // %bb.0:176; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b177; CHECK-NEXT: ret178 %mx = and <1 x i64> %x, %mask179 %notmask = xor <1 x i64> %mask, <i64 -1>180 %my = and <1 x i64> %y, %notmask181 %r = or <1 x i64> %mx, %my182 ret <1 x i64> %r183}184 185; ============================================================================ ;186; 128-bit vector width187; ============================================================================ ;188 189define <16 x i8> @out_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %mask) nounwind {190; CHECK-LABEL: out_v16i8:191; CHECK: // %bb.0:192; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b193; CHECK-NEXT: ret194 %mx = and <16 x i8> %x, %mask195 %notmask = xor <16 x i8> %mask, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>196 %my = and <16 x i8> %y, %notmask197 %r = or <16 x i8> %mx, %my198 ret <16 x i8> %r199}200 201define <8 x i16> @out_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %mask) nounwind {202; CHECK-LABEL: out_v8i16:203; CHECK: // %bb.0:204; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b205; CHECK-NEXT: ret206 %mx = and <8 x i16> %x, %mask207 %notmask = xor <8 x i16> %mask, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>208 %my = and <8 x i16> %y, %notmask209 %r = or <8 x i16> %mx, %my210 ret <8 x i16> %r211}212 213define <4 x i32> @out_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) nounwind {214; CHECK-LABEL: out_v4i32:215; CHECK: // %bb.0:216; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b217; CHECK-NEXT: ret218 %mx = and <4 x i32> %x, %mask219 %notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>220 %my = and <4 x i32> %y, %notmask221 %r = or <4 x i32> %mx, %my222 ret <4 x i32> %r223}224 225define <4 x i32> @out_v4i32_undef(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) nounwind {226; CHECK-LABEL: out_v4i32_undef:227; CHECK: // %bb.0:228; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b229; CHECK-NEXT: ret230 %mx = and <4 x i32> %x, %mask231 %notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 undef, i32 -1>232 %my = and <4 x i32> %y, %notmask233 %r = or <4 x i32> %mx, %my234 ret <4 x i32> %r235}236 237define <2 x i64> @out_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %mask) nounwind {238; CHECK-LABEL: out_v2i64:239; CHECK: // %bb.0:240; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b241; CHECK-NEXT: ret242 %mx = and <2 x i64> %x, %mask243 %notmask = xor <2 x i64> %mask, <i64 -1, i64 -1>244 %my = and <2 x i64> %y, %notmask245 %r = or <2 x i64> %mx, %my246 ret <2 x i64> %r247}248 249;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;250; Should be the same as the previous one.251;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;252 253; ============================================================================ ;254; 8-bit vector width255; ============================================================================ ;256 257define <1 x i8> @in_v1i8(<1 x i8> %x, <1 x i8> %y, <1 x i8> %mask) nounwind {258; CHECK-LABEL: in_v1i8:259; CHECK: // %bb.0:260; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b261; CHECK-NEXT: ret262 %n0 = xor <1 x i8> %x, %y263 %n1 = and <1 x i8> %n0, %mask264 %r = xor <1 x i8> %n1, %y265 ret <1 x i8> %r266}267 268; ============================================================================ ;269; 16-bit vector width270; ============================================================================ ;271 272define <2 x i8> @in_v2i8(<2 x i8> %x, <2 x i8> %y, <2 x i8> %mask) nounwind {273; CHECK-LABEL: in_v2i8:274; CHECK: // %bb.0:275; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b276; CHECK-NEXT: ret277 %n0 = xor <2 x i8> %x, %y278 %n1 = and <2 x i8> %n0, %mask279 %r = xor <2 x i8> %n1, %y280 ret <2 x i8> %r281}282 283define <1 x i16> @in_v1i16(<1 x i16> %x, <1 x i16> %y, <1 x i16> %mask) nounwind {284; CHECK-LABEL: in_v1i16:285; CHECK: // %bb.0:286; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b287; CHECK-NEXT: ret288 %n0 = xor <1 x i16> %x, %y289 %n1 = and <1 x i16> %n0, %mask290 %r = xor <1 x i16> %n1, %y291 ret <1 x i16> %r292}293 294; ============================================================================ ;295; 32-bit vector width296; ============================================================================ ;297 298define <4 x i8> @in_v4i8(<4 x i8> %x, <4 x i8> %y, <4 x i8> %mask) nounwind {299; CHECK-LABEL: in_v4i8:300; CHECK: // %bb.0:301; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b302; CHECK-NEXT: ret303 %n0 = xor <4 x i8> %x, %y304 %n1 = and <4 x i8> %n0, %mask305 %r = xor <4 x i8> %n1, %y306 ret <4 x i8> %r307}308 309define <2 x i16> @in_v2i16(<2 x i16> %x, <2 x i16> %y, <2 x i16> %mask) nounwind {310; CHECK-LABEL: in_v2i16:311; CHECK: // %bb.0:312; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b313; CHECK-NEXT: ret314 %n0 = xor <2 x i16> %x, %y315 %n1 = and <2 x i16> %n0, %mask316 %r = xor <2 x i16> %n1, %y317 ret <2 x i16> %r318}319 320define <1 x i32> @in_v1i32(<1 x i32> %x, <1 x i32> %y, <1 x i32> %mask) nounwind {321; CHECK-LABEL: in_v1i32:322; CHECK: // %bb.0:323; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b324; CHECK-NEXT: ret325 %n0 = xor <1 x i32> %x, %y326 %n1 = and <1 x i32> %n0, %mask327 %r = xor <1 x i32> %n1, %y328 ret <1 x i32> %r329}330 331; ============================================================================ ;332; 64-bit vector width333; ============================================================================ ;334 335define <8 x i8> @in_v8i8(<8 x i8> %x, <8 x i8> %y, <8 x i8> %mask) nounwind {336; CHECK-LABEL: in_v8i8:337; CHECK: // %bb.0:338; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b339; CHECK-NEXT: ret340 %n0 = xor <8 x i8> %x, %y341 %n1 = and <8 x i8> %n0, %mask342 %r = xor <8 x i8> %n1, %y343 ret <8 x i8> %r344}345 346define <4 x i16> @in_v4i16(<4 x i16> %x, <4 x i16> %y, <4 x i16> %mask) nounwind {347; CHECK-LABEL: in_v4i16:348; CHECK: // %bb.0:349; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b350; CHECK-NEXT: ret351 %n0 = xor <4 x i16> %x, %y352 %n1 = and <4 x i16> %n0, %mask353 %r = xor <4 x i16> %n1, %y354 ret <4 x i16> %r355}356 357define <2 x i32> @in_v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %mask) nounwind {358; CHECK-LABEL: in_v2i32:359; CHECK: // %bb.0:360; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b361; CHECK-NEXT: ret362 %n0 = xor <2 x i32> %x, %y363 %n1 = and <2 x i32> %n0, %mask364 %r = xor <2 x i32> %n1, %y365 ret <2 x i32> %r366}367 368define <1 x i64> @in_v1i64(<1 x i64> %x, <1 x i64> %y, <1 x i64> %mask) nounwind {369; CHECK-LABEL: in_v1i64:370; CHECK: // %bb.0:371; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b372; CHECK-NEXT: ret373 %n0 = xor <1 x i64> %x, %y374 %n1 = and <1 x i64> %n0, %mask375 %r = xor <1 x i64> %n1, %y376 ret <1 x i64> %r377}378 379; ============================================================================ ;380; 128-bit vector width381; ============================================================================ ;382 383define <16 x i8> @in_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %mask) nounwind {384; CHECK-LABEL: in_v16i8:385; CHECK: // %bb.0:386; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b387; CHECK-NEXT: ret388 %n0 = xor <16 x i8> %x, %y389 %n1 = and <16 x i8> %n0, %mask390 %r = xor <16 x i8> %n1, %y391 ret <16 x i8> %r392}393 394define <8 x i16> @in_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %mask) nounwind {395; CHECK-LABEL: in_v8i16:396; CHECK: // %bb.0:397; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b398; CHECK-NEXT: ret399 %n0 = xor <8 x i16> %x, %y400 %n1 = and <8 x i16> %n0, %mask401 %r = xor <8 x i16> %n1, %y402 ret <8 x i16> %r403}404 405define <4 x i32> @in_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) nounwind {406; CHECK-LABEL: in_v4i32:407; CHECK: // %bb.0:408; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b409; CHECK-NEXT: ret410 %n0 = xor <4 x i32> %x, %y411 %n1 = and <4 x i32> %n0, %mask412 %r = xor <4 x i32> %n1, %y413 ret <4 x i32> %r414}415 416define <2 x i64> @in_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %mask) nounwind {417; CHECK-LABEL: in_v2i64:418; CHECK: // %bb.0:419; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b420; CHECK-NEXT: ret421 %n0 = xor <2 x i64> %x, %y422 %n1 = and <2 x i64> %n0, %mask423 %r = xor <2 x i64> %n1, %y424 ret <2 x i64> %r425}426