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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s3 4define <4 x i1> @t32_3(<4 x i32> %X) nounwind {5; CHECK-LABEL: t32_3:6; CHECK: // %bb.0:7; CHECK-NEXT: adrp x8, .LCPI0_08; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI0_0]9; CHECK-NEXT: mov w8, #43691 // =0xaaab10; CHECK-NEXT: movk w8, #43690, lsl #1611; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s12; CHECK-NEXT: dup v1.4s, w813; CHECK-NEXT: adrp x8, .LCPI0_114; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s15; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI0_1]16; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s17; CHECK-NEXT: xtn v0.4h, v0.4s18; CHECK-NEXT: ret19 %urem = urem <4 x i32> %X, <i32 3, i32 3, i32 3, i32 3>20 %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 1, i32 2, i32 2>21 ret <4 x i1> %cmp22}23 24define <4 x i1> @t32_5(<4 x i32> %X) nounwind {25; CHECK-LABEL: t32_5:26; CHECK: // %bb.0:27; CHECK-NEXT: adrp x8, .LCPI1_028; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI1_0]29; CHECK-NEXT: mov w8, #52429 // =0xcccd30; CHECK-NEXT: movk w8, #52428, lsl #1631; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s32; CHECK-NEXT: dup v1.4s, w833; CHECK-NEXT: mov w8, #13106 // =0x333234; CHECK-NEXT: movk w8, #13107, lsl #1635; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s36; CHECK-NEXT: dup v1.4s, w837; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s38; CHECK-NEXT: xtn v0.4h, v0.4s39; CHECK-NEXT: ret40 %urem = urem <4 x i32> %X, <i32 5, i32 5, i32 5, i32 5>41 %cmp = icmp eq <4 x i32> %urem, <i32 1, i32 2, i32 3, i32 4>42 ret <4 x i1> %cmp43}44 45define <4 x i1> @t32_6_part0(<4 x i32> %X) nounwind {46; CHECK-LABEL: t32_6_part0:47; CHECK: // %bb.0:48; CHECK-NEXT: adrp x8, .LCPI2_049; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI2_0]50; CHECK-NEXT: mov w8, #43691 // =0xaaab51; CHECK-NEXT: movk w8, #43690, lsl #1652; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s53; CHECK-NEXT: dup v1.4s, w854; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s55; CHECK-NEXT: movi v1.16b, #17056; CHECK-NEXT: shl v2.4s, v0.4s, #3157; CHECK-NEXT: fneg v1.4s, v1.4s58; CHECK-NEXT: usra v2.4s, v0.4s, #159; CHECK-NEXT: cmhs v0.4s, v1.4s, v2.4s60; CHECK-NEXT: xtn v0.4h, v0.4s61; CHECK-NEXT: ret62 %urem = urem <4 x i32> %X, <i32 6, i32 6, i32 6, i32 6>63 %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 1, i32 2, i32 3>64 ret <4 x i1> %cmp65}66 67define <4 x i1> @t32_6_part1(<4 x i32> %X) nounwind {68; CHECK-LABEL: t32_6_part1:69; CHECK: // %bb.0:70; CHECK-NEXT: adrp x8, .LCPI3_071; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI3_0]72; CHECK-NEXT: mov w8, #43691 // =0xaaab73; CHECK-NEXT: movk w8, #43690, lsl #1674; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s75; CHECK-NEXT: dup v1.4s, w876; CHECK-NEXT: adrp x8, .LCPI3_177; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s78; CHECK-NEXT: shl v1.4s, v0.4s, #3179; CHECK-NEXT: usra v1.4s, v0.4s, #180; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI3_1]81; CHECK-NEXT: cmhs v0.4s, v0.4s, v1.4s82; CHECK-NEXT: xtn v0.4h, v0.4s83; CHECK-NEXT: ret84 %urem = urem <4 x i32> %X, <i32 6, i32 6, i32 6, i32 6>85 %cmp = icmp eq <4 x i32> %urem, <i32 4, i32 5, i32 0, i32 0>86 ret <4 x i1> %cmp87}88 89define <4 x i1> @t32_tautological(<4 x i32> %X) nounwind {90; CHECK-LABEL: t32_tautological:91; CHECK: // %bb.0:92; CHECK-NEXT: adrp x8, .LCPI4_093; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI4_0]94; CHECK-NEXT: mov w8, #43691 // =0xaaab95; CHECK-NEXT: movk w8, #43690, lsl #1696; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s97; CHECK-NEXT: dup v1.4s, w898; CHECK-NEXT: adrp x8, .LCPI4_199; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s100; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI4_1]101; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s102; CHECK-NEXT: movi d1, #0x00ffffffff0000103; CHECK-NEXT: xtn v0.4h, v0.4s104; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b105; CHECK-NEXT: ret106 %urem = urem <4 x i32> %X, <i32 1, i32 1, i32 2, i32 3>107 %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 1, i32 2, i32 2>108 ret <4 x i1> %cmp109}110