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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s3 4define <4 x i1> @t0_all_tautological(<4 x i32> %X) nounwind {5; CHECK-LABEL: t0_all_tautological:6; CHECK: // %bb.0:7; CHECK-NEXT: adrp x8, .LCPI0_08; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI0_0]9; CHECK-NEXT: adrp x8, .LCPI0_110; CHECK-NEXT: and v0.16b, v0.16b, v1.16b11; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI0_1]12; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s13; CHECK-NEXT: xtn v0.4h, v0.4s14; CHECK-NEXT: ret15 %urem = urem <4 x i32> %X, <i32 1, i32 1, i32 2, i32 2>16 %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 1, i32 2, i32 3>17 ret <4 x i1> %cmp18}19 20define <4 x i1> @t1_all_odd_eq(<4 x i32> %X) nounwind {21; CHECK-LABEL: t1_all_odd_eq:22; CHECK: // %bb.0:23; CHECK-NEXT: mov w8, #43691 // =0xaaab24; CHECK-NEXT: movk w8, #43690, lsl #1625; CHECK-NEXT: dup v1.4s, w826; CHECK-NEXT: adrp x8, .LCPI1_027; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s28; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI1_0]29; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s30; CHECK-NEXT: movi d1, #0xffff0000ffff000031; CHECK-NEXT: xtn v0.4h, v0.4s32; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b33; CHECK-NEXT: ret34 %urem = urem <4 x i32> %X, <i32 3, i32 1, i32 1, i32 9>35 %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 42, i32 0, i32 42>36 ret <4 x i1> %cmp37}38 39define <4 x i1> @t1_all_odd_ne(<4 x i32> %X) nounwind {40; CHECK-LABEL: t1_all_odd_ne:41; CHECK: // %bb.0:42; CHECK-NEXT: mov w8, #43691 // =0xaaab43; CHECK-NEXT: movk w8, #43690, lsl #1644; CHECK-NEXT: dup v1.4s, w845; CHECK-NEXT: adrp x8, .LCPI2_046; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s47; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI2_0]48; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s49; CHECK-NEXT: movi d1, #0xffff0000ffff000050; CHECK-NEXT: xtn v0.4h, v0.4s51; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b52; CHECK-NEXT: ret53 %urem = urem <4 x i32> %X, <i32 3, i32 1, i32 1, i32 9>54 %cmp = icmp ne <4 x i32> %urem, <i32 0, i32 42, i32 0, i32 42>55 ret <4 x i1> %cmp56}57 58define <8 x i1> @t2_narrow(<8 x i16> %X) nounwind {59; CHECK-LABEL: t2_narrow:60; CHECK: // %bb.0:61; CHECK-NEXT: mov w8, #43691 // =0xaaab62; CHECK-NEXT: dup v1.8h, w863; CHECK-NEXT: adrp x8, .LCPI3_064; CHECK-NEXT: mul v0.8h, v0.8h, v1.8h65; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI3_0]66; CHECK-NEXT: cmhs v0.8h, v1.8h, v0.8h67; CHECK-NEXT: movi d1, #0xffff0000ffff000068; CHECK-NEXT: xtn v0.8b, v0.8h69; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b70; CHECK-NEXT: ret71 %urem = urem <8 x i16> %X, <i16 3, i16 1, i16 1, i16 9, i16 3, i16 1, i16 1, i16 9>72 %cmp = icmp eq <8 x i16> %urem, <i16 0, i16 0, i16 42, i16 42, i16 0, i16 0, i16 42, i16 42>73 ret <8 x i1> %cmp74}75 76define <2 x i1> @t3_wide(<2 x i64> %X) nounwind {77; CHECK-LABEL: t3_wide:78; CHECK: // %bb.0:79; CHECK-NEXT: fmov x10, d080; CHECK-NEXT: mov x8, #-6148914691236517206 // =0xaaaaaaaaaaaaaaaa81; CHECK-NEXT: mov x9, v0.d[1]82; CHECK-NEXT: movk x8, #4369183; CHECK-NEXT: mul x10, x10, x884; CHECK-NEXT: mul x8, x9, x885; CHECK-NEXT: fmov d0, x1086; CHECK-NEXT: mov v0.d[1], x887; CHECK-NEXT: adrp x8, .LCPI4_088; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI4_0]89; CHECK-NEXT: cmhs v0.2d, v1.2d, v0.2d90; CHECK-NEXT: movi d1, #0xffffffff0000000091; CHECK-NEXT: xtn v0.2s, v0.2d92; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b93; CHECK-NEXT: ret94 %urem = urem <2 x i64> %X, <i64 3, i64 1>95 %cmp = icmp eq <2 x i64> %urem, <i64 0, i64 42>96 ret <2 x i1> %cmp97}98