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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s3 4define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) {5; CHECK-LABEL: fold_urem_vec_1:6; CHECK: // %bb.0:7; CHECK-NEXT: adrp x8, .LCPI0_08; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI0_0]9; CHECK-NEXT: adrp x8, .LCPI0_110; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI0_1]11; CHECK-NEXT: adrp x8, .LCPI0_212; CHECK-NEXT: ushl v1.4h, v0.4h, v1.4h13; CHECK-NEXT: umull v1.4s, v1.4h, v2.4h14; CHECK-NEXT: movi d2, #000000000000000015; CHECK-NEXT: shrn v1.4h, v1.4s, #1616; CHECK-NEXT: fneg d2, d217; CHECK-NEXT: sub v3.4h, v0.4h, v1.4h18; CHECK-NEXT: umull v2.4s, v3.4h, v2.4h19; CHECK-NEXT: shrn v2.4h, v2.4s, #1620; CHECK-NEXT: add v1.4h, v2.4h, v1.4h21; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI0_2]22; CHECK-NEXT: adrp x8, .LCPI0_323; CHECK-NEXT: ushl v1.4h, v1.4h, v2.4h24; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI0_3]25; CHECK-NEXT: mls v0.4h, v1.4h, v2.4h26; CHECK-NEXT: ret27 %1 = urem <4 x i16> %x, <i16 95, i16 124, i16 98, i16 1003>28 ret <4 x i16> %129}30 31define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) {32; CHECK-LABEL: fold_urem_vec_2:33; CHECK: // %bb.0:34; CHECK-NEXT: mov w8, #44151 // =0xac7735; CHECK-NEXT: movi v2.4h, #9536; CHECK-NEXT: dup v1.4h, w837; CHECK-NEXT: umull v1.4s, v0.4h, v1.4h38; CHECK-NEXT: ushr v1.4s, v1.4s, #2239; CHECK-NEXT: xtn v1.4h, v1.4s40; CHECK-NEXT: mls v0.4h, v1.4h, v2.4h41; CHECK-NEXT: ret42 %1 = urem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>43 ret <4 x i16> %144}45 46 47; Don't fold if we can combine urem with udiv.48define <4 x i16> @combine_urem_udiv(<4 x i16> %x) {49; CHECK-LABEL: combine_urem_udiv:50; CHECK: // %bb.0:51; CHECK-NEXT: mov w8, #44151 // =0xac7752; CHECK-NEXT: movi v2.4h, #9553; CHECK-NEXT: dup v1.4h, w854; CHECK-NEXT: umull v1.4s, v0.4h, v1.4h55; CHECK-NEXT: ushr v1.4s, v1.4s, #2256; CHECK-NEXT: xtn v1.4h, v1.4s57; CHECK-NEXT: mls v0.4h, v1.4h, v2.4h58; CHECK-NEXT: add v0.4h, v0.4h, v1.4h59; CHECK-NEXT: ret60 %1 = urem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>61 %2 = udiv <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>62 %3 = add <4 x i16> %1, %263 ret <4 x i16> %364}65 66 67; Don't fold for divisors that are a power of two.68define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) {69; CHECK-LABEL: dont_fold_urem_power_of_two:70; CHECK: // %bb.0:71; CHECK-NEXT: adrp x8, .LCPI3_072; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI3_0]73; CHECK-NEXT: adrp x8, .LCPI3_174; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI3_1]75; CHECK-NEXT: adrp x8, .LCPI3_276; CHECK-NEXT: umull v1.4s, v0.4h, v1.4h77; CHECK-NEXT: shrn v1.4h, v1.4s, #1678; CHECK-NEXT: ushl v1.4h, v1.4h, v2.4h79; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI3_2]80; CHECK-NEXT: mls v0.4h, v1.4h, v2.4h81; CHECK-NEXT: ret82 %1 = urem <4 x i16> %x, <i16 64, i16 32, i16 8, i16 95>83 ret <4 x i16> %184}85 86; Don't fold if the divisor is one.87define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) {88; CHECK-LABEL: dont_fold_urem_one:89; CHECK: // %bb.0:90; CHECK-NEXT: adrp x8, .LCPI4_091; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI4_0]92; CHECK-NEXT: adrp x8, .LCPI4_193; CHECK-NEXT: ldr d3, [x8, :lo12:.LCPI4_1]94; CHECK-NEXT: adrp x8, .LCPI4_295; CHECK-NEXT: umull v1.4s, v0.4h, v1.4h96; CHECK-NEXT: shrn v1.4h, v1.4s, #1697; CHECK-NEXT: sub v2.4h, v0.4h, v1.4h98; CHECK-NEXT: umull v2.4s, v2.4h, v3.4h99; CHECK-NEXT: movi d3, #0x0000000000ffff100; CHECK-NEXT: shrn v2.4h, v2.4s, #16101; CHECK-NEXT: add v1.4h, v2.4h, v1.4h102; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI4_2]103; CHECK-NEXT: adrp x8, .LCPI4_3104; CHECK-NEXT: ushl v1.4h, v1.4h, v2.4h105; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI4_3]106; CHECK-NEXT: bit v1.8b, v0.8b, v3.8b107; CHECK-NEXT: mls v0.4h, v1.4h, v2.4h108; CHECK-NEXT: ret109 %1 = urem <4 x i16> %x, <i16 1, i16 654, i16 23, i16 5423>110 ret <4 x i16> %1111}112 113; Don't fold if the divisor is 2^16.114define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {115; CHECK-LABEL: dont_fold_urem_i16_smax:116; CHECK: // %bb.0:117; CHECK-NEXT: ret118 %1 = urem <4 x i16> %x, <i16 1, i16 65536, i16 23, i16 5423>119 ret <4 x i16> %1120}121 122; Don't fold i64 urem.123define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) {124; CHECK-LABEL: dont_fold_urem_i64:125; CHECK: // %bb.0:126; CHECK-NEXT: mov x8, #17097 // =0x42c9127; CHECK-NEXT: fmov x9, d1128; CHECK-NEXT: mov x10, v1.d[1]129; CHECK-NEXT: movk x8, #45590, lsl #16130; CHECK-NEXT: mov x11, v0.d[1]131; CHECK-NEXT: mov x12, #12109 // =0x2f4d132; CHECK-NEXT: movk x8, #34192, lsl #32133; CHECK-NEXT: movk x12, #52170, lsl #16134; CHECK-NEXT: movi v0.2d, #0000000000000000135; CHECK-NEXT: movk x8, #25644, lsl #48136; CHECK-NEXT: movk x12, #28749, lsl #32137; CHECK-NEXT: umulh x8, x9, x8138; CHECK-NEXT: movk x12, #49499, lsl #48139; CHECK-NEXT: lsr x13, x11, #1140; CHECK-NEXT: umulh x12, x10, x12141; CHECK-NEXT: sub x14, x9, x8142; CHECK-NEXT: add x8, x8, x14, lsr #1143; CHECK-NEXT: mov x14, #21445 // =0x53c5144; CHECK-NEXT: movk x14, #1603, lsl #16145; CHECK-NEXT: movk x14, #15432, lsl #32146; CHECK-NEXT: lsr x8, x8, #4147; CHECK-NEXT: movk x14, #25653, lsl #48148; CHECK-NEXT: umulh x13, x13, x14149; CHECK-NEXT: mov w14, #23 // =0x17150; CHECK-NEXT: msub x8, x8, x14, x9151; CHECK-NEXT: lsr x9, x12, #12152; CHECK-NEXT: mov w12, #5423 // =0x152f153; CHECK-NEXT: msub x9, x9, x12, x10154; CHECK-NEXT: mov w12, #654 // =0x28e155; CHECK-NEXT: lsr x10, x13, #7156; CHECK-NEXT: msub x10, x10, x12, x11157; CHECK-NEXT: fmov d1, x8158; CHECK-NEXT: mov v1.d[1], x9159; CHECK-NEXT: mov v0.d[1], x10160; CHECK-NEXT: ret161 %1 = urem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423>162 ret <4 x i64> %1163}164 165define <16 x i8> @fold_urem_v16i8(<16 x i8> %x) {166; CHECK-LABEL: fold_urem_v16i8:167; CHECK: // %bb.0:168; CHECK-NEXT: movi v1.16b, #205169; CHECK-NEXT: umull2 v2.8h, v0.16b, v1.16b170; CHECK-NEXT: umull v1.8h, v0.8b, v1.8b171; CHECK-NEXT: uzp2 v1.16b, v1.16b, v2.16b172; CHECK-NEXT: movi v2.16b, #10173; CHECK-NEXT: ushr v1.16b, v1.16b, #3174; CHECK-NEXT: mls v0.16b, v1.16b, v2.16b175; CHECK-NEXT: ret176 %1 = urem <16 x i8> %x, <i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10>177 ret <16 x i8> %1178}179 180define <8 x i8> @fold_urem_v8i8(<8 x i8> %x) {181; CHECK-LABEL: fold_urem_v8i8:182; CHECK: // %bb.0:183; CHECK-NEXT: movi v1.8b, #205184; CHECK-NEXT: movi v2.8b, #10185; CHECK-NEXT: umull v1.8h, v0.8b, v1.8b186; CHECK-NEXT: shrn v1.8b, v1.8h, #8187; CHECK-NEXT: ushr v1.8b, v1.8b, #3188; CHECK-NEXT: mls v0.8b, v1.8b, v2.8b189; CHECK-NEXT: ret190 %1 = urem <8 x i8> %x, <i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10>191 ret <8 x i8> %1192}193 194define <8 x i16> @fold_urem_v8i16(<8 x i16> %x) {195; CHECK-LABEL: fold_urem_v8i16:196; CHECK: // %bb.0:197; CHECK-NEXT: mov w8, #52429 // =0xcccd198; CHECK-NEXT: dup v1.8h, w8199; CHECK-NEXT: umull2 v2.4s, v0.8h, v1.8h200; CHECK-NEXT: umull v1.4s, v0.4h, v1.4h201; CHECK-NEXT: uzp2 v1.8h, v1.8h, v2.8h202; CHECK-NEXT: movi v2.8h, #10203; CHECK-NEXT: ushr v1.8h, v1.8h, #3204; CHECK-NEXT: mls v0.8h, v1.8h, v2.8h205; CHECK-NEXT: ret206 %1 = urem <8 x i16> %x, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>207 ret <8 x i16> %1208}209 210define <4 x i16> @fold_urem_v4i16(<4 x i16> %x) {211; CHECK-LABEL: fold_urem_v4i16:212; CHECK: // %bb.0:213; CHECK-NEXT: mov w8, #52429 // =0xcccd214; CHECK-NEXT: movi v2.4h, #10215; CHECK-NEXT: dup v1.4h, w8216; CHECK-NEXT: umull v1.4s, v0.4h, v1.4h217; CHECK-NEXT: ushr v1.4s, v1.4s, #19218; CHECK-NEXT: xtn v1.4h, v1.4s219; CHECK-NEXT: mls v0.4h, v1.4h, v2.4h220; CHECK-NEXT: ret221 %1 = urem <4 x i16> %x, <i16 10, i16 10, i16 10, i16 10>222 ret <4 x i16> %1223}224 225define <4 x i32> @fold_urem_v4i32(<4 x i32> %x) {226; CHECK-LABEL: fold_urem_v4i32:227; CHECK: // %bb.0:228; CHECK-NEXT: mov w8, #52429 // =0xcccd229; CHECK-NEXT: movk w8, #52428, lsl #16230; CHECK-NEXT: dup v1.4s, w8231; CHECK-NEXT: umull2 v2.2d, v0.4s, v1.4s232; CHECK-NEXT: umull v1.2d, v0.2s, v1.2s233; CHECK-NEXT: uzp2 v1.4s, v1.4s, v2.4s234; CHECK-NEXT: movi v2.4s, #10235; CHECK-NEXT: ushr v1.4s, v1.4s, #3236; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s237; CHECK-NEXT: ret238 %1 = urem <4 x i32> %x, <i32 10, i32 10, i32 10, i32 10>239 ret <4 x i32> %1240}241 242define <2 x i32> @fold_urem_v2i32(<2 x i32> %x) {243; CHECK-LABEL: fold_urem_v2i32:244; CHECK: // %bb.0:245; CHECK-NEXT: mov w8, #52429 // =0xcccd246; CHECK-NEXT: movi v2.2s, #10247; CHECK-NEXT: movk w8, #52428, lsl #16248; CHECK-NEXT: dup v1.2s, w8249; CHECK-NEXT: umull v1.2d, v0.2s, v1.2s250; CHECK-NEXT: ushr v1.2d, v1.2d, #35251; CHECK-NEXT: xtn v1.2s, v1.2d252; CHECK-NEXT: mls v0.2s, v1.2s, v2.2s253; CHECK-NEXT: ret254 %1 = urem <2 x i32> %x, <i32 10, i32 10>255 ret <2 x i32> %1256}257 258define <2 x i64> @fold_urem_v2i64(<2 x i64> %x) {259; CHECK-LABEL: fold_urem_v2i64:260; CHECK: // %bb.0:261; CHECK-NEXT: fmov x10, d0262; CHECK-NEXT: mov x8, #-3689348814741910324 // =0xcccccccccccccccc263; CHECK-NEXT: mov x9, v0.d[1]264; CHECK-NEXT: movk x8, #52429265; CHECK-NEXT: mov w12, #10 // =0xa266; CHECK-NEXT: umulh x11, x10, x8267; CHECK-NEXT: umulh x8, x9, x8268; CHECK-NEXT: lsr x11, x11, #3269; CHECK-NEXT: msub x10, x11, x12, x10270; CHECK-NEXT: lsr x8, x8, #3271; CHECK-NEXT: msub x8, x8, x12, x9272; CHECK-NEXT: fmov d0, x10273; CHECK-NEXT: mov v0.d[1], x8274; CHECK-NEXT: ret275 %1 = urem <2 x i64> %x, <i64 10, i64 10>276 ret <2 x i64> %1277}278 279define <1 x i64> @fold_urem_v1i64(<1 x i64> %x) {280; CHECK-LABEL: fold_urem_v1i64:281; CHECK: // %bb.0:282; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0283; CHECK-NEXT: fmov x9, d0284; CHECK-NEXT: mov x8, #-3689348814741910324 // =0xcccccccccccccccc285; CHECK-NEXT: mov w10, #10 // =0xa286; CHECK-NEXT: movk x8, #52429287; CHECK-NEXT: umulh x8, x9, x8288; CHECK-NEXT: lsr x8, x8, #3289; CHECK-NEXT: msub x8, x8, x10, x9290; CHECK-NEXT: fmov d0, x8291; CHECK-NEXT: ret292 %1 = urem <1 x i64> %x, <i64 10>293 ret <1 x i64> %1294}295