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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc < %s -mtriple=aarch64-- -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5declare i4 @llvm.usub.sat.i4(i4, i4)6declare i8 @llvm.usub.sat.i8(i8, i8)7declare i16 @llvm.usub.sat.i16(i16, i16)8declare i32 @llvm.usub.sat.i32(i32, i32)9declare i64 @llvm.usub.sat.i64(i64, i64)10 11define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {12; CHECK-SD-LABEL: func32:13; CHECK-SD: // %bb.0:14; CHECK-SD-NEXT: mul w8, w1, w215; CHECK-SD-NEXT: subs w8, w0, w816; CHECK-SD-NEXT: csel w0, wzr, w8, lo17; CHECK-SD-NEXT: ret18;19; CHECK-GI-LABEL: func32:20; CHECK-GI: // %bb.0:21; CHECK-GI-NEXT: mul w8, w1, w222; CHECK-GI-NEXT: subs w8, w0, w823; CHECK-GI-NEXT: cset w9, lo24; CHECK-GI-NEXT: tst w9, #0x125; CHECK-GI-NEXT: csel w0, wzr, w8, ne26; CHECK-GI-NEXT: ret27 %a = mul i32 %y, %z28 %tmp = call i32 @llvm.usub.sat.i32(i32 %x, i32 %a)29 ret i32 %tmp30}31 32define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {33; CHECK-SD-LABEL: func64:34; CHECK-SD: // %bb.0:35; CHECK-SD-NEXT: subs x8, x0, x236; CHECK-SD-NEXT: csel x0, xzr, x8, lo37; CHECK-SD-NEXT: ret38;39; CHECK-GI-LABEL: func64:40; CHECK-GI: // %bb.0:41; CHECK-GI-NEXT: subs x8, x0, x242; CHECK-GI-NEXT: cset w9, lo43; CHECK-GI-NEXT: tst w9, #0x144; CHECK-GI-NEXT: csel x0, xzr, x8, ne45; CHECK-GI-NEXT: ret46 %a = mul i64 %y, %z47 %tmp = call i64 @llvm.usub.sat.i64(i64 %x, i64 %z)48 ret i64 %tmp49}50 51define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {52; CHECK-SD-LABEL: func16:53; CHECK-SD: // %bb.0:54; CHECK-SD-NEXT: mul w8, w1, w255; CHECK-SD-NEXT: and w9, w0, #0xffff56; CHECK-SD-NEXT: subs w8, w9, w8, uxth57; CHECK-SD-NEXT: csel w0, wzr, w8, lo58; CHECK-SD-NEXT: ret59;60; CHECK-GI-LABEL: func16:61; CHECK-GI: // %bb.0:62; CHECK-GI-NEXT: mul w8, w1, w263; CHECK-GI-NEXT: and w9, w0, #0xffff64; CHECK-GI-NEXT: sub w8, w9, w8, uxth65; CHECK-GI-NEXT: cmp w8, w8, uxth66; CHECK-GI-NEXT: csel w0, wzr, w8, ne67; CHECK-GI-NEXT: ret68 %a = mul i16 %y, %z69 %tmp = call i16 @llvm.usub.sat.i16(i16 %x, i16 %a)70 ret i16 %tmp71}72 73define i8 @func8(i8 %x, i8 %y, i8 %z) nounwind {74; CHECK-SD-LABEL: func8:75; CHECK-SD: // %bb.0:76; CHECK-SD-NEXT: mul w8, w1, w277; CHECK-SD-NEXT: and w9, w0, #0xff78; CHECK-SD-NEXT: subs w8, w9, w8, uxtb79; CHECK-SD-NEXT: csel w0, wzr, w8, lo80; CHECK-SD-NEXT: ret81;82; CHECK-GI-LABEL: func8:83; CHECK-GI: // %bb.0:84; CHECK-GI-NEXT: mul w8, w1, w285; CHECK-GI-NEXT: and w9, w0, #0xff86; CHECK-GI-NEXT: sub w8, w9, w8, uxtb87; CHECK-GI-NEXT: cmp w8, w8, uxtb88; CHECK-GI-NEXT: csel w0, wzr, w8, ne89; CHECK-GI-NEXT: ret90 %a = mul i8 %y, %z91 %tmp = call i8 @llvm.usub.sat.i8(i8 %x, i8 %a)92 ret i8 %tmp93}94 95define i4 @func4(i4 %x, i4 %y, i4 %z) nounwind {96; CHECK-SD-LABEL: func4:97; CHECK-SD: // %bb.0:98; CHECK-SD-NEXT: mul w8, w1, w299; CHECK-SD-NEXT: and w9, w0, #0xf100; CHECK-SD-NEXT: and w8, w8, #0xf101; CHECK-SD-NEXT: subs w8, w9, w8102; CHECK-SD-NEXT: csel w0, wzr, w8, lo103; CHECK-SD-NEXT: ret104;105; CHECK-GI-LABEL: func4:106; CHECK-GI: // %bb.0:107; CHECK-GI-NEXT: mul w8, w1, w2108; CHECK-GI-NEXT: and w9, w0, #0xf109; CHECK-GI-NEXT: and w8, w8, #0xf110; CHECK-GI-NEXT: sub w8, w9, w8111; CHECK-GI-NEXT: and w9, w8, #0xf112; CHECK-GI-NEXT: cmp w8, w9113; CHECK-GI-NEXT: csel w0, wzr, w8, ne114; CHECK-GI-NEXT: ret115 %a = mul i4 %y, %z116 %tmp = call i4 @llvm.usub.sat.i4(i4 %x, i4 %a)117 ret i4 %tmp118}119;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:120; CHECK: {{.*}}121