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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=aarch64-apple-darwin -mattr=+neon -verify-machineinstrs < %s | FileCheck %s3 4define void @store_16_elements(<16 x i8> %vec, ptr %out) {5; Bits used in mask6; CHECK-LABEL: store_16_elements:7; CHECK: ; %bb.0:8; CHECK-NEXT: Lloh0:9; CHECK-NEXT: adrp x8, lCPI0_0@PAGE10; CHECK-NEXT: cmeq.16b v0, v0, #011; CHECK-NEXT: Lloh1:12; CHECK-NEXT: ldr q1, [x8, lCPI0_0@PAGEOFF]13; CHECK-NEXT: bic.16b v0, v1, v014; CHECK-NEXT: ext.16b v1, v0, v0, #815; CHECK-NEXT: zip1.16b v0, v0, v116; CHECK-NEXT: addv.8h h0, v017; CHECK-NEXT: str h0, [x0]18; CHECK-NEXT: ret19; CHECK-NEXT: .loh AdrpLdr Lloh0, Lloh120 21; Actual conversion22 23 %cmp_result = icmp ne <16 x i8> %vec, zeroinitializer24 store <16 x i1> %cmp_result, ptr %out25 ret void26}27 28define void @store_8_elements(<8 x i16> %vec, ptr %out) {29; CHECK-LABEL: store_8_elements:30; CHECK: ; %bb.0:31; CHECK-NEXT: Lloh2:32; CHECK-NEXT: adrp x8, lCPI1_0@PAGE33; CHECK-NEXT: cmeq.8h v0, v0, #034; CHECK-NEXT: Lloh3:35; CHECK-NEXT: ldr q1, [x8, lCPI1_0@PAGEOFF]36; CHECK-NEXT: bic.16b v0, v1, v037; CHECK-NEXT: addv.8h h0, v038; CHECK-NEXT: str b0, [x0]39; CHECK-NEXT: ret40; CHECK-NEXT: .loh AdrpLdr Lloh2, Lloh341 42 43 %cmp_result = icmp ne <8 x i16> %vec, zeroinitializer44 store <8 x i1> %cmp_result, ptr %out45 ret void46}47 48define void @store_4_elements(<4 x i32> %vec, ptr %out) {49; CHECK-LABEL: store_4_elements:50; CHECK: ; %bb.0:51; CHECK-NEXT: Lloh4:52; CHECK-NEXT: adrp x8, lCPI2_0@PAGE53; CHECK-NEXT: cmeq.4s v0, v0, #054; CHECK-NEXT: Lloh5:55; CHECK-NEXT: ldr q1, [x8, lCPI2_0@PAGEOFF]56; CHECK-NEXT: bic.16b v0, v1, v057; CHECK-NEXT: addv.4s s0, v058; CHECK-NEXT: str b0, [x0]59; CHECK-NEXT: ret60; CHECK-NEXT: .loh AdrpLdr Lloh4, Lloh561 62 63 %cmp_result = icmp ne <4 x i32> %vec, zeroinitializer64 store <4 x i1> %cmp_result, ptr %out65 ret void66}67 68define void @store_2_elements(<2 x i64> %vec, ptr %out) {69; CHECK-LABEL: store_2_elements:70; CHECK: ; %bb.0:71; CHECK-NEXT: Lloh6:72; CHECK-NEXT: adrp x8, lCPI3_0@PAGE73; CHECK-NEXT: cmeq.2d v0, v0, #074; CHECK-NEXT: Lloh7:75; CHECK-NEXT: ldr q1, [x8, lCPI3_0@PAGEOFF]76; CHECK-NEXT: bic.16b v0, v1, v077; CHECK-NEXT: addp.2d d0, v078; CHECK-NEXT: str b0, [x0]79; CHECK-NEXT: ret80; CHECK-NEXT: .loh AdrpLdr Lloh6, Lloh781 82 83 %cmp_result = icmp ne <2 x i64> %vec, zeroinitializer84 store <2 x i1> %cmp_result, ptr %out85 ret void86}87 88define void @add_trunc_compare_before_store(<4 x i32> %vec, ptr %out) {89; CHECK-LABEL: add_trunc_compare_before_store:90; CHECK: ; %bb.0:91; CHECK-NEXT: shl.4s v0, v0, #3192; CHECK-NEXT: Lloh8:93; CHECK-NEXT: adrp x8, lCPI4_0@PAGE94; CHECK-NEXT: Lloh9:95; CHECK-NEXT: ldr q1, [x8, lCPI4_0@PAGEOFF]96; CHECK-NEXT: cmlt.4s v0, v0, #097; CHECK-NEXT: and.16b v0, v0, v198; CHECK-NEXT: addv.4s s0, v099; CHECK-NEXT: str b0, [x0]100; CHECK-NEXT: ret101; CHECK-NEXT: .loh AdrpLdr Lloh8, Lloh9102 103 104 %trunc = trunc <4 x i32> %vec to <4 x i1>105 store <4 x i1> %trunc, ptr %out106 ret void107}108 109define void @add_trunc_mask_unknown_vector_type(<4 x i1> %vec, ptr %out) {110; CHECK-LABEL: add_trunc_mask_unknown_vector_type:111; CHECK: ; %bb.0:112; CHECK-NEXT: shl.4h v0, v0, #15113; CHECK-NEXT: Lloh10:114; CHECK-NEXT: adrp x8, lCPI5_0@PAGE115; CHECK-NEXT: Lloh11:116; CHECK-NEXT: ldr d1, [x8, lCPI5_0@PAGEOFF]117; CHECK-NEXT: cmlt.4h v0, v0, #0118; CHECK-NEXT: and.8b v0, v0, v1119; CHECK-NEXT: addv.4h h0, v0120; CHECK-NEXT: str b0, [x0]121; CHECK-NEXT: ret122; CHECK-NEXT: .loh AdrpLdr Lloh10, Lloh11123 124 125 store <4 x i1> %vec, ptr %out126 ret void127}128 129define void @store_8_elements_64_bit_vector(<8 x i8> %vec, ptr %out) {130; CHECK-LABEL: store_8_elements_64_bit_vector:131; CHECK: ; %bb.0:132; CHECK-NEXT: Lloh12:133; CHECK-NEXT: adrp x8, lCPI6_0@PAGE134; CHECK-NEXT: cmeq.8b v0, v0, #0135; CHECK-NEXT: Lloh13:136; CHECK-NEXT: ldr d1, [x8, lCPI6_0@PAGEOFF]137; CHECK-NEXT: bic.8b v0, v1, v0138; CHECK-NEXT: addv.8b b0, v0139; CHECK-NEXT: str b0, [x0]140; CHECK-NEXT: ret141; CHECK-NEXT: .loh AdrpLdr Lloh12, Lloh13142 143 144 %cmp_result = icmp ne <8 x i8> %vec, zeroinitializer145 store <8 x i1> %cmp_result, ptr %out146 ret void147}148 149define void @store_4_elements_64_bit_vector(<4 x i16> %vec, ptr %out) {150; CHECK-LABEL: store_4_elements_64_bit_vector:151; CHECK: ; %bb.0:152; CHECK-NEXT: Lloh14:153; CHECK-NEXT: adrp x8, lCPI7_0@PAGE154; CHECK-NEXT: cmeq.4h v0, v0, #0155; CHECK-NEXT: Lloh15:156; CHECK-NEXT: ldr d1, [x8, lCPI7_0@PAGEOFF]157; CHECK-NEXT: bic.8b v0, v1, v0158; CHECK-NEXT: addv.4h h0, v0159; CHECK-NEXT: str b0, [x0]160; CHECK-NEXT: ret161; CHECK-NEXT: .loh AdrpLdr Lloh14, Lloh15162 163 164 %cmp_result = icmp ne <4 x i16> %vec, zeroinitializer165 store <4 x i1> %cmp_result, ptr %out166 ret void167}168 169define void @store_2_elements_64_bit_vector(<2 x i32> %vec, ptr %out) {170; CHECK-LABEL: store_2_elements_64_bit_vector:171; CHECK: ; %bb.0:172; CHECK-NEXT: Lloh16:173; CHECK-NEXT: adrp x8, lCPI8_0@PAGE174; CHECK-NEXT: cmeq.2s v0, v0, #0175; CHECK-NEXT: Lloh17:176; CHECK-NEXT: ldr d1, [x8, lCPI8_0@PAGEOFF]177; CHECK-NEXT: bic.8b v0, v1, v0178; CHECK-NEXT: addp.2s v0, v0, v0179; CHECK-NEXT: str b0, [x0]180; CHECK-NEXT: ret181; CHECK-NEXT: .loh AdrpLdr Lloh16, Lloh17182 183 184 %cmp_result = icmp ne <2 x i32> %vec, zeroinitializer185 store <2 x i1> %cmp_result, ptr %out186 ret void187}188 189define void @no_combine_without_truncate(<16 x i8> %vec, ptr %out) {190; CHECK-LABEL: no_combine_without_truncate:191; CHECK: ; %bb.0:192; CHECK-NEXT: cmtst.16b v0, v0, v0193; CHECK-NEXT: str q0, [x0]194; CHECK-NEXT: ret195 196 %cmp_result = icmp ne <16 x i8> %vec, zeroinitializer197 %extended_result = sext <16 x i1> %cmp_result to <16 x i8>198 store <16 x i8> %extended_result, ptr %out199 ret void200}201 202define void @no_combine_for_non_bool_truncate(<4 x i32> %vec, ptr %out) {203; CHECK-LABEL: no_combine_for_non_bool_truncate:204; CHECK: ; %bb.0:205; CHECK-NEXT: xtn.4h v0, v0206; CHECK-NEXT: uzp1.8b v0, v0, v0207; CHECK-NEXT: str s0, [x0]208; CHECK-NEXT: ret209 210 %trunc = trunc <4 x i32> %vec to <4 x i8>211 store <4 x i8> %trunc, ptr %out212 ret void213}214 215define void @no_combine_for_build_vector(i1 %a, i1 %b, i1 %c, i1 %d, ptr %out) {216; CHECK-LABEL: no_combine_for_build_vector:217; CHECK: ; %bb.0:218; CHECK-NEXT: orr w8, w0, w1, lsl #1219; CHECK-NEXT: orr w8, w8, w2, lsl #2220; CHECK-NEXT: orr w8, w8, w3, lsl #3221; CHECK-NEXT: strb w8, [x4]222; CHECK-NEXT: ret223 224 %1 = insertelement <4 x i1> undef, i1 %a, i64 0225 %2 = insertelement <4 x i1> %1, i1 %b, i64 1226 %3 = insertelement <4 x i1> %2, i1 %c, i64 2227 %vec = insertelement <4 x i1> %3, i1 %d, i64 3228 store <4 x i1> %vec, ptr %out229 ret void230}231