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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK3 4declare {<1 x i32>, <1 x i1>} @llvm.umul.with.overflow.v1i32(<1 x i32>, <1 x i32>)5declare {<2 x i32>, <2 x i1>} @llvm.umul.with.overflow.v2i32(<2 x i32>, <2 x i32>)6declare {<3 x i32>, <3 x i1>} @llvm.umul.with.overflow.v3i32(<3 x i32>, <3 x i32>)7declare {<4 x i32>, <4 x i1>} @llvm.umul.with.overflow.v4i32(<4 x i32>, <4 x i32>)8declare {<6 x i32>, <6 x i1>} @llvm.umul.with.overflow.v6i32(<6 x i32>, <6 x i32>)9declare {<8 x i32>, <8 x i1>} @llvm.umul.with.overflow.v8i32(<8 x i32>, <8 x i32>)10 11declare {<16 x i8>, <16 x i1>} @llvm.umul.with.overflow.v16i8(<16 x i8>, <16 x i8>)12declare {<8 x i16>, <8 x i1>} @llvm.umul.with.overflow.v8i16(<8 x i16>, <8 x i16>)13declare {<2 x i64>, <2 x i1>} @llvm.umul.with.overflow.v2i64(<2 x i64>, <2 x i64>)14 15declare {<4 x i24>, <4 x i1>} @llvm.umul.with.overflow.v4i24(<4 x i24>, <4 x i24>)16declare {<4 x i1>, <4 x i1>} @llvm.umul.with.overflow.v4i1(<4 x i1>, <4 x i1>)17declare {<2 x i128>, <2 x i1>} @llvm.umul.with.overflow.v2i128(<2 x i128>, <2 x i128>)18 19define <1 x i32> @umulo_v1i32(<1 x i32> %a0, <1 x i32> %a1, ptr %p2) nounwind {20; CHECK-LABEL: umulo_v1i32:21; CHECK: // %bb.0:22; CHECK-NEXT: umull v1.2d, v0.2s, v1.2s23; CHECK-NEXT: shrn v0.2s, v1.2d, #3224; CHECK-NEXT: xtn v1.2s, v1.2d25; CHECK-NEXT: cmtst v0.2s, v0.2s, v0.2s26; CHECK-NEXT: str s1, [x0]27; CHECK-NEXT: ret28 %t = call {<1 x i32>, <1 x i1>} @llvm.umul.with.overflow.v1i32(<1 x i32> %a0, <1 x i32> %a1)29 %val = extractvalue {<1 x i32>, <1 x i1>} %t, 030 %obit = extractvalue {<1 x i32>, <1 x i1>} %t, 131 %res = sext <1 x i1> %obit to <1 x i32>32 store <1 x i32> %val, ptr %p233 ret <1 x i32> %res34}35 36define <2 x i32> @umulo_v2i32(<2 x i32> %a0, <2 x i32> %a1, ptr %p2) nounwind {37; CHECK-LABEL: umulo_v2i32:38; CHECK: // %bb.0:39; CHECK-NEXT: umull v1.2d, v0.2s, v1.2s40; CHECK-NEXT: shrn v0.2s, v1.2d, #3241; CHECK-NEXT: xtn v1.2s, v1.2d42; CHECK-NEXT: cmtst v0.2s, v0.2s, v0.2s43; CHECK-NEXT: str d1, [x0]44; CHECK-NEXT: ret45 %t = call {<2 x i32>, <2 x i1>} @llvm.umul.with.overflow.v2i32(<2 x i32> %a0, <2 x i32> %a1)46 %val = extractvalue {<2 x i32>, <2 x i1>} %t, 047 %obit = extractvalue {<2 x i32>, <2 x i1>} %t, 148 %res = sext <2 x i1> %obit to <2 x i32>49 store <2 x i32> %val, ptr %p250 ret <2 x i32> %res51}52 53define <3 x i32> @umulo_v3i32(<3 x i32> %a0, <3 x i32> %a1, ptr %p2) nounwind {54; CHECK-LABEL: umulo_v3i32:55; CHECK: // %bb.0:56; CHECK-NEXT: umull2 v2.2d, v0.4s, v1.4s57; CHECK-NEXT: umull v3.2d, v0.2s, v1.2s58; CHECK-NEXT: mul v1.4s, v0.4s, v1.4s59; CHECK-NEXT: uzp2 v2.4s, v3.4s, v2.4s60; CHECK-NEXT: str d1, [x0]61; CHECK-NEXT: cmtst v0.4s, v2.4s, v2.4s62; CHECK-NEXT: mov s2, v1.s[2]63; CHECK-NEXT: str s2, [x0, #8]64; CHECK-NEXT: ret65 %t = call {<3 x i32>, <3 x i1>} @llvm.umul.with.overflow.v3i32(<3 x i32> %a0, <3 x i32> %a1)66 %val = extractvalue {<3 x i32>, <3 x i1>} %t, 067 %obit = extractvalue {<3 x i32>, <3 x i1>} %t, 168 %res = sext <3 x i1> %obit to <3 x i32>69 store <3 x i32> %val, ptr %p270 ret <3 x i32> %res71}72 73define <4 x i32> @umulo_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %p2) nounwind {74; CHECK-LABEL: umulo_v4i32:75; CHECK: // %bb.0:76; CHECK-NEXT: umull2 v2.2d, v0.4s, v1.4s77; CHECK-NEXT: umull v3.2d, v0.2s, v1.2s78; CHECK-NEXT: mul v1.4s, v0.4s, v1.4s79; CHECK-NEXT: uzp2 v2.4s, v3.4s, v2.4s80; CHECK-NEXT: str q1, [x0]81; CHECK-NEXT: cmtst v2.4s, v2.4s, v2.4s82; CHECK-NEXT: mov v0.16b, v2.16b83; CHECK-NEXT: ret84 %t = call {<4 x i32>, <4 x i1>} @llvm.umul.with.overflow.v4i32(<4 x i32> %a0, <4 x i32> %a1)85 %val = extractvalue {<4 x i32>, <4 x i1>} %t, 086 %obit = extractvalue {<4 x i32>, <4 x i1>} %t, 187 %res = sext <4 x i1> %obit to <4 x i32>88 store <4 x i32> %val, ptr %p289 ret <4 x i32> %res90}91 92define <6 x i32> @umulo_v6i32(<6 x i32> %a0, <6 x i32> %a1, ptr %p2) nounwind {93; CHECK-LABEL: umulo_v6i32:94; CHECK: // %bb.0:95; CHECK-NEXT: fmov s0, w096; CHECK-NEXT: fmov s1, w697; CHECK-NEXT: mov x8, sp98; CHECK-NEXT: fmov s3, w499; CHECK-NEXT: ldr s2, [sp, #16]100; CHECK-NEXT: add x9, sp, #24101; CHECK-NEXT: mov v0.s[1], w1102; CHECK-NEXT: mov v1.s[1], w7103; CHECK-NEXT: ld1 { v2.s }[1], [x9]104; CHECK-NEXT: mov v3.s[1], w5105; CHECK-NEXT: mov v0.s[2], w2106; CHECK-NEXT: ld1 { v1.s }[2], [x8]107; CHECK-NEXT: add x8, sp, #8108; CHECK-NEXT: umull2 v6.2d, v3.4s, v2.4s109; CHECK-NEXT: umull v7.2d, v3.2s, v2.2s110; CHECK-NEXT: mul v2.4s, v3.4s, v2.4s111; CHECK-NEXT: ld1 { v1.s }[3], [x8]112; CHECK-NEXT: ldr x8, [sp, #32]113; CHECK-NEXT: mov v0.s[3], w3114; CHECK-NEXT: str d2, [x8, #16]115; CHECK-NEXT: umull2 v4.2d, v0.4s, v1.4s116; CHECK-NEXT: umull v5.2d, v0.2s, v1.2s117; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s118; CHECK-NEXT: uzp2 v4.4s, v5.4s, v4.4s119; CHECK-NEXT: uzp2 v5.4s, v7.4s, v6.4s120; CHECK-NEXT: str q0, [x8]121; CHECK-NEXT: cmtst v4.4s, v4.4s, v4.4s122; CHECK-NEXT: cmtst v5.4s, v5.4s, v5.4s123; CHECK-NEXT: mov w1, v4.s[1]124; CHECK-NEXT: mov w2, v4.s[2]125; CHECK-NEXT: mov w5, v5.s[1]126; CHECK-NEXT: mov w3, v4.s[3]127; CHECK-NEXT: fmov w4, s5128; CHECK-NEXT: fmov w0, s4129; CHECK-NEXT: ret130 %t = call {<6 x i32>, <6 x i1>} @llvm.umul.with.overflow.v6i32(<6 x i32> %a0, <6 x i32> %a1)131 %val = extractvalue {<6 x i32>, <6 x i1>} %t, 0132 %obit = extractvalue {<6 x i32>, <6 x i1>} %t, 1133 %res = sext <6 x i1> %obit to <6 x i32>134 store <6 x i32> %val, ptr %p2135 ret <6 x i32> %res136}137 138define <8 x i32> @umulo_v8i32(<8 x i32> %a0, <8 x i32> %a1, ptr %p2) nounwind {139; CHECK-LABEL: umulo_v8i32:140; CHECK: // %bb.0:141; CHECK-NEXT: umull2 v4.2d, v0.4s, v2.4s142; CHECK-NEXT: umull v5.2d, v0.2s, v2.2s143; CHECK-NEXT: umull2 v6.2d, v1.4s, v3.4s144; CHECK-NEXT: umull v7.2d, v1.2s, v3.2s145; CHECK-NEXT: mul v1.4s, v1.4s, v3.4s146; CHECK-NEXT: mul v2.4s, v0.4s, v2.4s147; CHECK-NEXT: uzp2 v4.4s, v5.4s, v4.4s148; CHECK-NEXT: uzp2 v5.4s, v7.4s, v6.4s149; CHECK-NEXT: stp q2, q1, [x0]150; CHECK-NEXT: cmtst v4.4s, v4.4s, v4.4s151; CHECK-NEXT: cmtst v5.4s, v5.4s, v5.4s152; CHECK-NEXT: mov v0.16b, v4.16b153; CHECK-NEXT: mov v1.16b, v5.16b154; CHECK-NEXT: ret155 %t = call {<8 x i32>, <8 x i1>} @llvm.umul.with.overflow.v8i32(<8 x i32> %a0, <8 x i32> %a1)156 %val = extractvalue {<8 x i32>, <8 x i1>} %t, 0157 %obit = extractvalue {<8 x i32>, <8 x i1>} %t, 1158 %res = sext <8 x i1> %obit to <8 x i32>159 store <8 x i32> %val, ptr %p2160 ret <8 x i32> %res161}162 163define <16 x i32> @umulo_v16i8(<16 x i8> %a0, <16 x i8> %a1, ptr %p2) nounwind {164; CHECK-LABEL: umulo_v16i8:165; CHECK: // %bb.0:166; CHECK-NEXT: umull2 v2.8h, v0.16b, v1.16b167; CHECK-NEXT: umull v3.8h, v0.8b, v1.8b168; CHECK-NEXT: mul v6.16b, v0.16b, v1.16b169; CHECK-NEXT: uzp2 v2.16b, v3.16b, v2.16b170; CHECK-NEXT: str q6, [x0]171; CHECK-NEXT: cmtst v2.16b, v2.16b, v2.16b172; CHECK-NEXT: ext v3.16b, v2.16b, v2.16b, #8173; CHECK-NEXT: zip1 v4.8b, v2.8b, v0.8b174; CHECK-NEXT: zip2 v2.8b, v2.8b, v0.8b175; CHECK-NEXT: zip1 v5.8b, v3.8b, v0.8b176; CHECK-NEXT: zip2 v3.8b, v3.8b, v0.8b177; CHECK-NEXT: ushll v4.4s, v4.4h, #0178; CHECK-NEXT: ushll v2.4s, v2.4h, #0179; CHECK-NEXT: shl v4.4s, v4.4s, #31180; CHECK-NEXT: ushll v5.4s, v5.4h, #0181; CHECK-NEXT: ushll v3.4s, v3.4h, #0182; CHECK-NEXT: shl v2.4s, v2.4s, #31183; CHECK-NEXT: cmlt v0.4s, v4.4s, #0184; CHECK-NEXT: shl v5.4s, v5.4s, #31185; CHECK-NEXT: shl v3.4s, v3.4s, #31186; CHECK-NEXT: cmlt v1.4s, v2.4s, #0187; CHECK-NEXT: cmlt v2.4s, v5.4s, #0188; CHECK-NEXT: cmlt v3.4s, v3.4s, #0189; CHECK-NEXT: ret190 %t = call {<16 x i8>, <16 x i1>} @llvm.umul.with.overflow.v16i8(<16 x i8> %a0, <16 x i8> %a1)191 %val = extractvalue {<16 x i8>, <16 x i1>} %t, 0192 %obit = extractvalue {<16 x i8>, <16 x i1>} %t, 1193 %res = sext <16 x i1> %obit to <16 x i32>194 store <16 x i8> %val, ptr %p2195 ret <16 x i32> %res196}197 198define <8 x i32> @umulo_v8i16(<8 x i16> %a0, <8 x i16> %a1, ptr %p2) nounwind {199; CHECK-LABEL: umulo_v8i16:200; CHECK: // %bb.0:201; CHECK-NEXT: umull2 v2.4s, v0.8h, v1.8h202; CHECK-NEXT: umull v3.4s, v0.4h, v1.4h203; CHECK-NEXT: mul v4.8h, v0.8h, v1.8h204; CHECK-NEXT: uzp2 v2.8h, v3.8h, v2.8h205; CHECK-NEXT: str q4, [x0]206; CHECK-NEXT: cmtst v2.8h, v2.8h, v2.8h207; CHECK-NEXT: xtn v2.8b, v2.8h208; CHECK-NEXT: zip1 v3.8b, v2.8b, v0.8b209; CHECK-NEXT: zip2 v2.8b, v2.8b, v0.8b210; CHECK-NEXT: ushll v3.4s, v3.4h, #0211; CHECK-NEXT: ushll v2.4s, v2.4h, #0212; CHECK-NEXT: shl v3.4s, v3.4s, #31213; CHECK-NEXT: shl v2.4s, v2.4s, #31214; CHECK-NEXT: cmlt v0.4s, v3.4s, #0215; CHECK-NEXT: cmlt v1.4s, v2.4s, #0216; CHECK-NEXT: ret217 %t = call {<8 x i16>, <8 x i1>} @llvm.umul.with.overflow.v8i16(<8 x i16> %a0, <8 x i16> %a1)218 %val = extractvalue {<8 x i16>, <8 x i1>} %t, 0219 %obit = extractvalue {<8 x i16>, <8 x i1>} %t, 1220 %res = sext <8 x i1> %obit to <8 x i32>221 store <8 x i16> %val, ptr %p2222 ret <8 x i32> %res223}224 225define <2 x i32> @umulo_v2i64(<2 x i64> %a0, <2 x i64> %a1, ptr %p2) nounwind {226; CHECK-LABEL: umulo_v2i64:227; CHECK: // %bb.0:228; CHECK-NEXT: mov x8, v1.d[1]229; CHECK-NEXT: mov x9, v0.d[1]230; CHECK-NEXT: fmov x11, d1231; CHECK-NEXT: fmov x12, d0232; CHECK-NEXT: umulh x10, x9, x8233; CHECK-NEXT: umulh x13, x12, x11234; CHECK-NEXT: mul x11, x12, x11235; CHECK-NEXT: cmp xzr, x10236; CHECK-NEXT: csetm x10, ne237; CHECK-NEXT: mul x8, x9, x8238; CHECK-NEXT: cmp xzr, x13239; CHECK-NEXT: csetm x13, ne240; CHECK-NEXT: fmov d0, x13241; CHECK-NEXT: fmov d1, x11242; CHECK-NEXT: mov v0.d[1], x10243; CHECK-NEXT: mov v1.d[1], x8244; CHECK-NEXT: xtn v0.2s, v0.2d245; CHECK-NEXT: str q1, [x0]246; CHECK-NEXT: ret247 %t = call {<2 x i64>, <2 x i1>} @llvm.umul.with.overflow.v2i64(<2 x i64> %a0, <2 x i64> %a1)248 %val = extractvalue {<2 x i64>, <2 x i1>} %t, 0249 %obit = extractvalue {<2 x i64>, <2 x i1>} %t, 1250 %res = sext <2 x i1> %obit to <2 x i32>251 store <2 x i64> %val, ptr %p2252 ret <2 x i32> %res253}254 255define <4 x i32> @umulo_v4i24(<4 x i24> %a0, <4 x i24> %a1, ptr %p2) nounwind {256; CHECK-LABEL: umulo_v4i24:257; CHECK: // %bb.0:258; CHECK-NEXT: bic v1.4s, #255, lsl #24259; CHECK-NEXT: bic v0.4s, #255, lsl #24260; CHECK-NEXT: umull2 v2.2d, v0.4s, v1.4s261; CHECK-NEXT: umull v3.2d, v0.2s, v1.2s262; CHECK-NEXT: mul v1.4s, v0.4s, v1.4s263; CHECK-NEXT: mov w8, v1.s[3]264; CHECK-NEXT: uzp2 v0.4s, v3.4s, v2.4s265; CHECK-NEXT: ushr v2.4s, v1.4s, #24266; CHECK-NEXT: mov w10, v1.s[1]267; CHECK-NEXT: mov w9, v1.s[2]268; CHECK-NEXT: str h1, [x0]269; CHECK-NEXT: cmtst v2.4s, v2.4s, v2.4s270; CHECK-NEXT: sturh w8, [x0, #9]271; CHECK-NEXT: lsr w8, w8, #16272; CHECK-NEXT: cmeq v0.4s, v0.4s, #0273; CHECK-NEXT: sturh w10, [x0, #3]274; CHECK-NEXT: strb w8, [x0, #11]275; CHECK-NEXT: lsr w8, w10, #16276; CHECK-NEXT: fmov w10, s1277; CHECK-NEXT: strh w9, [x0, #6]278; CHECK-NEXT: lsr w9, w9, #16279; CHECK-NEXT: orn v0.16b, v2.16b, v0.16b280; CHECK-NEXT: strb w8, [x0, #5]281; CHECK-NEXT: strb w9, [x0, #8]282; CHECK-NEXT: lsr w9, w10, #16283; CHECK-NEXT: strb w9, [x0, #2]284; CHECK-NEXT: ret285 %t = call {<4 x i24>, <4 x i1>} @llvm.umul.with.overflow.v4i24(<4 x i24> %a0, <4 x i24> %a1)286 %val = extractvalue {<4 x i24>, <4 x i1>} %t, 0287 %obit = extractvalue {<4 x i24>, <4 x i1>} %t, 1288 %res = sext <4 x i1> %obit to <4 x i32>289 store <4 x i24> %val, ptr %p2290 ret <4 x i32> %res291}292 293define <4 x i32> @umulo_v4i1(<4 x i1> %a0, <4 x i1> %a1, ptr %p2) nounwind {294; CHECK-LABEL: umulo_v4i1:295; CHECK: // %bb.0:296; CHECK-NEXT: and v0.8b, v0.8b, v1.8b297; CHECK-NEXT: adrp x8, .LCPI10_0298; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI10_0]299; CHECK-NEXT: shl v0.4h, v0.4h, #15300; CHECK-NEXT: cmlt v0.4h, v0.4h, #0301; CHECK-NEXT: and v1.8b, v0.8b, v1.8b302; CHECK-NEXT: movi v0.2d, #0000000000000000303; CHECK-NEXT: addv h1, v1.4h304; CHECK-NEXT: str b1, [x0]305; CHECK-NEXT: ret306 %t = call {<4 x i1>, <4 x i1>} @llvm.umul.with.overflow.v4i1(<4 x i1> %a0, <4 x i1> %a1)307 %val = extractvalue {<4 x i1>, <4 x i1>} %t, 0308 %obit = extractvalue {<4 x i1>, <4 x i1>} %t, 1309 %res = sext <4 x i1> %obit to <4 x i32>310 store <4 x i1> %val, ptr %p2311 ret <4 x i32> %res312}313 314define <2 x i32> @umulo_v2i128(<2 x i128> %a0, <2 x i128> %a1, ptr %p2) nounwind {315; CHECK-LABEL: umulo_v2i128:316; CHECK: // %bb.0:317; CHECK-NEXT: mul x9, x7, x2318; CHECK-NEXT: cmp x3, #0319; CHECK-NEXT: ccmp x7, #0, #4, ne320; CHECK-NEXT: umulh x10, x3, x6321; CHECK-NEXT: umulh x8, x7, x2322; CHECK-NEXT: madd x9, x3, x6, x9323; CHECK-NEXT: ccmp xzr, x10, #0, eq324; CHECK-NEXT: umulh x11, x2, x6325; CHECK-NEXT: ccmp xzr, x8, #0, eq326; CHECK-NEXT: mul x13, x5, x0327; CHECK-NEXT: cset w8, ne328; CHECK-NEXT: umulh x14, x1, x4329; CHECK-NEXT: adds x9, x11, x9330; CHECK-NEXT: umulh x12, x5, x0331; CHECK-NEXT: csinc w8, w8, wzr, lo332; CHECK-NEXT: cmp x1, #0333; CHECK-NEXT: ccmp x5, #0, #4, ne334; CHECK-NEXT: madd x10, x1, x4, x13335; CHECK-NEXT: ccmp xzr, x14, #0, eq336; CHECK-NEXT: umulh x11, x0, x4337; CHECK-NEXT: ccmp xzr, x12, #0, eq338; CHECK-NEXT: cset w12, ne339; CHECK-NEXT: adds x10, x11, x10340; CHECK-NEXT: csinc w11, w12, wzr, lo341; CHECK-NEXT: ldr x12, [sp]342; CHECK-NEXT: fmov s0, w11343; CHECK-NEXT: mul x11, x2, x6344; CHECK-NEXT: mov v0.s[1], w8345; CHECK-NEXT: mul x8, x0, x4346; CHECK-NEXT: stp x11, x9, [x12, #16]347; CHECK-NEXT: shl v0.2s, v0.2s, #31348; CHECK-NEXT: stp x8, x10, [x12]349; CHECK-NEXT: cmlt v0.2s, v0.2s, #0350; CHECK-NEXT: ret351 %t = call {<2 x i128>, <2 x i1>} @llvm.umul.with.overflow.v2i128(<2 x i128> %a0, <2 x i128> %a1)352 %val = extractvalue {<2 x i128>, <2 x i1>} %t, 0353 %obit = extractvalue {<2 x i128>, <2 x i1>} %t, 1354 %res = sext <2 x i1> %obit to <2 x i32>355 store <2 x i128> %val, ptr %p2356 ret <2 x i32> %res357}358