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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=aarch64-gnu-linux -mattr=+neon,+sve -vector-library=sleefgnuabi < %s | FileCheck %s -check-prefix=SLEEF3; RUN: llc -mtriple=aarch64-gnu-linux -mattr=+neon,+sve -vector-library=ArmPL < %s | FileCheck %s -check-prefix=ARMPL4 5define void @test_sincospi_v4f32(<4 x float> %x, ptr noalias %out_sin, ptr noalias %out_cos) {6; SLEEF-LABEL: test_sincospi_v4f32:7; SLEEF: // %bb.0:8; SLEEF-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill9; SLEEF-NEXT: .cfi_def_cfa_offset 1610; SLEEF-NEXT: .cfi_offset w30, -1611; SLEEF-NEXT: bl _ZGVnN4vl4l4_sincospif12; SLEEF-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload13; SLEEF-NEXT: ret14;15; ARMPL-LABEL: test_sincospi_v4f32:16; ARMPL: // %bb.0:17; ARMPL-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill18; ARMPL-NEXT: .cfi_def_cfa_offset 1619; ARMPL-NEXT: .cfi_offset w30, -1620; ARMPL-NEXT: bl armpl_vsincospiq_f3221; ARMPL-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload22; ARMPL-NEXT: ret23 %result = call { <4 x float>, <4 x float> } @llvm.sincospi.v4f32(<4 x float> %x)24 %result.0 = extractvalue { <4 x float>, <4 x float> } %result, 025 %result.1 = extractvalue { <4 x float>, <4 x float> } %result, 126 store <4 x float> %result.0, ptr %out_sin, align 427 store <4 x float> %result.1, ptr %out_cos, align 428 ret void29}30 31define void @test_sincospi_v2f64(<2 x double> %x, ptr noalias %out_sin, ptr noalias %out_cos) {32; SLEEF-LABEL: test_sincospi_v2f64:33; SLEEF: // %bb.0:34; SLEEF-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill35; SLEEF-NEXT: .cfi_def_cfa_offset 1636; SLEEF-NEXT: .cfi_offset w30, -1637; SLEEF-NEXT: bl _ZGVnN2vl8l8_sincospi38; SLEEF-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload39; SLEEF-NEXT: ret40;41; ARMPL-LABEL: test_sincospi_v2f64:42; ARMPL: // %bb.0:43; ARMPL-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill44; ARMPL-NEXT: .cfi_def_cfa_offset 1645; ARMPL-NEXT: .cfi_offset w30, -1646; ARMPL-NEXT: bl armpl_vsincospiq_f6447; ARMPL-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload48; ARMPL-NEXT: ret49 %result = call { <2 x double>, <2 x double> } @llvm.sincospi.v2f64(<2 x double> %x)50 %result.0 = extractvalue { <2 x double>, <2 x double> } %result, 051 %result.1 = extractvalue { <2 x double>, <2 x double> } %result, 152 store <2 x double> %result.0, ptr %out_sin, align 853 store <2 x double> %result.1, ptr %out_cos, align 854 ret void55}56 57define void @test_sincospi_nxv4f32(<vscale x 4 x float> %x, ptr noalias %out_sin, ptr noalias %out_cos) {58; SLEEF-LABEL: test_sincospi_nxv4f32:59; SLEEF: // %bb.0:60; SLEEF-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill61; SLEEF-NEXT: .cfi_def_cfa_offset 1662; SLEEF-NEXT: .cfi_offset w30, -1663; SLEEF-NEXT: bl _ZGVsNxvl4l4_sincospif64; SLEEF-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload65; SLEEF-NEXT: ret66;67; ARMPL-LABEL: test_sincospi_nxv4f32:68; ARMPL: // %bb.0:69; ARMPL-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill70; ARMPL-NEXT: .cfi_def_cfa_offset 1671; ARMPL-NEXT: .cfi_offset w30, -1672; ARMPL-NEXT: ptrue p0.s73; ARMPL-NEXT: bl armpl_svsincospi_f32_x74; ARMPL-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload75; ARMPL-NEXT: ret76 %result = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.sincospi.nxv4f32(<vscale x 4 x float> %x)77 %result.0 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %result, 078 %result.1 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %result, 179 store <vscale x 4 x float> %result.0, ptr %out_sin, align 480 store <vscale x 4 x float> %result.1, ptr %out_cos, align 481 ret void82}83 84define void @test_sincospi_nxv2f64(<vscale x 2 x double> %x, ptr noalias %out_sin, ptr noalias %out_cos) {85; SLEEF-LABEL: test_sincospi_nxv2f64:86; SLEEF: // %bb.0:87; SLEEF-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill88; SLEEF-NEXT: .cfi_def_cfa_offset 1689; SLEEF-NEXT: .cfi_offset w30, -1690; SLEEF-NEXT: bl _ZGVsNxvl8l8_sincospi91; SLEEF-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload92; SLEEF-NEXT: ret93;94; ARMPL-LABEL: test_sincospi_nxv2f64:95; ARMPL: // %bb.0:96; ARMPL-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill97; ARMPL-NEXT: .cfi_def_cfa_offset 1698; ARMPL-NEXT: .cfi_offset w30, -1699; ARMPL-NEXT: ptrue p0.d100; ARMPL-NEXT: bl armpl_svsincospi_f64_x101; ARMPL-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload102; ARMPL-NEXT: ret103 %result = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.sincospi.nxv2f64(<vscale x 2 x double> %x)104 %result.0 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %result, 0105 %result.1 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %result, 1106 store <vscale x 2 x double> %result.0, ptr %out_sin, align 8107 store <vscale x 2 x double> %result.1, ptr %out_cos, align 8108 ret void109}110