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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK3 4declare i1 @llvm.vector.reduce.add.v1i1(<1 x i1> %a)5declare i8 @llvm.vector.reduce.add.v1i8(<1 x i8> %a)6declare i16 @llvm.vector.reduce.add.v1i16(<1 x i16> %a)7declare i24 @llvm.vector.reduce.add.v1i24(<1 x i24> %a)8declare i32 @llvm.vector.reduce.add.v1i32(<1 x i32> %a)9declare i64 @llvm.vector.reduce.add.v1i64(<1 x i64> %a)10declare i128 @llvm.vector.reduce.add.v1i128(<1 x i128> %a)11 12declare i8 @llvm.vector.reduce.add.v3i8(<3 x i8> %a)13declare i8 @llvm.vector.reduce.add.v9i8(<9 x i8> %a)14declare i32 @llvm.vector.reduce.add.v3i32(<3 x i32> %a)15declare i1 @llvm.vector.reduce.add.v4i1(<4 x i1> %a)16declare i24 @llvm.vector.reduce.add.v4i24(<4 x i24> %a)17declare i128 @llvm.vector.reduce.add.v2i128(<2 x i128> %a)18declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %a)19 20define i1 @test_v1i1(<1 x i1> %a) nounwind {21; CHECK-LABEL: test_v1i1:22; CHECK: // %bb.0:23; CHECK-NEXT: and w0, w0, #0x124; CHECK-NEXT: ret25 %b = call i1 @llvm.vector.reduce.add.v1i1(<1 x i1> %a)26 ret i1 %b27}28 29define i8 @test_v1i8(<1 x i8> %a) nounwind {30; CHECK-LABEL: test_v1i8:31; CHECK: // %bb.0:32; CHECK-NEXT: // kill: def $d0 killed $d0 def $q033; CHECK-NEXT: umov w0, v0.b[0]34; CHECK-NEXT: ret35 %b = call i8 @llvm.vector.reduce.add.v1i8(<1 x i8> %a)36 ret i8 %b37}38 39define i16 @test_v1i16(<1 x i16> %a) nounwind {40; CHECK-LABEL: test_v1i16:41; CHECK: // %bb.0:42; CHECK-NEXT: // kill: def $d0 killed $d0 def $q043; CHECK-NEXT: umov w0, v0.h[0]44; CHECK-NEXT: ret45 %b = call i16 @llvm.vector.reduce.add.v1i16(<1 x i16> %a)46 ret i16 %b47}48 49define i24 @test_v1i24(<1 x i24> %a) nounwind {50; CHECK-LABEL: test_v1i24:51; CHECK: // %bb.0:52; CHECK-NEXT: ret53 %b = call i24 @llvm.vector.reduce.add.v1i24(<1 x i24> %a)54 ret i24 %b55}56 57define i32 @test_v1i32(<1 x i32> %a) nounwind {58; CHECK-LABEL: test_v1i32:59; CHECK: // %bb.0:60; CHECK-NEXT: // kill: def $d0 killed $d0 def $q061; CHECK-NEXT: fmov w0, s062; CHECK-NEXT: ret63 %b = call i32 @llvm.vector.reduce.add.v1i32(<1 x i32> %a)64 ret i32 %b65}66 67define i64 @test_v1i64(<1 x i64> %a) nounwind {68; CHECK-LABEL: test_v1i64:69; CHECK: // %bb.0:70; CHECK-NEXT: // kill: def $d0 killed $d0 def $q071; CHECK-NEXT: fmov x0, d072; CHECK-NEXT: ret73 %b = call i64 @llvm.vector.reduce.add.v1i64(<1 x i64> %a)74 ret i64 %b75}76 77define i128 @test_v1i128(<1 x i128> %a) nounwind {78; CHECK-LABEL: test_v1i128:79; CHECK: // %bb.0:80; CHECK-NEXT: ret81 %b = call i128 @llvm.vector.reduce.add.v1i128(<1 x i128> %a)82 ret i128 %b83}84 85define i8 @test_v3i8(<3 x i8> %a) nounwind {86; CHECK-LABEL: test_v3i8:87; CHECK: // %bb.0:88; CHECK-NEXT: movi v0.2d, #000000000000000089; CHECK-NEXT: mov v0.h[0], w090; CHECK-NEXT: mov v0.h[1], w191; CHECK-NEXT: mov v0.h[2], w292; CHECK-NEXT: addv h0, v0.4h93; CHECK-NEXT: fmov w0, s094; CHECK-NEXT: ret95 %b = call i8 @llvm.vector.reduce.add.v3i8(<3 x i8> %a)96 ret i8 %b97}98 99define i8 @test_v9i8(<9 x i8> %a) nounwind {100; CHECK-LABEL: test_v9i8:101; CHECK: // %bb.0:102; CHECK-NEXT: adrp x8, .LCPI8_0103; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI8_0]104; CHECK-NEXT: and v0.16b, v0.16b, v1.16b105; CHECK-NEXT: addv b0, v0.16b106; CHECK-NEXT: fmov w0, s0107; CHECK-NEXT: ret108 %b = call i8 @llvm.vector.reduce.add.v9i8(<9 x i8> %a)109 ret i8 %b110}111 112define i32 @test_v3i32(<3 x i32> %a) nounwind {113; CHECK-LABEL: test_v3i32:114; CHECK: // %bb.0:115; CHECK-NEXT: mov v0.s[3], wzr116; CHECK-NEXT: addv s0, v0.4s117; CHECK-NEXT: fmov w0, s0118; CHECK-NEXT: ret119 %b = call i32 @llvm.vector.reduce.add.v3i32(<3 x i32> %a)120 ret i32 %b121}122 123define i1 @test_v4i1(<4 x i1> %a) nounwind {124; CHECK-LABEL: test_v4i1:125; CHECK: // %bb.0:126; CHECK-NEXT: addv h0, v0.4h127; CHECK-NEXT: fmov w8, s0128; CHECK-NEXT: and w0, w8, #0x1129; CHECK-NEXT: ret130 %b = call i1 @llvm.vector.reduce.add.v4i1(<4 x i1> %a)131 ret i1 %b132}133 134define i24 @test_v4i24(<4 x i24> %a) nounwind {135; CHECK-LABEL: test_v4i24:136; CHECK: // %bb.0:137; CHECK-NEXT: addv s0, v0.4s138; CHECK-NEXT: fmov w0, s0139; CHECK-NEXT: ret140 %b = call i24 @llvm.vector.reduce.add.v4i24(<4 x i24> %a)141 ret i24 %b142}143 144define i128 @test_v2i128(<2 x i128> %a) nounwind {145; CHECK-LABEL: test_v2i128:146; CHECK: // %bb.0:147; CHECK-NEXT: adds x0, x0, x2148; CHECK-NEXT: adc x1, x1, x3149; CHECK-NEXT: ret150 %b = call i128 @llvm.vector.reduce.add.v2i128(<2 x i128> %a)151 ret i128 %b152}153 154define i32 @test_v16i32(<16 x i32> %a) nounwind {155; CHECK-LABEL: test_v16i32:156; CHECK: // %bb.0:157; CHECK-NEXT: add v1.4s, v1.4s, v3.4s158; CHECK-NEXT: add v0.4s, v0.4s, v2.4s159; CHECK-NEXT: add v0.4s, v0.4s, v1.4s160; CHECK-NEXT: addv s0, v0.4s161; CHECK-NEXT: fmov w0, s0162; CHECK-NEXT: ret163 %b = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %a)164 ret i32 %b165}166