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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK3 4declare i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %a)5declare i8 @llvm.vector.reduce.and.v1i8(<1 x i8> %a)6declare i16 @llvm.vector.reduce.and.v1i16(<1 x i16> %a)7declare i24 @llvm.vector.reduce.and.v1i24(<1 x i24> %a)8declare i32 @llvm.vector.reduce.and.v1i32(<1 x i32> %a)9declare i64 @llvm.vector.reduce.and.v1i64(<1 x i64> %a)10declare i128 @llvm.vector.reduce.and.v1i128(<1 x i128> %a)11 12declare i8 @llvm.vector.reduce.and.v3i8(<3 x i8> %a)13declare i8 @llvm.vector.reduce.and.v9i8(<9 x i8> %a)14declare i32 @llvm.vector.reduce.and.v3i32(<3 x i32> %a)15declare i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %a)16declare i24 @llvm.vector.reduce.and.v4i24(<4 x i24> %a)17declare i128 @llvm.vector.reduce.and.v2i128(<2 x i128> %a)18declare i32 @llvm.vector.reduce.and.v16i32(<16 x i32> %a)19 20define i1 @test_v1i1(<1 x i1> %a) nounwind {21; CHECK-LABEL: test_v1i1:22; CHECK: // %bb.0:23; CHECK-NEXT: and w0, w0, #0x124; CHECK-NEXT: ret25 %b = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %a)26 ret i1 %b27}28 29define i8 @test_v1i8(<1 x i8> %a) nounwind {30; CHECK-LABEL: test_v1i8:31; CHECK: // %bb.0:32; CHECK-NEXT: // kill: def $d0 killed $d0 def $q033; CHECK-NEXT: umov w0, v0.b[0]34; CHECK-NEXT: ret35 %b = call i8 @llvm.vector.reduce.and.v1i8(<1 x i8> %a)36 ret i8 %b37}38 39define i16 @test_v1i16(<1 x i16> %a) nounwind {40; CHECK-LABEL: test_v1i16:41; CHECK: // %bb.0:42; CHECK-NEXT: // kill: def $d0 killed $d0 def $q043; CHECK-NEXT: umov w0, v0.h[0]44; CHECK-NEXT: ret45 %b = call i16 @llvm.vector.reduce.and.v1i16(<1 x i16> %a)46 ret i16 %b47}48 49define i24 @test_v1i24(<1 x i24> %a) nounwind {50; CHECK-LABEL: test_v1i24:51; CHECK: // %bb.0:52; CHECK-NEXT: ret53 %b = call i24 @llvm.vector.reduce.and.v1i24(<1 x i24> %a)54 ret i24 %b55}56 57define i32 @test_v1i32(<1 x i32> %a) nounwind {58; CHECK-LABEL: test_v1i32:59; CHECK: // %bb.0:60; CHECK-NEXT: // kill: def $d0 killed $d0 def $q061; CHECK-NEXT: fmov w0, s062; CHECK-NEXT: ret63 %b = call i32 @llvm.vector.reduce.and.v1i32(<1 x i32> %a)64 ret i32 %b65}66 67define i64 @test_v1i64(<1 x i64> %a) nounwind {68; CHECK-LABEL: test_v1i64:69; CHECK: // %bb.0:70; CHECK-NEXT: // kill: def $d0 killed $d0 def $q071; CHECK-NEXT: fmov x0, d072; CHECK-NEXT: ret73 %b = call i64 @llvm.vector.reduce.and.v1i64(<1 x i64> %a)74 ret i64 %b75}76 77define i128 @test_v1i128(<1 x i128> %a) nounwind {78; CHECK-LABEL: test_v1i128:79; CHECK: // %bb.0:80; CHECK-NEXT: ret81 %b = call i128 @llvm.vector.reduce.and.v1i128(<1 x i128> %a)82 ret i128 %b83}84 85define i8 @test_v3i8(<3 x i8> %a) nounwind {86; CHECK-LABEL: test_v3i8:87; CHECK: // %bb.0:88; CHECK-NEXT: movi d0, #0xff00ff00ff00ff89; CHECK-NEXT: mov v0.h[0], w090; CHECK-NEXT: mov v0.h[1], w191; CHECK-NEXT: mov v0.h[2], w292; CHECK-NEXT: fmov x8, d093; CHECK-NEXT: and x8, x8, x8, lsr #3294; CHECK-NEXT: lsr x9, x8, #1695; CHECK-NEXT: and w0, w8, w996; CHECK-NEXT: ret97 %b = call i8 @llvm.vector.reduce.and.v3i8(<3 x i8> %a)98 ret i8 %b99}100 101define i8 @test_v9i8(<9 x i8> %a) nounwind {102; CHECK-LABEL: test_v9i8:103; CHECK: // %bb.0:104; CHECK-NEXT: movi v1.2d, #0xffffff00ffffff00105; CHECK-NEXT: fmov x8, d0106; CHECK-NEXT: orr v1.16b, v0.16b, v1.16b107; CHECK-NEXT: ext v1.16b, v1.16b, v1.16b, #8108; CHECK-NEXT: and v0.8b, v0.8b, v1.8b109; CHECK-NEXT: fmov x9, d0110; CHECK-NEXT: and x8, x9, x8, lsr #32111; CHECK-NEXT: and x8, x8, x8, lsr #16112; CHECK-NEXT: lsr x9, x8, #8113; CHECK-NEXT: and w0, w8, w9114; CHECK-NEXT: ret115 %b = call i8 @llvm.vector.reduce.and.v9i8(<9 x i8> %a)116 ret i8 %b117}118 119define i32 @test_v3i32(<3 x i32> %a) nounwind {120; CHECK-LABEL: test_v3i32:121; CHECK: // %bb.0:122; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8123; CHECK-NEXT: fmov x8, d0124; CHECK-NEXT: lsr x8, x8, #32125; CHECK-NEXT: and v1.8b, v0.8b, v1.8b126; CHECK-NEXT: fmov x9, d1127; CHECK-NEXT: and w0, w9, w8128; CHECK-NEXT: ret129 %b = call i32 @llvm.vector.reduce.and.v3i32(<3 x i32> %a)130 ret i32 %b131}132 133define i1 @test_v4i1(<4 x i1> %a) nounwind {134; CHECK-LABEL: test_v4i1:135; CHECK: // %bb.0:136; CHECK-NEXT: shl v0.4h, v0.4h, #15137; CHECK-NEXT: cmlt v0.4h, v0.4h, #0138; CHECK-NEXT: uminv h0, v0.4h139; CHECK-NEXT: fmov w8, s0140; CHECK-NEXT: and w0, w8, #0x1141; CHECK-NEXT: ret142 %b = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %a)143 ret i1 %b144}145 146define i24 @test_v4i24(<4 x i24> %a) nounwind {147; CHECK-LABEL: test_v4i24:148; CHECK: // %bb.0:149; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8150; CHECK-NEXT: and v0.8b, v0.8b, v1.8b151; CHECK-NEXT: fmov x8, d0152; CHECK-NEXT: lsr x9, x8, #32153; CHECK-NEXT: and w0, w8, w9154; CHECK-NEXT: ret155 %b = call i24 @llvm.vector.reduce.and.v4i24(<4 x i24> %a)156 ret i24 %b157}158 159define i128 @test_v2i128(<2 x i128> %a) nounwind {160; CHECK-LABEL: test_v2i128:161; CHECK: // %bb.0:162; CHECK-NEXT: and x1, x1, x3163; CHECK-NEXT: and x0, x0, x2164; CHECK-NEXT: ret165 %b = call i128 @llvm.vector.reduce.and.v2i128(<2 x i128> %a)166 ret i128 %b167}168 169define i32 @test_v16i32(<16 x i32> %a) nounwind {170; CHECK-LABEL: test_v16i32:171; CHECK: // %bb.0:172; CHECK-NEXT: and v1.16b, v1.16b, v3.16b173; CHECK-NEXT: and v0.16b, v0.16b, v2.16b174; CHECK-NEXT: and v0.16b, v0.16b, v1.16b175; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8176; CHECK-NEXT: and v0.8b, v0.8b, v1.8b177; CHECK-NEXT: fmov x8, d0178; CHECK-NEXT: lsr x9, x8, #32179; CHECK-NEXT: and w0, w8, w9180; CHECK-NEXT: ret181 %b = call i32 @llvm.vector.reduce.and.v16i32(<16 x i32> %a)182 ret i32 %b183}184