1203 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=aarch64 -verify-machineinstrs %s -o - | FileCheck %s3 4define zeroext i16 @and_sext_v8i8_i16(<8 x i8> %x) {5; CHECK-LABEL: and_sext_v8i8_i16:6; CHECK: // %bb.0: // %entry7; CHECK-NEXT: fmov x8, d08; CHECK-NEXT: and x8, x8, x8, lsr #329; CHECK-NEXT: lsr x9, x8, #1610; CHECK-NEXT: and w8, w8, w911; CHECK-NEXT: and w8, w8, w8, lsr #812; CHECK-NEXT: sxtb w8, w813; CHECK-NEXT: and w0, w8, #0xffff14; CHECK-NEXT: ret15entry:16 %y = sext <8 x i8> %x to <8 x i16>17 %z = call i16 @llvm.vector.reduce.and.v8i16(<8 x i16> %y)18 ret i16 %z19}20 21define zeroext i16 @and_zext_v8i8_i16(<8 x i8> %x) {22; CHECK-LABEL: and_zext_v8i8_i16:23; CHECK: // %bb.0: // %entry24; CHECK-NEXT: fmov x8, d025; CHECK-NEXT: and x8, x8, x8, lsr #3226; CHECK-NEXT: lsr x9, x8, #1627; CHECK-NEXT: and w8, w8, w928; CHECK-NEXT: and w8, w8, w8, lsr #829; CHECK-NEXT: and w0, w8, #0xff30; CHECK-NEXT: ret31entry:32 %y = zext <8 x i8> %x to <8 x i16>33 %z = call i16 @llvm.vector.reduce.and.v8i16(<8 x i16> %y)34 ret i16 %z35}36 37define zeroext i16 @and_sext_v16i8_i16(<16 x i8> %x) {38; CHECK-LABEL: and_sext_v16i8_i16:39; CHECK: // %bb.0: // %entry40; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #841; CHECK-NEXT: and v0.8b, v0.8b, v1.8b42; CHECK-NEXT: fmov x8, d043; CHECK-NEXT: and x8, x8, x8, lsr #3244; CHECK-NEXT: lsr x9, x8, #1645; CHECK-NEXT: and w8, w8, w946; CHECK-NEXT: and w8, w8, w8, lsr #847; CHECK-NEXT: sxtb w8, w848; CHECK-NEXT: and w0, w8, #0xffff49; CHECK-NEXT: ret50entry:51 %y = sext <16 x i8> %x to <16 x i16>52 %z = call i16 @llvm.vector.reduce.and.v16i16(<16 x i16> %y)53 ret i16 %z54}55 56define zeroext i16 @and_zext_v16i8_i16(<16 x i8> %x) {57; CHECK-LABEL: and_zext_v16i8_i16:58; CHECK: // %bb.0: // %entry59; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #860; CHECK-NEXT: and v0.8b, v0.8b, v1.8b61; CHECK-NEXT: fmov x8, d062; CHECK-NEXT: and x8, x8, x8, lsr #3263; CHECK-NEXT: lsr x9, x8, #1664; CHECK-NEXT: and w8, w8, w965; CHECK-NEXT: and w8, w8, w8, lsr #866; CHECK-NEXT: and w0, w8, #0xff67; CHECK-NEXT: ret68entry:69 %y = zext <16 x i8> %x to <16 x i16>70 %z = call i16 @llvm.vector.reduce.and.v16i16(<16 x i16> %y)71 ret i16 %z72}73 74define i32 @and_sext_v8i8_i32(<8 x i8> %x) {75; CHECK-LABEL: and_sext_v8i8_i32:76; CHECK: // %bb.0: // %entry77; CHECK-NEXT: fmov x8, d078; CHECK-NEXT: and x8, x8, x8, lsr #3279; CHECK-NEXT: lsr x9, x8, #1680; CHECK-NEXT: and w8, w8, w981; CHECK-NEXT: and w8, w8, w8, lsr #882; CHECK-NEXT: sxtb w0, w883; CHECK-NEXT: ret84entry:85 %y = sext <8 x i8> %x to <8 x i32>86 %z = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> %y)87 ret i32 %z88}89 90define i32 @and_zext_v8i8_i32(<8 x i8> %x) {91; CHECK-LABEL: and_zext_v8i8_i32:92; CHECK: // %bb.0: // %entry93; CHECK-NEXT: fmov x8, d094; CHECK-NEXT: and x8, x8, x8, lsr #3295; CHECK-NEXT: lsr x9, x8, #1696; CHECK-NEXT: and w8, w8, w997; CHECK-NEXT: and w8, w8, w8, lsr #898; CHECK-NEXT: and w0, w8, #0xff99; CHECK-NEXT: ret100entry:101 %y = zext <8 x i8> %x to <8 x i32>102 %z = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> %y)103 ret i32 %z104}105 106define i32 @and_sext_v16i8_i32(<16 x i8> %x) {107; CHECK-LABEL: and_sext_v16i8_i32:108; CHECK: // %bb.0: // %entry109; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8110; CHECK-NEXT: and v0.8b, v0.8b, v1.8b111; CHECK-NEXT: fmov x8, d0112; CHECK-NEXT: and x8, x8, x8, lsr #32113; CHECK-NEXT: lsr x9, x8, #16114; CHECK-NEXT: and w8, w8, w9115; CHECK-NEXT: and w8, w8, w8, lsr #8116; CHECK-NEXT: sxtb w0, w8117; CHECK-NEXT: ret118entry:119 %y = sext <16 x i8> %x to <16 x i32>120 %z = call i32 @llvm.vector.reduce.and.v16i32(<16 x i32> %y)121 ret i32 %z122}123 124define i32 @and_zext_v16i8_i32(<16 x i8> %x) {125; CHECK-LABEL: and_zext_v16i8_i32:126; CHECK: // %bb.0: // %entry127; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8128; CHECK-NEXT: and v0.8b, v0.8b, v1.8b129; CHECK-NEXT: fmov x8, d0130; CHECK-NEXT: and x8, x8, x8, lsr #32131; CHECK-NEXT: lsr x9, x8, #16132; CHECK-NEXT: and w8, w8, w9133; CHECK-NEXT: and w8, w8, w8, lsr #8134; CHECK-NEXT: and w0, w8, #0xff135; CHECK-NEXT: ret136entry:137 %y = zext <16 x i8> %x to <16 x i32>138 %z = call i32 @llvm.vector.reduce.and.v16i32(<16 x i32> %y)139 ret i32 %z140}141 142define i64 @and_sext_v8i8_i64(<8 x i8> %x) {143; CHECK-LABEL: and_sext_v8i8_i64:144; CHECK: // %bb.0: // %entry145; CHECK-NEXT: fmov x8, d0146; CHECK-NEXT: and x8, x8, x8, lsr #32147; CHECK-NEXT: lsr x9, x8, #16148; CHECK-NEXT: and w8, w8, w9149; CHECK-NEXT: and w8, w8, w8, lsr #8150; CHECK-NEXT: sxtb x0, w8151; CHECK-NEXT: ret152entry:153 %y = sext <8 x i8> %x to <8 x i64>154 %z = call i64 @llvm.vector.reduce.and.v8i64(<8 x i64> %y)155 ret i64 %z156}157 158define i64 @and_zext_v8i8_i64(<8 x i8> %x) {159; CHECK-LABEL: and_zext_v8i8_i64:160; CHECK: // %bb.0: // %entry161; CHECK-NEXT: fmov x8, d0162; CHECK-NEXT: and x8, x8, x8, lsr #32163; CHECK-NEXT: lsr x9, x8, #16164; CHECK-NEXT: and w8, w8, w9165; CHECK-NEXT: and w8, w8, w8, lsr #8166; CHECK-NEXT: and x0, x8, #0xff167; CHECK-NEXT: ret168entry:169 %y = zext <8 x i8> %x to <8 x i64>170 %z = call i64 @llvm.vector.reduce.and.v8i64(<8 x i64> %y)171 ret i64 %z172}173 174define i64 @and_sext_v16i8_i64(<16 x i8> %x) {175; CHECK-LABEL: and_sext_v16i8_i64:176; CHECK: // %bb.0: // %entry177; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8178; CHECK-NEXT: and v0.8b, v0.8b, v1.8b179; CHECK-NEXT: fmov x8, d0180; CHECK-NEXT: and x8, x8, x8, lsr #32181; CHECK-NEXT: lsr x9, x8, #16182; CHECK-NEXT: and w8, w8, w9183; CHECK-NEXT: and w8, w8, w8, lsr #8184; CHECK-NEXT: sxtb x0, w8185; CHECK-NEXT: ret186entry:187 %y = sext <16 x i8> %x to <16 x i64>188 %z = call i64 @llvm.vector.reduce.and.v16i64(<16 x i64> %y)189 ret i64 %z190}191 192define i64 @and_zext_v16i8_i64(<16 x i8> %x) {193; CHECK-LABEL: and_zext_v16i8_i64:194; CHECK: // %bb.0: // %entry195; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8196; CHECK-NEXT: and v0.8b, v0.8b, v1.8b197; CHECK-NEXT: fmov x8, d0198; CHECK-NEXT: and x8, x8, x8, lsr #32199; CHECK-NEXT: lsr x9, x8, #16200; CHECK-NEXT: and w8, w8, w9201; CHECK-NEXT: and w8, w8, w8, lsr #8202; CHECK-NEXT: and x0, x8, #0xff203; CHECK-NEXT: ret204entry:205 %y = zext <16 x i8> %x to <16 x i64>206 %z = call i64 @llvm.vector.reduce.and.v16i64(<16 x i64> %y)207 ret i64 %z208}209 210define i32 @and_sext_v4i16_i32(<4 x i16> %x) {211; CHECK-LABEL: and_sext_v4i16_i32:212; CHECK: // %bb.0: // %entry213; CHECK-NEXT: fmov x8, d0214; CHECK-NEXT: lsr x9, x8, #32215; CHECK-NEXT: and w8, w8, w9216; CHECK-NEXT: and w8, w8, w8, lsr #16217; CHECK-NEXT: sxth w0, w8218; CHECK-NEXT: ret219entry:220 %y = sext <4 x i16> %x to <4 x i32>221 %z = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %y)222 ret i32 %z223}224 225define i32 @and_zext_v4i16_i32(<4 x i16> %x) {226; CHECK-LABEL: and_zext_v4i16_i32:227; CHECK: // %bb.0: // %entry228; CHECK-NEXT: fmov x8, d0229; CHECK-NEXT: and x8, x8, x8, lsr #32230; CHECK-NEXT: lsr x9, x8, #16231; CHECK-NEXT: and w0, w8, w9232; CHECK-NEXT: ret233entry:234 %y = zext <4 x i16> %x to <4 x i32>235 %z = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %y)236 ret i32 %z237}238 239define i32 @and_sext_v8i16_i32(<8 x i16> %x) {240; CHECK-LABEL: and_sext_v8i16_i32:241; CHECK: // %bb.0: // %entry242; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8243; CHECK-NEXT: and v0.8b, v0.8b, v1.8b244; CHECK-NEXT: fmov x8, d0245; CHECK-NEXT: lsr x9, x8, #32246; CHECK-NEXT: and w8, w8, w9247; CHECK-NEXT: and w8, w8, w8, lsr #16248; CHECK-NEXT: sxth w0, w8249; CHECK-NEXT: ret250entry:251 %y = sext <8 x i16> %x to <8 x i32>252 %z = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> %y)253 ret i32 %z254}255 256define i32 @and_zext_v8i16_i32(<8 x i16> %x) {257; CHECK-LABEL: and_zext_v8i16_i32:258; CHECK: // %bb.0: // %entry259; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8260; CHECK-NEXT: and v0.8b, v0.8b, v1.8b261; CHECK-NEXT: fmov x8, d0262; CHECK-NEXT: and x8, x8, x8, lsr #32263; CHECK-NEXT: lsr x9, x8, #16264; CHECK-NEXT: and w0, w8, w9265; CHECK-NEXT: ret266entry:267 %y = zext <8 x i16> %x to <8 x i32>268 %z = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> %y)269 ret i32 %z270}271 272define i64 @and_sext_v4i16_i64(<4 x i16> %x) {273; CHECK-LABEL: and_sext_v4i16_i64:274; CHECK: // %bb.0: // %entry275; CHECK-NEXT: fmov x8, d0276; CHECK-NEXT: lsr x9, x8, #32277; CHECK-NEXT: and w8, w8, w9278; CHECK-NEXT: and w8, w8, w8, lsr #16279; CHECK-NEXT: sxth x0, w8280; CHECK-NEXT: ret281entry:282 %y = sext <4 x i16> %x to <4 x i64>283 %z = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> %y)284 ret i64 %z285}286 287define i64 @and_zext_v4i16_i64(<4 x i16> %x) {288; CHECK-LABEL: and_zext_v4i16_i64:289; CHECK: // %bb.0: // %entry290; CHECK-NEXT: fmov x8, d0291; CHECK-NEXT: and x8, x8, x8, lsr #32292; CHECK-NEXT: lsr x9, x8, #16293; CHECK-NEXT: and w0, w8, w9294; CHECK-NEXT: ret295entry:296 %y = zext <4 x i16> %x to <4 x i64>297 %z = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> %y)298 ret i64 %z299}300 301define i64 @and_sext_v8i16_i64(<8 x i16> %x) {302; CHECK-LABEL: and_sext_v8i16_i64:303; CHECK: // %bb.0: // %entry304; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8305; CHECK-NEXT: and v0.8b, v0.8b, v1.8b306; CHECK-NEXT: fmov x8, d0307; CHECK-NEXT: lsr x9, x8, #32308; CHECK-NEXT: and w8, w8, w9309; CHECK-NEXT: and w8, w8, w8, lsr #16310; CHECK-NEXT: sxth x0, w8311; CHECK-NEXT: ret312entry:313 %y = sext <8 x i16> %x to <8 x i64>314 %z = call i64 @llvm.vector.reduce.and.v8i64(<8 x i64> %y)315 ret i64 %z316}317 318define i64 @and_zext_v8i16_i64(<8 x i16> %x) {319; CHECK-LABEL: and_zext_v8i16_i64:320; CHECK: // %bb.0: // %entry321; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8322; CHECK-NEXT: and v0.8b, v0.8b, v1.8b323; CHECK-NEXT: fmov x8, d0324; CHECK-NEXT: and x8, x8, x8, lsr #32325; CHECK-NEXT: lsr x9, x8, #16326; CHECK-NEXT: and w0, w8, w9327; CHECK-NEXT: ret328entry:329 %y = zext <8 x i16> %x to <8 x i64>330 %z = call i64 @llvm.vector.reduce.and.v8i64(<8 x i64> %y)331 ret i64 %z332}333 334define i64 @and_sext_v2i32_i64(<2 x i32> %x) {335; CHECK-LABEL: and_sext_v2i32_i64:336; CHECK: // %bb.0: // %entry337; CHECK-NEXT: fmov x8, d0338; CHECK-NEXT: lsr x9, x8, #32339; CHECK-NEXT: and w8, w8, w9340; CHECK-NEXT: sxtw x0, w8341; CHECK-NEXT: ret342entry:343 %y = sext <2 x i32> %x to <2 x i64>344 %z = call i64 @llvm.vector.reduce.and.v2i64(<2 x i64> %y)345 ret i64 %z346}347 348define i64 @and_zext_v2i32_i64(<2 x i32> %x) {349; CHECK-LABEL: and_zext_v2i32_i64:350; CHECK: // %bb.0: // %entry351; CHECK-NEXT: fmov x8, d0352; CHECK-NEXT: lsr x9, x8, #32353; CHECK-NEXT: and w0, w8, w9354; CHECK-NEXT: ret355entry:356 %y = zext <2 x i32> %x to <2 x i64>357 %z = call i64 @llvm.vector.reduce.and.v2i64(<2 x i64> %y)358 ret i64 %z359}360 361define i64 @and_sext_v4i32_i64(<4 x i32> %x) {362; CHECK-LABEL: and_sext_v4i32_i64:363; CHECK: // %bb.0: // %entry364; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8365; CHECK-NEXT: and v0.8b, v0.8b, v1.8b366; CHECK-NEXT: fmov x8, d0367; CHECK-NEXT: lsr x9, x8, #32368; CHECK-NEXT: and w8, w8, w9369; CHECK-NEXT: sxtw x0, w8370; CHECK-NEXT: ret371entry:372 %y = sext <4 x i32> %x to <4 x i64>373 %z = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> %y)374 ret i64 %z375}376 377define i64 @and_zext_v4i32_i64(<4 x i32> %x) {378; CHECK-LABEL: and_zext_v4i32_i64:379; CHECK: // %bb.0: // %entry380; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8381; CHECK-NEXT: and v0.8b, v0.8b, v1.8b382; CHECK-NEXT: fmov x8, d0383; CHECK-NEXT: lsr x9, x8, #32384; CHECK-NEXT: and w0, w8, w9385; CHECK-NEXT: ret386entry:387 %y = zext <4 x i32> %x to <4 x i64>388 %z = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> %y)389 ret i64 %z390}391 392define zeroext i16 @or_sext_v8i8_i16(<8 x i8> %x) {393; CHECK-LABEL: or_sext_v8i8_i16:394; CHECK: // %bb.0: // %entry395; CHECK-NEXT: fmov x8, d0396; CHECK-NEXT: orr x8, x8, x8, lsr #32397; CHECK-NEXT: lsr x9, x8, #16398; CHECK-NEXT: orr w8, w8, w9399; CHECK-NEXT: orr w8, w8, w8, lsr #8400; CHECK-NEXT: sxtb w8, w8401; CHECK-NEXT: and w0, w8, #0xffff402; CHECK-NEXT: ret403entry:404 %y = sext <8 x i8> %x to <8 x i16>405 %z = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> %y)406 ret i16 %z407}408 409define zeroext i16 @or_zext_v8i8_i16(<8 x i8> %x) {410; CHECK-LABEL: or_zext_v8i8_i16:411; CHECK: // %bb.0: // %entry412; CHECK-NEXT: fmov x8, d0413; CHECK-NEXT: orr x8, x8, x8, lsr #32414; CHECK-NEXT: lsr x9, x8, #16415; CHECK-NEXT: orr w8, w8, w9416; CHECK-NEXT: orr w8, w8, w8, lsr #8417; CHECK-NEXT: and w0, w8, #0xff418; CHECK-NEXT: ret419entry:420 %y = zext <8 x i8> %x to <8 x i16>421 %z = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> %y)422 ret i16 %z423}424 425define zeroext i16 @or_sext_v16i8_i16(<16 x i8> %x) {426; CHECK-LABEL: or_sext_v16i8_i16:427; CHECK: // %bb.0: // %entry428; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8429; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b430; CHECK-NEXT: fmov x8, d0431; CHECK-NEXT: orr x8, x8, x8, lsr #32432; CHECK-NEXT: lsr x9, x8, #16433; CHECK-NEXT: orr w8, w8, w9434; CHECK-NEXT: orr w8, w8, w8, lsr #8435; CHECK-NEXT: sxtb w8, w8436; CHECK-NEXT: and w0, w8, #0xffff437; CHECK-NEXT: ret438entry:439 %y = sext <16 x i8> %x to <16 x i16>440 %z = call i16 @llvm.vector.reduce.or.v16i16(<16 x i16> %y)441 ret i16 %z442}443 444define zeroext i16 @or_zext_v16i8_i16(<16 x i8> %x) {445; CHECK-LABEL: or_zext_v16i8_i16:446; CHECK: // %bb.0: // %entry447; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8448; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b449; CHECK-NEXT: fmov x8, d0450; CHECK-NEXT: orr x8, x8, x8, lsr #32451; CHECK-NEXT: lsr x9, x8, #16452; CHECK-NEXT: orr w8, w8, w9453; CHECK-NEXT: orr w8, w8, w8, lsr #8454; CHECK-NEXT: and w0, w8, #0xff455; CHECK-NEXT: ret456entry:457 %y = zext <16 x i8> %x to <16 x i16>458 %z = call i16 @llvm.vector.reduce.or.v16i16(<16 x i16> %y)459 ret i16 %z460}461 462define i32 @or_sext_v8i8_i32(<8 x i8> %x) {463; CHECK-LABEL: or_sext_v8i8_i32:464; CHECK: // %bb.0: // %entry465; CHECK-NEXT: fmov x8, d0466; CHECK-NEXT: orr x8, x8, x8, lsr #32467; CHECK-NEXT: lsr x9, x8, #16468; CHECK-NEXT: orr w8, w8, w9469; CHECK-NEXT: orr w8, w8, w8, lsr #8470; CHECK-NEXT: sxtb w0, w8471; CHECK-NEXT: ret472entry:473 %y = sext <8 x i8> %x to <8 x i32>474 %z = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> %y)475 ret i32 %z476}477 478define i32 @or_zext_v8i8_i32(<8 x i8> %x) {479; CHECK-LABEL: or_zext_v8i8_i32:480; CHECK: // %bb.0: // %entry481; CHECK-NEXT: fmov x8, d0482; CHECK-NEXT: orr x8, x8, x8, lsr #32483; CHECK-NEXT: lsr x9, x8, #16484; CHECK-NEXT: orr w8, w8, w9485; CHECK-NEXT: orr w8, w8, w8, lsr #8486; CHECK-NEXT: and w0, w8, #0xff487; CHECK-NEXT: ret488entry:489 %y = zext <8 x i8> %x to <8 x i32>490 %z = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> %y)491 ret i32 %z492}493 494define i32 @or_sext_v16i8_i32(<16 x i8> %x) {495; CHECK-LABEL: or_sext_v16i8_i32:496; CHECK: // %bb.0: // %entry497; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8498; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b499; CHECK-NEXT: fmov x8, d0500; CHECK-NEXT: orr x8, x8, x8, lsr #32501; CHECK-NEXT: lsr x9, x8, #16502; CHECK-NEXT: orr w8, w8, w9503; CHECK-NEXT: orr w8, w8, w8, lsr #8504; CHECK-NEXT: sxtb w0, w8505; CHECK-NEXT: ret506entry:507 %y = sext <16 x i8> %x to <16 x i32>508 %z = call i32 @llvm.vector.reduce.or.v16i32(<16 x i32> %y)509 ret i32 %z510}511 512define i32 @or_zext_v16i8_i32(<16 x i8> %x) {513; CHECK-LABEL: or_zext_v16i8_i32:514; CHECK: // %bb.0: // %entry515; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8516; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b517; CHECK-NEXT: fmov x8, d0518; CHECK-NEXT: orr x8, x8, x8, lsr #32519; CHECK-NEXT: lsr x9, x8, #16520; CHECK-NEXT: orr w8, w8, w9521; CHECK-NEXT: orr w8, w8, w8, lsr #8522; CHECK-NEXT: and w0, w8, #0xff523; CHECK-NEXT: ret524entry:525 %y = zext <16 x i8> %x to <16 x i32>526 %z = call i32 @llvm.vector.reduce.or.v16i32(<16 x i32> %y)527 ret i32 %z528}529 530define i64 @or_sext_v8i8_i64(<8 x i8> %x) {531; CHECK-LABEL: or_sext_v8i8_i64:532; CHECK: // %bb.0: // %entry533; CHECK-NEXT: fmov x8, d0534; CHECK-NEXT: orr x8, x8, x8, lsr #32535; CHECK-NEXT: lsr x9, x8, #16536; CHECK-NEXT: orr w8, w8, w9537; CHECK-NEXT: orr w8, w8, w8, lsr #8538; CHECK-NEXT: sxtb x0, w8539; CHECK-NEXT: ret540entry:541 %y = sext <8 x i8> %x to <8 x i64>542 %z = call i64 @llvm.vector.reduce.or.v8i64(<8 x i64> %y)543 ret i64 %z544}545 546define i64 @or_zext_v8i8_i64(<8 x i8> %x) {547; CHECK-LABEL: or_zext_v8i8_i64:548; CHECK: // %bb.0: // %entry549; CHECK-NEXT: fmov x8, d0550; CHECK-NEXT: orr x8, x8, x8, lsr #32551; CHECK-NEXT: lsr x9, x8, #16552; CHECK-NEXT: orr w8, w8, w9553; CHECK-NEXT: orr w8, w8, w8, lsr #8554; CHECK-NEXT: and x0, x8, #0xff555; CHECK-NEXT: ret556entry:557 %y = zext <8 x i8> %x to <8 x i64>558 %z = call i64 @llvm.vector.reduce.or.v8i64(<8 x i64> %y)559 ret i64 %z560}561 562define i64 @or_sext_v16i8_i64(<16 x i8> %x) {563; CHECK-LABEL: or_sext_v16i8_i64:564; CHECK: // %bb.0: // %entry565; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8566; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b567; CHECK-NEXT: fmov x8, d0568; CHECK-NEXT: orr x8, x8, x8, lsr #32569; CHECK-NEXT: lsr x9, x8, #16570; CHECK-NEXT: orr w8, w8, w9571; CHECK-NEXT: orr w8, w8, w8, lsr #8572; CHECK-NEXT: sxtb x0, w8573; CHECK-NEXT: ret574entry:575 %y = sext <16 x i8> %x to <16 x i64>576 %z = call i64 @llvm.vector.reduce.or.v16i64(<16 x i64> %y)577 ret i64 %z578}579 580define i64 @or_zext_v16i8_i64(<16 x i8> %x) {581; CHECK-LABEL: or_zext_v16i8_i64:582; CHECK: // %bb.0: // %entry583; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8584; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b585; CHECK-NEXT: fmov x8, d0586; CHECK-NEXT: orr x8, x8, x8, lsr #32587; CHECK-NEXT: lsr x9, x8, #16588; CHECK-NEXT: orr w8, w8, w9589; CHECK-NEXT: orr w8, w8, w8, lsr #8590; CHECK-NEXT: and x0, x8, #0xff591; CHECK-NEXT: ret592entry:593 %y = zext <16 x i8> %x to <16 x i64>594 %z = call i64 @llvm.vector.reduce.or.v16i64(<16 x i64> %y)595 ret i64 %z596}597 598define i32 @or_sext_v4i16_i32(<4 x i16> %x) {599; CHECK-LABEL: or_sext_v4i16_i32:600; CHECK: // %bb.0: // %entry601; CHECK-NEXT: fmov x8, d0602; CHECK-NEXT: lsr x9, x8, #32603; CHECK-NEXT: orr w8, w8, w9604; CHECK-NEXT: orr w8, w8, w8, lsr #16605; CHECK-NEXT: sxth w0, w8606; CHECK-NEXT: ret607entry:608 %y = sext <4 x i16> %x to <4 x i32>609 %z = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %y)610 ret i32 %z611}612 613define i32 @or_zext_v4i16_i32(<4 x i16> %x) {614; CHECK-LABEL: or_zext_v4i16_i32:615; CHECK: // %bb.0: // %entry616; CHECK-NEXT: fmov x8, d0617; CHECK-NEXT: lsr x9, x8, #32618; CHECK-NEXT: orr w8, w8, w9619; CHECK-NEXT: orr w8, w8, w8, lsr #16620; CHECK-NEXT: and w0, w8, #0xffff621; CHECK-NEXT: ret622entry:623 %y = zext <4 x i16> %x to <4 x i32>624 %z = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %y)625 ret i32 %z626}627 628define i32 @or_sext_v8i16_i32(<8 x i16> %x) {629; CHECK-LABEL: or_sext_v8i16_i32:630; CHECK: // %bb.0: // %entry631; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8632; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b633; CHECK-NEXT: fmov x8, d0634; CHECK-NEXT: lsr x9, x8, #32635; CHECK-NEXT: orr w8, w8, w9636; CHECK-NEXT: orr w8, w8, w8, lsr #16637; CHECK-NEXT: sxth w0, w8638; CHECK-NEXT: ret639entry:640 %y = sext <8 x i16> %x to <8 x i32>641 %z = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> %y)642 ret i32 %z643}644 645define i32 @or_zext_v8i16_i32(<8 x i16> %x) {646; CHECK-LABEL: or_zext_v8i16_i32:647; CHECK: // %bb.0: // %entry648; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8649; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b650; CHECK-NEXT: fmov x8, d0651; CHECK-NEXT: lsr x9, x8, #32652; CHECK-NEXT: orr w8, w8, w9653; CHECK-NEXT: orr w8, w8, w8, lsr #16654; CHECK-NEXT: and w0, w8, #0xffff655; CHECK-NEXT: ret656entry:657 %y = zext <8 x i16> %x to <8 x i32>658 %z = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> %y)659 ret i32 %z660}661 662define i64 @or_sext_v4i16_i64(<4 x i16> %x) {663; CHECK-LABEL: or_sext_v4i16_i64:664; CHECK: // %bb.0: // %entry665; CHECK-NEXT: fmov x8, d0666; CHECK-NEXT: lsr x9, x8, #32667; CHECK-NEXT: orr w8, w8, w9668; CHECK-NEXT: orr w8, w8, w8, lsr #16669; CHECK-NEXT: sxth x0, w8670; CHECK-NEXT: ret671entry:672 %y = sext <4 x i16> %x to <4 x i64>673 %z = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> %y)674 ret i64 %z675}676 677define i64 @or_zext_v4i16_i64(<4 x i16> %x) {678; CHECK-LABEL: or_zext_v4i16_i64:679; CHECK: // %bb.0: // %entry680; CHECK-NEXT: fmov x8, d0681; CHECK-NEXT: lsr x9, x8, #32682; CHECK-NEXT: orr w8, w8, w9683; CHECK-NEXT: orr w8, w8, w8, lsr #16684; CHECK-NEXT: and x0, x8, #0xffff685; CHECK-NEXT: ret686entry:687 %y = zext <4 x i16> %x to <4 x i64>688 %z = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> %y)689 ret i64 %z690}691 692define i64 @or_sext_v8i16_i64(<8 x i16> %x) {693; CHECK-LABEL: or_sext_v8i16_i64:694; CHECK: // %bb.0: // %entry695; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8696; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b697; CHECK-NEXT: fmov x8, d0698; CHECK-NEXT: lsr x9, x8, #32699; CHECK-NEXT: orr w8, w8, w9700; CHECK-NEXT: orr w8, w8, w8, lsr #16701; CHECK-NEXT: sxth x0, w8702; CHECK-NEXT: ret703entry:704 %y = sext <8 x i16> %x to <8 x i64>705 %z = call i64 @llvm.vector.reduce.or.v8i64(<8 x i64> %y)706 ret i64 %z707}708 709define i64 @or_zext_v8i16_i64(<8 x i16> %x) {710; CHECK-LABEL: or_zext_v8i16_i64:711; CHECK: // %bb.0: // %entry712; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8713; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b714; CHECK-NEXT: fmov x8, d0715; CHECK-NEXT: lsr x9, x8, #32716; CHECK-NEXT: orr w8, w8, w9717; CHECK-NEXT: orr w8, w8, w8, lsr #16718; CHECK-NEXT: and x0, x8, #0xffff719; CHECK-NEXT: ret720entry:721 %y = zext <8 x i16> %x to <8 x i64>722 %z = call i64 @llvm.vector.reduce.or.v8i64(<8 x i64> %y)723 ret i64 %z724}725 726define i64 @or_sext_v2i32_i64(<2 x i32> %x) {727; CHECK-LABEL: or_sext_v2i32_i64:728; CHECK: // %bb.0: // %entry729; CHECK-NEXT: fmov x8, d0730; CHECK-NEXT: lsr x9, x8, #32731; CHECK-NEXT: orr w8, w8, w9732; CHECK-NEXT: sxtw x0, w8733; CHECK-NEXT: ret734entry:735 %y = sext <2 x i32> %x to <2 x i64>736 %z = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> %y)737 ret i64 %z738}739 740define i64 @or_zext_v2i32_i64(<2 x i32> %x) {741; CHECK-LABEL: or_zext_v2i32_i64:742; CHECK: // %bb.0: // %entry743; CHECK-NEXT: fmov x8, d0744; CHECK-NEXT: lsr x9, x8, #32745; CHECK-NEXT: orr w0, w8, w9746; CHECK-NEXT: ret747entry:748 %y = zext <2 x i32> %x to <2 x i64>749 %z = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> %y)750 ret i64 %z751}752 753define i64 @or_sext_v4i32_i64(<4 x i32> %x) {754; CHECK-LABEL: or_sext_v4i32_i64:755; CHECK: // %bb.0: // %entry756; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8757; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b758; CHECK-NEXT: fmov x8, d0759; CHECK-NEXT: lsr x9, x8, #32760; CHECK-NEXT: orr w8, w8, w9761; CHECK-NEXT: sxtw x0, w8762; CHECK-NEXT: ret763entry:764 %y = sext <4 x i32> %x to <4 x i64>765 %z = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> %y)766 ret i64 %z767}768 769define i64 @or_zext_v4i32_i64(<4 x i32> %x) {770; CHECK-LABEL: or_zext_v4i32_i64:771; CHECK: // %bb.0: // %entry772; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8773; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b774; CHECK-NEXT: fmov x8, d0775; CHECK-NEXT: lsr x9, x8, #32776; CHECK-NEXT: orr w0, w8, w9777; CHECK-NEXT: ret778entry:779 %y = zext <4 x i32> %x to <4 x i64>780 %z = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> %y)781 ret i64 %z782}783 784define zeroext i16 @xor_sext_v8i8_i16(<8 x i8> %x) {785; CHECK-LABEL: xor_sext_v8i8_i16:786; CHECK: // %bb.0: // %entry787; CHECK-NEXT: fmov x8, d0788; CHECK-NEXT: eor x8, x8, x8, lsr #32789; CHECK-NEXT: lsr x9, x8, #16790; CHECK-NEXT: eor w8, w8, w9791; CHECK-NEXT: eor w8, w8, w8, lsr #8792; CHECK-NEXT: sxtb w8, w8793; CHECK-NEXT: and w0, w8, #0xffff794; CHECK-NEXT: ret795entry:796 %y = sext <8 x i8> %x to <8 x i16>797 %z = call i16 @llvm.vector.reduce.xor.v8i16(<8 x i16> %y)798 ret i16 %z799}800 801define zeroext i16 @xor_zext_v8i8_i16(<8 x i8> %x) {802; CHECK-LABEL: xor_zext_v8i8_i16:803; CHECK: // %bb.0: // %entry804; CHECK-NEXT: fmov x8, d0805; CHECK-NEXT: eor x8, x8, x8, lsr #32806; CHECK-NEXT: lsr x9, x8, #16807; CHECK-NEXT: eor w8, w8, w9808; CHECK-NEXT: eor w8, w8, w8, lsr #8809; CHECK-NEXT: and w0, w8, #0xff810; CHECK-NEXT: ret811entry:812 %y = zext <8 x i8> %x to <8 x i16>813 %z = call i16 @llvm.vector.reduce.xor.v8i16(<8 x i16> %y)814 ret i16 %z815}816 817define zeroext i16 @xor_sext_v16i8_i16(<16 x i8> %x) {818; CHECK-LABEL: xor_sext_v16i8_i16:819; CHECK: // %bb.0: // %entry820; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8821; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b822; CHECK-NEXT: fmov x8, d0823; CHECK-NEXT: eor x8, x8, x8, lsr #32824; CHECK-NEXT: lsr x9, x8, #16825; CHECK-NEXT: eor w8, w8, w9826; CHECK-NEXT: eor w8, w8, w8, lsr #8827; CHECK-NEXT: sxtb w8, w8828; CHECK-NEXT: and w0, w8, #0xffff829; CHECK-NEXT: ret830entry:831 %y = sext <16 x i8> %x to <16 x i16>832 %z = call i16 @llvm.vector.reduce.xor.v16i16(<16 x i16> %y)833 ret i16 %z834}835 836define zeroext i16 @xor_zext_v16i8_i16(<16 x i8> %x) {837; CHECK-LABEL: xor_zext_v16i8_i16:838; CHECK: // %bb.0: // %entry839; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8840; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b841; CHECK-NEXT: fmov x8, d0842; CHECK-NEXT: eor x8, x8, x8, lsr #32843; CHECK-NEXT: lsr x9, x8, #16844; CHECK-NEXT: eor w8, w8, w9845; CHECK-NEXT: eor w8, w8, w8, lsr #8846; CHECK-NEXT: and w0, w8, #0xff847; CHECK-NEXT: ret848entry:849 %y = zext <16 x i8> %x to <16 x i16>850 %z = call i16 @llvm.vector.reduce.xor.v16i16(<16 x i16> %y)851 ret i16 %z852}853 854define i32 @xor_sext_v8i8_i32(<8 x i8> %x) {855; CHECK-LABEL: xor_sext_v8i8_i32:856; CHECK: // %bb.0: // %entry857; CHECK-NEXT: fmov x8, d0858; CHECK-NEXT: eor x8, x8, x8, lsr #32859; CHECK-NEXT: lsr x9, x8, #16860; CHECK-NEXT: eor w8, w8, w9861; CHECK-NEXT: eor w8, w8, w8, lsr #8862; CHECK-NEXT: sxtb w0, w8863; CHECK-NEXT: ret864entry:865 %y = sext <8 x i8> %x to <8 x i32>866 %z = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> %y)867 ret i32 %z868}869 870define i32 @xor_zext_v8i8_i32(<8 x i8> %x) {871; CHECK-LABEL: xor_zext_v8i8_i32:872; CHECK: // %bb.0: // %entry873; CHECK-NEXT: fmov x8, d0874; CHECK-NEXT: eor x8, x8, x8, lsr #32875; CHECK-NEXT: lsr x9, x8, #16876; CHECK-NEXT: eor w8, w8, w9877; CHECK-NEXT: eor w8, w8, w8, lsr #8878; CHECK-NEXT: and w0, w8, #0xff879; CHECK-NEXT: ret880entry:881 %y = zext <8 x i8> %x to <8 x i32>882 %z = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> %y)883 ret i32 %z884}885 886define i32 @xor_sext_v16i8_i32(<16 x i8> %x) {887; CHECK-LABEL: xor_sext_v16i8_i32:888; CHECK: // %bb.0: // %entry889; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8890; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b891; CHECK-NEXT: fmov x8, d0892; CHECK-NEXT: eor x8, x8, x8, lsr #32893; CHECK-NEXT: lsr x9, x8, #16894; CHECK-NEXT: eor w8, w8, w9895; CHECK-NEXT: eor w8, w8, w8, lsr #8896; CHECK-NEXT: sxtb w0, w8897; CHECK-NEXT: ret898entry:899 %y = sext <16 x i8> %x to <16 x i32>900 %z = call i32 @llvm.vector.reduce.xor.v16i32(<16 x i32> %y)901 ret i32 %z902}903 904define i32 @xor_zext_v16i8_i32(<16 x i8> %x) {905; CHECK-LABEL: xor_zext_v16i8_i32:906; CHECK: // %bb.0: // %entry907; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8908; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b909; CHECK-NEXT: fmov x8, d0910; CHECK-NEXT: eor x8, x8, x8, lsr #32911; CHECK-NEXT: lsr x9, x8, #16912; CHECK-NEXT: eor w8, w8, w9913; CHECK-NEXT: eor w8, w8, w8, lsr #8914; CHECK-NEXT: and w0, w8, #0xff915; CHECK-NEXT: ret916entry:917 %y = zext <16 x i8> %x to <16 x i32>918 %z = call i32 @llvm.vector.reduce.xor.v16i32(<16 x i32> %y)919 ret i32 %z920}921 922define i64 @xor_sext_v8i8_i64(<8 x i8> %x) {923; CHECK-LABEL: xor_sext_v8i8_i64:924; CHECK: // %bb.0: // %entry925; CHECK-NEXT: fmov x8, d0926; CHECK-NEXT: eor x8, x8, x8, lsr #32927; CHECK-NEXT: lsr x9, x8, #16928; CHECK-NEXT: eor w8, w8, w9929; CHECK-NEXT: eor w8, w8, w8, lsr #8930; CHECK-NEXT: sxtb x0, w8931; CHECK-NEXT: ret932entry:933 %y = sext <8 x i8> %x to <8 x i64>934 %z = call i64 @llvm.vector.reduce.xor.v8i64(<8 x i64> %y)935 ret i64 %z936}937 938define i64 @xor_zext_v8i8_i64(<8 x i8> %x) {939; CHECK-LABEL: xor_zext_v8i8_i64:940; CHECK: // %bb.0: // %entry941; CHECK-NEXT: fmov x8, d0942; CHECK-NEXT: eor x8, x8, x8, lsr #32943; CHECK-NEXT: lsr x9, x8, #16944; CHECK-NEXT: eor w8, w8, w9945; CHECK-NEXT: eor w8, w8, w8, lsr #8946; CHECK-NEXT: and x0, x8, #0xff947; CHECK-NEXT: ret948entry:949 %y = zext <8 x i8> %x to <8 x i64>950 %z = call i64 @llvm.vector.reduce.xor.v8i64(<8 x i64> %y)951 ret i64 %z952}953 954define i64 @xor_sext_v16i8_i64(<16 x i8> %x) {955; CHECK-LABEL: xor_sext_v16i8_i64:956; CHECK: // %bb.0: // %entry957; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8958; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b959; CHECK-NEXT: fmov x8, d0960; CHECK-NEXT: eor x8, x8, x8, lsr #32961; CHECK-NEXT: lsr x9, x8, #16962; CHECK-NEXT: eor w8, w8, w9963; CHECK-NEXT: eor w8, w8, w8, lsr #8964; CHECK-NEXT: sxtb x0, w8965; CHECK-NEXT: ret966entry:967 %y = sext <16 x i8> %x to <16 x i64>968 %z = call i64 @llvm.vector.reduce.xor.v16i64(<16 x i64> %y)969 ret i64 %z970}971 972define i64 @xor_zext_v16i8_i64(<16 x i8> %x) {973; CHECK-LABEL: xor_zext_v16i8_i64:974; CHECK: // %bb.0: // %entry975; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8976; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b977; CHECK-NEXT: fmov x8, d0978; CHECK-NEXT: eor x8, x8, x8, lsr #32979; CHECK-NEXT: lsr x9, x8, #16980; CHECK-NEXT: eor w8, w8, w9981; CHECK-NEXT: eor w8, w8, w8, lsr #8982; CHECK-NEXT: and x0, x8, #0xff983; CHECK-NEXT: ret984entry:985 %y = zext <16 x i8> %x to <16 x i64>986 %z = call i64 @llvm.vector.reduce.xor.v16i64(<16 x i64> %y)987 ret i64 %z988}989 990define i32 @xor_sext_v4i16_i32(<4 x i16> %x) {991; CHECK-LABEL: xor_sext_v4i16_i32:992; CHECK: // %bb.0: // %entry993; CHECK-NEXT: fmov x8, d0994; CHECK-NEXT: lsr x9, x8, #32995; CHECK-NEXT: eor w8, w8, w9996; CHECK-NEXT: eor w8, w8, w8, lsr #16997; CHECK-NEXT: sxth w0, w8998; CHECK-NEXT: ret999entry:1000 %y = sext <4 x i16> %x to <4 x i32>1001 %z = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %y)1002 ret i32 %z1003}1004 1005define i32 @xor_zext_v4i16_i32(<4 x i16> %x) {1006; CHECK-LABEL: xor_zext_v4i16_i32:1007; CHECK: // %bb.0: // %entry1008; CHECK-NEXT: fmov x8, d01009; CHECK-NEXT: lsr x9, x8, #321010; CHECK-NEXT: eor w8, w8, w91011; CHECK-NEXT: eor w8, w8, w8, lsr #161012; CHECK-NEXT: and w0, w8, #0xffff1013; CHECK-NEXT: ret1014entry:1015 %y = zext <4 x i16> %x to <4 x i32>1016 %z = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %y)1017 ret i32 %z1018}1019 1020define i32 @xor_sext_v8i16_i32(<8 x i16> %x) {1021; CHECK-LABEL: xor_sext_v8i16_i32:1022; CHECK: // %bb.0: // %entry1023; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #81024; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b1025; CHECK-NEXT: fmov x8, d01026; CHECK-NEXT: lsr x9, x8, #321027; CHECK-NEXT: eor w8, w8, w91028; CHECK-NEXT: eor w8, w8, w8, lsr #161029; CHECK-NEXT: sxth w0, w81030; CHECK-NEXT: ret1031entry:1032 %y = sext <8 x i16> %x to <8 x i32>1033 %z = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> %y)1034 ret i32 %z1035}1036 1037define i32 @xor_zext_v8i16_i32(<8 x i16> %x) {1038; CHECK-LABEL: xor_zext_v8i16_i32:1039; CHECK: // %bb.0: // %entry1040; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #81041; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b1042; CHECK-NEXT: fmov x8, d01043; CHECK-NEXT: lsr x9, x8, #321044; CHECK-NEXT: eor w8, w8, w91045; CHECK-NEXT: eor w8, w8, w8, lsr #161046; CHECK-NEXT: and w0, w8, #0xffff1047; CHECK-NEXT: ret1048entry:1049 %y = zext <8 x i16> %x to <8 x i32>1050 %z = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> %y)1051 ret i32 %z1052}1053 1054define i64 @xor_sext_v4i16_i64(<4 x i16> %x) {1055; CHECK-LABEL: xor_sext_v4i16_i64:1056; CHECK: // %bb.0: // %entry1057; CHECK-NEXT: fmov x8, d01058; CHECK-NEXT: lsr x9, x8, #321059; CHECK-NEXT: eor w8, w8, w91060; CHECK-NEXT: eor w8, w8, w8, lsr #161061; CHECK-NEXT: sxth x0, w81062; CHECK-NEXT: ret1063entry:1064 %y = sext <4 x i16> %x to <4 x i64>1065 %z = call i64 @llvm.vector.reduce.xor.v4i64(<4 x i64> %y)1066 ret i64 %z1067}1068 1069define i64 @xor_zext_v4i16_i64(<4 x i16> %x) {1070; CHECK-LABEL: xor_zext_v4i16_i64:1071; CHECK: // %bb.0: // %entry1072; CHECK-NEXT: fmov x8, d01073; CHECK-NEXT: lsr x9, x8, #321074; CHECK-NEXT: eor w8, w8, w91075; CHECK-NEXT: eor w8, w8, w8, lsr #161076; CHECK-NEXT: and x0, x8, #0xffff1077; CHECK-NEXT: ret1078entry:1079 %y = zext <4 x i16> %x to <4 x i64>1080 %z = call i64 @llvm.vector.reduce.xor.v4i64(<4 x i64> %y)1081 ret i64 %z1082}1083 1084define i64 @xor_sext_v8i16_i64(<8 x i16> %x) {1085; CHECK-LABEL: xor_sext_v8i16_i64:1086; CHECK: // %bb.0: // %entry1087; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #81088; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b1089; CHECK-NEXT: fmov x8, d01090; CHECK-NEXT: lsr x9, x8, #321091; CHECK-NEXT: eor w8, w8, w91092; CHECK-NEXT: eor w8, w8, w8, lsr #161093; CHECK-NEXT: sxth x0, w81094; CHECK-NEXT: ret1095entry:1096 %y = sext <8 x i16> %x to <8 x i64>1097 %z = call i64 @llvm.vector.reduce.xor.v8i64(<8 x i64> %y)1098 ret i64 %z1099}1100 1101define i64 @xor_zext_v8i16_i64(<8 x i16> %x) {1102; CHECK-LABEL: xor_zext_v8i16_i64:1103; CHECK: // %bb.0: // %entry1104; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #81105; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b1106; CHECK-NEXT: fmov x8, d01107; CHECK-NEXT: lsr x9, x8, #321108; CHECK-NEXT: eor w8, w8, w91109; CHECK-NEXT: eor w8, w8, w8, lsr #161110; CHECK-NEXT: and x0, x8, #0xffff1111; CHECK-NEXT: ret1112entry:1113 %y = zext <8 x i16> %x to <8 x i64>1114 %z = call i64 @llvm.vector.reduce.xor.v8i64(<8 x i64> %y)1115 ret i64 %z1116}1117 1118define i64 @xor_sext_v2i32_i64(<2 x i32> %x) {1119; CHECK-LABEL: xor_sext_v2i32_i64:1120; CHECK: // %bb.0: // %entry1121; CHECK-NEXT: fmov x8, d01122; CHECK-NEXT: lsr x9, x8, #321123; CHECK-NEXT: eor w8, w8, w91124; CHECK-NEXT: sxtw x0, w81125; CHECK-NEXT: ret1126entry:1127 %y = sext <2 x i32> %x to <2 x i64>1128 %z = call i64 @llvm.vector.reduce.xor.v2i64(<2 x i64> %y)1129 ret i64 %z1130}1131 1132define i64 @xor_zext_v2i32_i64(<2 x i32> %x) {1133; CHECK-LABEL: xor_zext_v2i32_i64:1134; CHECK: // %bb.0: // %entry1135; CHECK-NEXT: fmov x8, d01136; CHECK-NEXT: lsr x9, x8, #321137; CHECK-NEXT: eor w0, w8, w91138; CHECK-NEXT: ret1139entry:1140 %y = zext <2 x i32> %x to <2 x i64>1141 %z = call i64 @llvm.vector.reduce.xor.v2i64(<2 x i64> %y)1142 ret i64 %z1143}1144 1145define i64 @xor_sext_v4i32_i64(<4 x i32> %x) {1146; CHECK-LABEL: xor_sext_v4i32_i64:1147; CHECK: // %bb.0: // %entry1148; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #81149; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b1150; CHECK-NEXT: fmov x8, d01151; CHECK-NEXT: lsr x9, x8, #321152; CHECK-NEXT: eor w8, w8, w91153; CHECK-NEXT: sxtw x0, w81154; CHECK-NEXT: ret1155entry:1156 %y = sext <4 x i32> %x to <4 x i64>1157 %z = call i64 @llvm.vector.reduce.xor.v4i64(<4 x i64> %y)1158 ret i64 %z1159}1160 1161define i64 @xor_zext_v4i32_i64(<4 x i32> %x) {1162; CHECK-LABEL: xor_zext_v4i32_i64:1163; CHECK: // %bb.0: // %entry1164; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #81165; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b1166; CHECK-NEXT: fmov x8, d01167; CHECK-NEXT: lsr x9, x8, #321168; CHECK-NEXT: eor w0, w8, w91169; CHECK-NEXT: ret1170entry:1171 %y = zext <4 x i32> %x to <4 x i64>1172 %z = call i64 @llvm.vector.reduce.xor.v4i64(<4 x i64> %y)1173 ret i64 %z1174}1175 1176declare i16 @llvm.vector.reduce.and.v16i16(<16 x i16>)1177declare i16 @llvm.vector.reduce.and.v8i16(<8 x i16>)1178declare i16 @llvm.vector.reduce.or.v16i16(<16 x i16>)1179declare i16 @llvm.vector.reduce.or.v8i16(<8 x i16>)1180declare i16 @llvm.vector.reduce.xor.v16i16(<16 x i16>)1181declare i16 @llvm.vector.reduce.xor.v8i16(<8 x i16>)1182declare i32 @llvm.vector.reduce.and.v16i32(<16 x i32>)1183declare i32 @llvm.vector.reduce.and.v4i32(<4 x i32>)1184declare i32 @llvm.vector.reduce.and.v8i32(<8 x i32>)1185declare i32 @llvm.vector.reduce.or.v16i32(<16 x i32>)1186declare i32 @llvm.vector.reduce.or.v4i32(<4 x i32>)1187declare i32 @llvm.vector.reduce.or.v8i32(<8 x i32>)1188declare i32 @llvm.vector.reduce.xor.v16i32(<16 x i32>)1189declare i32 @llvm.vector.reduce.xor.v4i32(<4 x i32>)1190declare i32 @llvm.vector.reduce.xor.v8i32(<8 x i32>)1191declare i64 @llvm.vector.reduce.and.v16i64(<16 x i64>)1192declare i64 @llvm.vector.reduce.and.v2i64(<2 x i64>)1193declare i64 @llvm.vector.reduce.and.v4i64(<4 x i64>)1194declare i64 @llvm.vector.reduce.and.v8i64(<8 x i64>)1195declare i64 @llvm.vector.reduce.or.v16i64(<16 x i64>)1196declare i64 @llvm.vector.reduce.or.v2i64(<2 x i64>)1197declare i64 @llvm.vector.reduce.or.v4i64(<4 x i64>)1198declare i64 @llvm.vector.reduce.or.v8i64(<8 x i64>)1199declare i64 @llvm.vector.reduce.xor.v16i64(<16 x i64>)1200declare i64 @llvm.vector.reduce.xor.v2i64(<2 x i64>)1201declare i64 @llvm.vector.reduce.xor.v4i64(<4 x i64>)1202declare i64 @llvm.vector.reduce.xor.v8i64(<8 x i64>)1203