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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK3 4declare i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %a)5declare i1 @llvm.vector.reduce.and.v2i1(<2 x i1> %a)6declare i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %a)7declare i1 @llvm.vector.reduce.and.v8i1(<8 x i1> %a)8declare i1 @llvm.vector.reduce.and.v16i1(<16 x i1> %a)9declare i1 @llvm.vector.reduce.and.v32i1(<32 x i1> %a)10 11declare i1 @llvm.vector.reduce.or.v1i1(<1 x i1> %a)12declare i1 @llvm.vector.reduce.or.v2i1(<2 x i1> %a)13declare i1 @llvm.vector.reduce.or.v4i1(<4 x i1> %a)14declare i1 @llvm.vector.reduce.or.v8i1(<8 x i1> %a)15declare i1 @llvm.vector.reduce.or.v16i1(<16 x i1> %a)16declare i1 @llvm.vector.reduce.or.v32i1(<32 x i1> %a)17 18declare i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> %a)19declare i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> %a)20declare i1 @llvm.vector.reduce.xor.v4i1(<4 x i1> %a)21declare i1 @llvm.vector.reduce.xor.v8i1(<8 x i1> %a)22declare i1 @llvm.vector.reduce.xor.v16i1(<16 x i1> %a)23declare i1 @llvm.vector.reduce.xor.v32i1(<32 x i1> %a)24 25define i32 @reduce_and_v1i8(<1 x i8> %a0, i32 %a1, i32 %a2) nounwind {26; CHECK-LABEL: reduce_and_v1i8:27; CHECK: // %bb.0:28; CHECK-NEXT: // kill: def $d0 killed $d0 def $q029; CHECK-NEXT: umov w8, v0.b[0]30; CHECK-NEXT: tst w8, #0x8031; CHECK-NEXT: csel w0, w0, w1, ne32; CHECK-NEXT: ret33 %x = icmp slt <1 x i8> %a0, zeroinitializer34 %y = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %x)35 %z = select i1 %y, i32 %a1, i32 %a236 ret i32 %z37}38 39define i32 @reduce_and_v2i8(<2 x i8> %a0, i32 %a1, i32 %a2) nounwind {40; CHECK-LABEL: reduce_and_v2i8:41; CHECK: // %bb.0:42; CHECK-NEXT: shl v0.2s, v0.2s, #2443; CHECK-NEXT: sshr v0.2s, v0.2s, #2444; CHECK-NEXT: cmlt v0.2s, v0.2s, #045; CHECK-NEXT: uminp v0.2s, v0.2s, v0.2s46; CHECK-NEXT: fmov w8, s047; CHECK-NEXT: tst w8, #0x148; CHECK-NEXT: csel w0, w0, w1, ne49; CHECK-NEXT: ret50 %x = icmp slt <2 x i8> %a0, zeroinitializer51 %y = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> %x)52 %z = select i1 %y, i32 %a1, i32 %a253 ret i32 %z54}55 56define i32 @reduce_and_v4i8(<4 x i8> %a0, i32 %a1, i32 %a2) nounwind {57; CHECK-LABEL: reduce_and_v4i8:58; CHECK: // %bb.0:59; CHECK-NEXT: shl v0.4h, v0.4h, #860; CHECK-NEXT: sshr v0.4h, v0.4h, #861; CHECK-NEXT: cmlt v0.4h, v0.4h, #062; CHECK-NEXT: uminv h0, v0.4h63; CHECK-NEXT: fmov w8, s064; CHECK-NEXT: tst w8, #0x165; CHECK-NEXT: csel w0, w0, w1, ne66; CHECK-NEXT: ret67 %x = icmp slt <4 x i8> %a0, zeroinitializer68 %y = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %x)69 %z = select i1 %y, i32 %a1, i32 %a270 ret i32 %z71}72 73define i32 @reduce_and_v8i8(<8 x i8> %a0, i32 %a1, i32 %a2) nounwind {74; CHECK-LABEL: reduce_and_v8i8:75; CHECK: // %bb.0:76; CHECK-NEXT: cmlt v0.8b, v0.8b, #077; CHECK-NEXT: uminv b0, v0.8b78; CHECK-NEXT: fmov w8, s079; CHECK-NEXT: tst w8, #0x180; CHECK-NEXT: csel w0, w0, w1, ne81; CHECK-NEXT: ret82 %x = icmp slt <8 x i8> %a0, zeroinitializer83 %y = call i1 @llvm.vector.reduce.and.v8i1(<8 x i1> %x)84 %z = select i1 %y, i32 %a1, i32 %a285 ret i32 %z86}87 88define i32 @reduce_and_v16i8(<16 x i8> %a0, i32 %a1, i32 %a2) nounwind {89; CHECK-LABEL: reduce_and_v16i8:90; CHECK: // %bb.0:91; CHECK-NEXT: cmlt v0.16b, v0.16b, #092; CHECK-NEXT: uminv b0, v0.16b93; CHECK-NEXT: fmov w8, s094; CHECK-NEXT: tst w8, #0x195; CHECK-NEXT: csel w0, w0, w1, ne96; CHECK-NEXT: ret97 %x = icmp slt <16 x i8> %a0, zeroinitializer98 %y = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> %x)99 %z = select i1 %y, i32 %a1, i32 %a2100 ret i32 %z101}102 103define i32 @reduce_and_v32i8(<32 x i8> %a0, i32 %a1, i32 %a2) nounwind {104; CHECK-LABEL: reduce_and_v32i8:105; CHECK: // %bb.0:106; CHECK-NEXT: and v0.16b, v0.16b, v1.16b107; CHECK-NEXT: cmlt v0.16b, v0.16b, #0108; CHECK-NEXT: uminv b0, v0.16b109; CHECK-NEXT: fmov w8, s0110; CHECK-NEXT: tst w8, #0x1111; CHECK-NEXT: csel w0, w0, w1, ne112; CHECK-NEXT: ret113 %x = icmp slt <32 x i8> %a0, zeroinitializer114 %y = call i1 @llvm.vector.reduce.and.v32i1(<32 x i1> %x)115 %z = select i1 %y, i32 %a1, i32 %a2116 ret i32 %z117}118 119define i32 @reduce_and_v1i16(<1 x i16> %a0, i32 %a1, i32 %a2) nounwind {120; CHECK-LABEL: reduce_and_v1i16:121; CHECK: // %bb.0:122; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0123; CHECK-NEXT: umov w8, v0.h[0]124; CHECK-NEXT: tst w8, #0x8000125; CHECK-NEXT: csel w0, w0, w1, ne126; CHECK-NEXT: ret127 %x = icmp slt <1 x i16> %a0, zeroinitializer128 %y = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %x)129 %z = select i1 %y, i32 %a1, i32 %a2130 ret i32 %z131}132 133define i32 @reduce_and_v2i16(<2 x i16> %a0, i32 %a1, i32 %a2) nounwind {134; CHECK-LABEL: reduce_and_v2i16:135; CHECK: // %bb.0:136; CHECK-NEXT: shl v0.2s, v0.2s, #16137; CHECK-NEXT: sshr v0.2s, v0.2s, #16138; CHECK-NEXT: cmlt v0.2s, v0.2s, #0139; CHECK-NEXT: uminp v0.2s, v0.2s, v0.2s140; CHECK-NEXT: fmov w8, s0141; CHECK-NEXT: tst w8, #0x1142; CHECK-NEXT: csel w0, w0, w1, ne143; CHECK-NEXT: ret144 %x = icmp slt <2 x i16> %a0, zeroinitializer145 %y = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> %x)146 %z = select i1 %y, i32 %a1, i32 %a2147 ret i32 %z148}149 150define i32 @reduce_and_v4i16(<4 x i16> %a0, i32 %a1, i32 %a2) nounwind {151; CHECK-LABEL: reduce_and_v4i16:152; CHECK: // %bb.0:153; CHECK-NEXT: cmlt v0.4h, v0.4h, #0154; CHECK-NEXT: uminv h0, v0.4h155; CHECK-NEXT: fmov w8, s0156; CHECK-NEXT: tst w8, #0x1157; CHECK-NEXT: csel w0, w0, w1, ne158; CHECK-NEXT: ret159 %x = icmp slt <4 x i16> %a0, zeroinitializer160 %y = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %x)161 %z = select i1 %y, i32 %a1, i32 %a2162 ret i32 %z163}164 165define i32 @reduce_and_v8i16(<8 x i16> %a0, i32 %a1, i32 %a2) nounwind {166; CHECK-LABEL: reduce_and_v8i16:167; CHECK: // %bb.0:168; CHECK-NEXT: cmlt v0.8h, v0.8h, #0169; CHECK-NEXT: uminv h0, v0.8h170; CHECK-NEXT: fmov w8, s0171; CHECK-NEXT: tst w8, #0x1172; CHECK-NEXT: csel w0, w0, w1, ne173; CHECK-NEXT: ret174 %x = icmp slt <8 x i16> %a0, zeroinitializer175 %y = call i1 @llvm.vector.reduce.and.v8i1(<8 x i1> %x)176 %z = select i1 %y, i32 %a1, i32 %a2177 ret i32 %z178}179 180define i32 @reduce_and_v16i16(<16 x i16> %a0, i32 %a1, i32 %a2) nounwind {181; CHECK-LABEL: reduce_and_v16i16:182; CHECK: // %bb.0:183; CHECK-NEXT: cmlt v1.8h, v1.8h, #0184; CHECK-NEXT: cmlt v0.8h, v0.8h, #0185; CHECK-NEXT: uzp1 v0.16b, v0.16b, v1.16b186; CHECK-NEXT: uminv b0, v0.16b187; CHECK-NEXT: fmov w8, s0188; CHECK-NEXT: tst w8, #0x1189; CHECK-NEXT: csel w0, w0, w1, ne190; CHECK-NEXT: ret191 %x = icmp slt <16 x i16> %a0, zeroinitializer192 %y = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> %x)193 %z = select i1 %y, i32 %a1, i32 %a2194 ret i32 %z195}196 197define i32 @reduce_and_v1i32(<1 x i32> %a0, i32 %a1, i32 %a2) nounwind {198; CHECK-LABEL: reduce_and_v1i32:199; CHECK: // %bb.0:200; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0201; CHECK-NEXT: fmov w8, s0202; CHECK-NEXT: cmp w8, #0203; CHECK-NEXT: csel w0, w0, w1, mi204; CHECK-NEXT: ret205 %x = icmp slt <1 x i32> %a0, zeroinitializer206 %y = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %x)207 %z = select i1 %y, i32 %a1, i32 %a2208 ret i32 %z209}210 211define i32 @reduce_and_v2i32(<2 x i32> %a0, i32 %a1, i32 %a2) nounwind {212; CHECK-LABEL: reduce_and_v2i32:213; CHECK: // %bb.0:214; CHECK-NEXT: cmlt v0.2s, v0.2s, #0215; CHECK-NEXT: uminp v0.2s, v0.2s, v0.2s216; CHECK-NEXT: fmov w8, s0217; CHECK-NEXT: tst w8, #0x1218; CHECK-NEXT: csel w0, w0, w1, ne219; CHECK-NEXT: ret220 %x = icmp slt <2 x i32> %a0, zeroinitializer221 %y = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> %x)222 %z = select i1 %y, i32 %a1, i32 %a2223 ret i32 %z224}225 226define i32 @reduce_and_v4i32(<4 x i32> %a0, i32 %a1, i32 %a2) nounwind {227; CHECK-LABEL: reduce_and_v4i32:228; CHECK: // %bb.0:229; CHECK-NEXT: cmlt v0.4s, v0.4s, #0230; CHECK-NEXT: uminv s0, v0.4s231; CHECK-NEXT: fmov w8, s0232; CHECK-NEXT: tst w8, #0x1233; CHECK-NEXT: csel w0, w0, w1, ne234; CHECK-NEXT: ret235 %x = icmp slt <4 x i32> %a0, zeroinitializer236 %y = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %x)237 %z = select i1 %y, i32 %a1, i32 %a2238 ret i32 %z239}240 241define i32 @reduce_and_v8i32(<8 x i32> %a0, i32 %a1, i32 %a2) nounwind {242; CHECK-LABEL: reduce_and_v8i32:243; CHECK: // %bb.0:244; CHECK-NEXT: cmlt v1.4s, v1.4s, #0245; CHECK-NEXT: cmlt v0.4s, v0.4s, #0246; CHECK-NEXT: uzp1 v0.8h, v0.8h, v1.8h247; CHECK-NEXT: uminv h0, v0.8h248; CHECK-NEXT: fmov w8, s0249; CHECK-NEXT: tst w8, #0x1250; CHECK-NEXT: csel w0, w0, w1, ne251; CHECK-NEXT: ret252 %x = icmp slt <8 x i32> %a0, zeroinitializer253 %y = call i1 @llvm.vector.reduce.and.v8i1(<8 x i1> %x)254 %z = select i1 %y, i32 %a1, i32 %a2255 ret i32 %z256}257 258define i32 @reduce_and_v1i64(<1 x i64> %a0, i32 %a1, i32 %a2) nounwind {259; CHECK-LABEL: reduce_and_v1i64:260; CHECK: // %bb.0:261; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0262; CHECK-NEXT: fmov x8, d0263; CHECK-NEXT: cmp x8, #0264; CHECK-NEXT: csel w0, w0, w1, mi265; CHECK-NEXT: ret266 %x = icmp slt <1 x i64> %a0, zeroinitializer267 %y = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %x)268 %z = select i1 %y, i32 %a1, i32 %a2269 ret i32 %z270}271 272define i32 @reduce_and_v2i64(<2 x i64> %a0, i32 %a1, i32 %a2) nounwind {273; CHECK-LABEL: reduce_and_v2i64:274; CHECK: // %bb.0:275; CHECK-NEXT: cmlt v0.2d, v0.2d, #0276; CHECK-NEXT: uminv s0, v0.4s277; CHECK-NEXT: fmov w8, s0278; CHECK-NEXT: tst w8, #0x1279; CHECK-NEXT: csel w0, w0, w1, ne280; CHECK-NEXT: ret281 %x = icmp slt <2 x i64> %a0, zeroinitializer282 %y = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> %x)283 %z = select i1 %y, i32 %a1, i32 %a2284 ret i32 %z285}286 287define i32 @reduce_and_v4i64(<4 x i64> %a0, i32 %a1, i32 %a2) nounwind {288; CHECK-LABEL: reduce_and_v4i64:289; CHECK: // %bb.0:290; CHECK-NEXT: cmlt v1.2d, v1.2d, #0291; CHECK-NEXT: cmlt v0.2d, v0.2d, #0292; CHECK-NEXT: uzp1 v0.4s, v0.4s, v1.4s293; CHECK-NEXT: uminv s0, v0.4s294; CHECK-NEXT: fmov w8, s0295; CHECK-NEXT: tst w8, #0x1296; CHECK-NEXT: csel w0, w0, w1, ne297; CHECK-NEXT: ret298 %x = icmp slt <4 x i64> %a0, zeroinitializer299 %y = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %x)300 %z = select i1 %y, i32 %a1, i32 %a2301 ret i32 %z302}303 304define i32 @reduce_or_v1i8(<1 x i8> %a0, i32 %a1, i32 %a2) nounwind {305; CHECK-LABEL: reduce_or_v1i8:306; CHECK: // %bb.0:307; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0308; CHECK-NEXT: umov w8, v0.b[0]309; CHECK-NEXT: tst w8, #0x80310; CHECK-NEXT: csel w0, w0, w1, ne311; CHECK-NEXT: ret312 %x = icmp slt <1 x i8> %a0, zeroinitializer313 %y = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> %x)314 %z = select i1 %y, i32 %a1, i32 %a2315 ret i32 %z316}317 318define i32 @reduce_or_v2i8(<2 x i8> %a0, i32 %a1, i32 %a2) nounwind {319; CHECK-LABEL: reduce_or_v2i8:320; CHECK: // %bb.0:321; CHECK-NEXT: shl v0.2s, v0.2s, #24322; CHECK-NEXT: sshr v0.2s, v0.2s, #24323; CHECK-NEXT: cmlt v0.2s, v0.2s, #0324; CHECK-NEXT: umaxp v0.2s, v0.2s, v0.2s325; CHECK-NEXT: fmov w8, s0326; CHECK-NEXT: tst w8, #0x1327; CHECK-NEXT: csel w0, w0, w1, ne328; CHECK-NEXT: ret329 %x = icmp slt <2 x i8> %a0, zeroinitializer330 %y = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> %x)331 %z = select i1 %y, i32 %a1, i32 %a2332 ret i32 %z333}334 335define i32 @reduce_or_v4i8(<4 x i8> %a0, i32 %a1, i32 %a2) nounwind {336; CHECK-LABEL: reduce_or_v4i8:337; CHECK: // %bb.0:338; CHECK-NEXT: shl v0.4h, v0.4h, #8339; CHECK-NEXT: sshr v0.4h, v0.4h, #8340; CHECK-NEXT: cmlt v0.4h, v0.4h, #0341; CHECK-NEXT: umaxv h0, v0.4h342; CHECK-NEXT: fmov w8, s0343; CHECK-NEXT: tst w8, #0x1344; CHECK-NEXT: csel w0, w0, w1, ne345; CHECK-NEXT: ret346 %x = icmp slt <4 x i8> %a0, zeroinitializer347 %y = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> %x)348 %z = select i1 %y, i32 %a1, i32 %a2349 ret i32 %z350}351 352define i32 @reduce_or_v8i8(<8 x i8> %a0, i32 %a1, i32 %a2) nounwind {353; CHECK-LABEL: reduce_or_v8i8:354; CHECK: // %bb.0:355; CHECK-NEXT: cmlt v0.8b, v0.8b, #0356; CHECK-NEXT: umaxv b0, v0.8b357; CHECK-NEXT: fmov w8, s0358; CHECK-NEXT: tst w8, #0x1359; CHECK-NEXT: csel w0, w0, w1, ne360; CHECK-NEXT: ret361 %x = icmp slt <8 x i8> %a0, zeroinitializer362 %y = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> %x)363 %z = select i1 %y, i32 %a1, i32 %a2364 ret i32 %z365}366 367define i32 @reduce_or_v16i8(<16 x i8> %a0, i32 %a1, i32 %a2) nounwind {368; CHECK-LABEL: reduce_or_v16i8:369; CHECK: // %bb.0:370; CHECK-NEXT: cmlt v0.16b, v0.16b, #0371; CHECK-NEXT: umaxv b0, v0.16b372; CHECK-NEXT: fmov w8, s0373; CHECK-NEXT: tst w8, #0x1374; CHECK-NEXT: csel w0, w0, w1, ne375; CHECK-NEXT: ret376 %x = icmp slt <16 x i8> %a0, zeroinitializer377 %y = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> %x)378 %z = select i1 %y, i32 %a1, i32 %a2379 ret i32 %z380}381 382define i32 @reduce_or_v32i8(<32 x i8> %a0, i32 %a1, i32 %a2) nounwind {383; CHECK-LABEL: reduce_or_v32i8:384; CHECK: // %bb.0:385; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b386; CHECK-NEXT: cmlt v0.16b, v0.16b, #0387; CHECK-NEXT: umaxv b0, v0.16b388; CHECK-NEXT: fmov w8, s0389; CHECK-NEXT: tst w8, #0x1390; CHECK-NEXT: csel w0, w0, w1, ne391; CHECK-NEXT: ret392 %x = icmp slt <32 x i8> %a0, zeroinitializer393 %y = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> %x)394 %z = select i1 %y, i32 %a1, i32 %a2395 ret i32 %z396}397 398define i32 @reduce_or_v1i16(<1 x i16> %a0, i32 %a1, i32 %a2) nounwind {399; CHECK-LABEL: reduce_or_v1i16:400; CHECK: // %bb.0:401; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0402; CHECK-NEXT: umov w8, v0.h[0]403; CHECK-NEXT: tst w8, #0x8000404; CHECK-NEXT: csel w0, w0, w1, ne405; CHECK-NEXT: ret406 %x = icmp slt <1 x i16> %a0, zeroinitializer407 %y = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> %x)408 %z = select i1 %y, i32 %a1, i32 %a2409 ret i32 %z410}411 412define i32 @reduce_or_v2i16(<2 x i16> %a0, i32 %a1, i32 %a2) nounwind {413; CHECK-LABEL: reduce_or_v2i16:414; CHECK: // %bb.0:415; CHECK-NEXT: shl v0.2s, v0.2s, #16416; CHECK-NEXT: sshr v0.2s, v0.2s, #16417; CHECK-NEXT: cmlt v0.2s, v0.2s, #0418; CHECK-NEXT: umaxp v0.2s, v0.2s, v0.2s419; CHECK-NEXT: fmov w8, s0420; CHECK-NEXT: tst w8, #0x1421; CHECK-NEXT: csel w0, w0, w1, ne422; CHECK-NEXT: ret423 %x = icmp slt <2 x i16> %a0, zeroinitializer424 %y = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> %x)425 %z = select i1 %y, i32 %a1, i32 %a2426 ret i32 %z427}428 429define i32 @reduce_or_v4i16(<4 x i16> %a0, i32 %a1, i32 %a2) nounwind {430; CHECK-LABEL: reduce_or_v4i16:431; CHECK: // %bb.0:432; CHECK-NEXT: cmlt v0.4h, v0.4h, #0433; CHECK-NEXT: umaxv h0, v0.4h434; CHECK-NEXT: fmov w8, s0435; CHECK-NEXT: tst w8, #0x1436; CHECK-NEXT: csel w0, w0, w1, ne437; CHECK-NEXT: ret438 %x = icmp slt <4 x i16> %a0, zeroinitializer439 %y = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> %x)440 %z = select i1 %y, i32 %a1, i32 %a2441 ret i32 %z442}443 444define i32 @reduce_or_v8i16(<8 x i16> %a0, i32 %a1, i32 %a2) nounwind {445; CHECK-LABEL: reduce_or_v8i16:446; CHECK: // %bb.0:447; CHECK-NEXT: cmlt v0.8h, v0.8h, #0448; CHECK-NEXT: umaxv h0, v0.8h449; CHECK-NEXT: fmov w8, s0450; CHECK-NEXT: tst w8, #0x1451; CHECK-NEXT: csel w0, w0, w1, ne452; CHECK-NEXT: ret453 %x = icmp slt <8 x i16> %a0, zeroinitializer454 %y = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> %x)455 %z = select i1 %y, i32 %a1, i32 %a2456 ret i32 %z457}458 459define i32 @reduce_or_v16i16(<16 x i16> %a0, i32 %a1, i32 %a2) nounwind {460; CHECK-LABEL: reduce_or_v16i16:461; CHECK: // %bb.0:462; CHECK-NEXT: cmlt v1.8h, v1.8h, #0463; CHECK-NEXT: cmlt v0.8h, v0.8h, #0464; CHECK-NEXT: uzp1 v0.16b, v0.16b, v1.16b465; CHECK-NEXT: umaxv b0, v0.16b466; CHECK-NEXT: fmov w8, s0467; CHECK-NEXT: tst w8, #0x1468; CHECK-NEXT: csel w0, w0, w1, ne469; CHECK-NEXT: ret470 %x = icmp slt <16 x i16> %a0, zeroinitializer471 %y = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> %x)472 %z = select i1 %y, i32 %a1, i32 %a2473 ret i32 %z474}475 476define i32 @reduce_or_v1i32(<1 x i32> %a0, i32 %a1, i32 %a2) nounwind {477; CHECK-LABEL: reduce_or_v1i32:478; CHECK: // %bb.0:479; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0480; CHECK-NEXT: fmov w8, s0481; CHECK-NEXT: cmp w8, #0482; CHECK-NEXT: csel w0, w0, w1, mi483; CHECK-NEXT: ret484 %x = icmp slt <1 x i32> %a0, zeroinitializer485 %y = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> %x)486 %z = select i1 %y, i32 %a1, i32 %a2487 ret i32 %z488}489 490define i32 @reduce_or_v2i32(<2 x i32> %a0, i32 %a1, i32 %a2) nounwind {491; CHECK-LABEL: reduce_or_v2i32:492; CHECK: // %bb.0:493; CHECK-NEXT: cmlt v0.2s, v0.2s, #0494; CHECK-NEXT: umaxp v0.2s, v0.2s, v0.2s495; CHECK-NEXT: fmov w8, s0496; CHECK-NEXT: tst w8, #0x1497; CHECK-NEXT: csel w0, w0, w1, ne498; CHECK-NEXT: ret499 %x = icmp slt <2 x i32> %a0, zeroinitializer500 %y = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> %x)501 %z = select i1 %y, i32 %a1, i32 %a2502 ret i32 %z503}504 505define i32 @reduce_or_v4i32(<4 x i32> %a0, i32 %a1, i32 %a2) nounwind {506; CHECK-LABEL: reduce_or_v4i32:507; CHECK: // %bb.0:508; CHECK-NEXT: cmlt v0.4s, v0.4s, #0509; CHECK-NEXT: umaxv s0, v0.4s510; CHECK-NEXT: fmov w8, s0511; CHECK-NEXT: tst w8, #0x1512; CHECK-NEXT: csel w0, w0, w1, ne513; CHECK-NEXT: ret514 %x = icmp slt <4 x i32> %a0, zeroinitializer515 %y = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> %x)516 %z = select i1 %y, i32 %a1, i32 %a2517 ret i32 %z518}519 520define i32 @reduce_or_v8i32(<8 x i32> %a0, i32 %a1, i32 %a2) nounwind {521; CHECK-LABEL: reduce_or_v8i32:522; CHECK: // %bb.0:523; CHECK-NEXT: cmlt v1.4s, v1.4s, #0524; CHECK-NEXT: cmlt v0.4s, v0.4s, #0525; CHECK-NEXT: uzp1 v0.8h, v0.8h, v1.8h526; CHECK-NEXT: umaxv h0, v0.8h527; CHECK-NEXT: fmov w8, s0528; CHECK-NEXT: tst w8, #0x1529; CHECK-NEXT: csel w0, w0, w1, ne530; CHECK-NEXT: ret531 %x = icmp slt <8 x i32> %a0, zeroinitializer532 %y = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> %x)533 %z = select i1 %y, i32 %a1, i32 %a2534 ret i32 %z535}536 537define i32 @reduce_or_v1i64(<1 x i64> %a0, i32 %a1, i32 %a2) nounwind {538; CHECK-LABEL: reduce_or_v1i64:539; CHECK: // %bb.0:540; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0541; CHECK-NEXT: fmov x8, d0542; CHECK-NEXT: cmp x8, #0543; CHECK-NEXT: csel w0, w0, w1, mi544; CHECK-NEXT: ret545 %x = icmp slt <1 x i64> %a0, zeroinitializer546 %y = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> %x)547 %z = select i1 %y, i32 %a1, i32 %a2548 ret i32 %z549}550 551define i32 @reduce_or_v2i64(<2 x i64> %a0, i32 %a1, i32 %a2) nounwind {552; CHECK-LABEL: reduce_or_v2i64:553; CHECK: // %bb.0:554; CHECK-NEXT: cmlt v0.2d, v0.2d, #0555; CHECK-NEXT: umaxv s0, v0.4s556; CHECK-NEXT: fmov w8, s0557; CHECK-NEXT: tst w8, #0x1558; CHECK-NEXT: csel w0, w0, w1, ne559; CHECK-NEXT: ret560 %x = icmp slt <2 x i64> %a0, zeroinitializer561 %y = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> %x)562 %z = select i1 %y, i32 %a1, i32 %a2563 ret i32 %z564}565 566define i32 @reduce_or_v4i64(<4 x i64> %a0, i32 %a1, i32 %a2) nounwind {567; CHECK-LABEL: reduce_or_v4i64:568; CHECK: // %bb.0:569; CHECK-NEXT: cmlt v1.2d, v1.2d, #0570; CHECK-NEXT: cmlt v0.2d, v0.2d, #0571; CHECK-NEXT: uzp1 v0.4s, v0.4s, v1.4s572; CHECK-NEXT: umaxv s0, v0.4s573; CHECK-NEXT: fmov w8, s0574; CHECK-NEXT: tst w8, #0x1575; CHECK-NEXT: csel w0, w0, w1, ne576; CHECK-NEXT: ret577 %x = icmp slt <4 x i64> %a0, zeroinitializer578 %y = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> %x)579 %z = select i1 %y, i32 %a1, i32 %a2580 ret i32 %z581}582 583define i32 @reduce_xor_v1i8(<1 x i8> %a0, i32 %a1, i32 %a2) nounwind {584; CHECK-LABEL: reduce_xor_v1i8:585; CHECK: // %bb.0:586; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0587; CHECK-NEXT: umov w8, v0.b[0]588; CHECK-NEXT: tst w8, #0x80589; CHECK-NEXT: csel w0, w0, w1, ne590; CHECK-NEXT: ret591 %x = icmp slt <1 x i8> %a0, zeroinitializer592 %y = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> %x)593 %z = select i1 %y, i32 %a1, i32 %a2594 ret i32 %z595}596 597define i32 @reduce_xor_v2i8(<2 x i8> %a0, i32 %a1, i32 %a2) nounwind {598; CHECK-LABEL: reduce_xor_v2i8:599; CHECK: // %bb.0:600; CHECK-NEXT: shl v0.2s, v0.2s, #24601; CHECK-NEXT: sshr v0.2s, v0.2s, #24602; CHECK-NEXT: cmlt v0.2s, v0.2s, #0603; CHECK-NEXT: addp v0.2s, v0.2s, v0.2s604; CHECK-NEXT: fmov w8, s0605; CHECK-NEXT: tst w8, #0x1606; CHECK-NEXT: csel w0, w0, w1, ne607; CHECK-NEXT: ret608 %x = icmp slt <2 x i8> %a0, zeroinitializer609 %y = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> %x)610 %z = select i1 %y, i32 %a1, i32 %a2611 ret i32 %z612}613 614define i32 @reduce_xor_v4i8(<4 x i8> %a0, i32 %a1, i32 %a2) nounwind {615; CHECK-LABEL: reduce_xor_v4i8:616; CHECK: // %bb.0:617; CHECK-NEXT: shl v0.4h, v0.4h, #8618; CHECK-NEXT: sshr v0.4h, v0.4h, #8619; CHECK-NEXT: cmlt v0.4h, v0.4h, #0620; CHECK-NEXT: addv h0, v0.4h621; CHECK-NEXT: fmov w8, s0622; CHECK-NEXT: tst w8, #0x1623; CHECK-NEXT: csel w0, w0, w1, ne624; CHECK-NEXT: ret625 %x = icmp slt <4 x i8> %a0, zeroinitializer626 %y = call i1 @llvm.vector.reduce.xor.v4i1(<4 x i1> %x)627 %z = select i1 %y, i32 %a1, i32 %a2628 ret i32 %z629}630 631define i32 @reduce_xor_v8i8(<8 x i8> %a0, i32 %a1, i32 %a2) nounwind {632; CHECK-LABEL: reduce_xor_v8i8:633; CHECK: // %bb.0:634; CHECK-NEXT: cmlt v0.8b, v0.8b, #0635; CHECK-NEXT: addv b0, v0.8b636; CHECK-NEXT: fmov w8, s0637; CHECK-NEXT: tst w8, #0x1638; CHECK-NEXT: csel w0, w0, w1, ne639; CHECK-NEXT: ret640 %x = icmp slt <8 x i8> %a0, zeroinitializer641 %y = call i1 @llvm.vector.reduce.xor.v8i1(<8 x i1> %x)642 %z = select i1 %y, i32 %a1, i32 %a2643 ret i32 %z644}645 646define i32 @reduce_xor_v16i8(<16 x i8> %a0, i32 %a1, i32 %a2) nounwind {647; CHECK-LABEL: reduce_xor_v16i8:648; CHECK: // %bb.0:649; CHECK-NEXT: cmlt v0.16b, v0.16b, #0650; CHECK-NEXT: addv b0, v0.16b651; CHECK-NEXT: fmov w8, s0652; CHECK-NEXT: tst w8, #0x1653; CHECK-NEXT: csel w0, w0, w1, ne654; CHECK-NEXT: ret655 %x = icmp slt <16 x i8> %a0, zeroinitializer656 %y = call i1 @llvm.vector.reduce.xor.v16i1(<16 x i1> %x)657 %z = select i1 %y, i32 %a1, i32 %a2658 ret i32 %z659}660 661define i32 @reduce_xor_v32i8(<32 x i8> %a0, i32 %a1, i32 %a2) nounwind {662; CHECK-LABEL: reduce_xor_v32i8:663; CHECK: // %bb.0:664; CHECK-NEXT: cmlt v1.16b, v1.16b, #0665; CHECK-NEXT: cmlt v0.16b, v0.16b, #0666; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b667; CHECK-NEXT: addv b0, v0.16b668; CHECK-NEXT: fmov w8, s0669; CHECK-NEXT: tst w8, #0x1670; CHECK-NEXT: csel w0, w0, w1, ne671; CHECK-NEXT: ret672 %x = icmp slt <32 x i8> %a0, zeroinitializer673 %y = call i1 @llvm.vector.reduce.xor.v32i1(<32 x i1> %x)674 %z = select i1 %y, i32 %a1, i32 %a2675 ret i32 %z676}677 678define i32 @reduce_xor_v1i16(<1 x i16> %a0, i32 %a1, i32 %a2) nounwind {679; CHECK-LABEL: reduce_xor_v1i16:680; CHECK: // %bb.0:681; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0682; CHECK-NEXT: umov w8, v0.h[0]683; CHECK-NEXT: tst w8, #0x8000684; CHECK-NEXT: csel w0, w0, w1, ne685; CHECK-NEXT: ret686 %x = icmp slt <1 x i16> %a0, zeroinitializer687 %y = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> %x)688 %z = select i1 %y, i32 %a1, i32 %a2689 ret i32 %z690}691 692define i32 @reduce_xor_v2i16(<2 x i16> %a0, i32 %a1, i32 %a2) nounwind {693; CHECK-LABEL: reduce_xor_v2i16:694; CHECK: // %bb.0:695; CHECK-NEXT: shl v0.2s, v0.2s, #16696; CHECK-NEXT: sshr v0.2s, v0.2s, #16697; CHECK-NEXT: cmlt v0.2s, v0.2s, #0698; CHECK-NEXT: addp v0.2s, v0.2s, v0.2s699; CHECK-NEXT: fmov w8, s0700; CHECK-NEXT: tst w8, #0x1701; CHECK-NEXT: csel w0, w0, w1, ne702; CHECK-NEXT: ret703 %x = icmp slt <2 x i16> %a0, zeroinitializer704 %y = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> %x)705 %z = select i1 %y, i32 %a1, i32 %a2706 ret i32 %z707}708 709define i32 @reduce_xor_v4i16(<4 x i16> %a0, i32 %a1, i32 %a2) nounwind {710; CHECK-LABEL: reduce_xor_v4i16:711; CHECK: // %bb.0:712; CHECK-NEXT: cmlt v0.4h, v0.4h, #0713; CHECK-NEXT: addv h0, v0.4h714; CHECK-NEXT: fmov w8, s0715; CHECK-NEXT: tst w8, #0x1716; CHECK-NEXT: csel w0, w0, w1, ne717; CHECK-NEXT: ret718 %x = icmp slt <4 x i16> %a0, zeroinitializer719 %y = call i1 @llvm.vector.reduce.xor.v4i1(<4 x i1> %x)720 %z = select i1 %y, i32 %a1, i32 %a2721 ret i32 %z722}723 724define i32 @reduce_xor_v8i16(<8 x i16> %a0, i32 %a1, i32 %a2) nounwind {725; CHECK-LABEL: reduce_xor_v8i16:726; CHECK: // %bb.0:727; CHECK-NEXT: cmlt v0.8h, v0.8h, #0728; CHECK-NEXT: addv h0, v0.8h729; CHECK-NEXT: fmov w8, s0730; CHECK-NEXT: tst w8, #0x1731; CHECK-NEXT: csel w0, w0, w1, ne732; CHECK-NEXT: ret733 %x = icmp slt <8 x i16> %a0, zeroinitializer734 %y = call i1 @llvm.vector.reduce.xor.v8i1(<8 x i1> %x)735 %z = select i1 %y, i32 %a1, i32 %a2736 ret i32 %z737}738 739define i32 @reduce_xor_v16i16(<16 x i16> %a0, i32 %a1, i32 %a2) nounwind {740; CHECK-LABEL: reduce_xor_v16i16:741; CHECK: // %bb.0:742; CHECK-NEXT: cmlt v1.8h, v1.8h, #0743; CHECK-NEXT: cmlt v0.8h, v0.8h, #0744; CHECK-NEXT: uzp1 v0.16b, v0.16b, v1.16b745; CHECK-NEXT: addv b0, v0.16b746; CHECK-NEXT: fmov w8, s0747; CHECK-NEXT: tst w8, #0x1748; CHECK-NEXT: csel w0, w0, w1, ne749; CHECK-NEXT: ret750 %x = icmp slt <16 x i16> %a0, zeroinitializer751 %y = call i1 @llvm.vector.reduce.xor.v16i1(<16 x i1> %x)752 %z = select i1 %y, i32 %a1, i32 %a2753 ret i32 %z754}755 756define i32 @reduce_xor_v1i32(<1 x i32> %a0, i32 %a1, i32 %a2) nounwind {757; CHECK-LABEL: reduce_xor_v1i32:758; CHECK: // %bb.0:759; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0760; CHECK-NEXT: fmov w8, s0761; CHECK-NEXT: cmp w8, #0762; CHECK-NEXT: csel w0, w0, w1, mi763; CHECK-NEXT: ret764 %x = icmp slt <1 x i32> %a0, zeroinitializer765 %y = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> %x)766 %z = select i1 %y, i32 %a1, i32 %a2767 ret i32 %z768}769 770define i32 @reduce_xor_v2i32(<2 x i32> %a0, i32 %a1, i32 %a2) nounwind {771; CHECK-LABEL: reduce_xor_v2i32:772; CHECK: // %bb.0:773; CHECK-NEXT: cmlt v0.2s, v0.2s, #0774; CHECK-NEXT: addp v0.2s, v0.2s, v0.2s775; CHECK-NEXT: fmov w8, s0776; CHECK-NEXT: tst w8, #0x1777; CHECK-NEXT: csel w0, w0, w1, ne778; CHECK-NEXT: ret779 %x = icmp slt <2 x i32> %a0, zeroinitializer780 %y = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> %x)781 %z = select i1 %y, i32 %a1, i32 %a2782 ret i32 %z783}784 785define i32 @reduce_xor_v4i32(<4 x i32> %a0, i32 %a1, i32 %a2) nounwind {786; CHECK-LABEL: reduce_xor_v4i32:787; CHECK: // %bb.0:788; CHECK-NEXT: cmlt v0.4s, v0.4s, #0789; CHECK-NEXT: addv s0, v0.4s790; CHECK-NEXT: fmov w8, s0791; CHECK-NEXT: tst w8, #0x1792; CHECK-NEXT: csel w0, w0, w1, ne793; CHECK-NEXT: ret794 %x = icmp slt <4 x i32> %a0, zeroinitializer795 %y = call i1 @llvm.vector.reduce.xor.v4i1(<4 x i1> %x)796 %z = select i1 %y, i32 %a1, i32 %a2797 ret i32 %z798}799 800define i32 @reduce_xor_v8i32(<8 x i32> %a0, i32 %a1, i32 %a2) nounwind {801; CHECK-LABEL: reduce_xor_v8i32:802; CHECK: // %bb.0:803; CHECK-NEXT: cmlt v1.4s, v1.4s, #0804; CHECK-NEXT: cmlt v0.4s, v0.4s, #0805; CHECK-NEXT: uzp1 v0.8h, v0.8h, v1.8h806; CHECK-NEXT: addv h0, v0.8h807; CHECK-NEXT: fmov w8, s0808; CHECK-NEXT: tst w8, #0x1809; CHECK-NEXT: csel w0, w0, w1, ne810; CHECK-NEXT: ret811 %x = icmp slt <8 x i32> %a0, zeroinitializer812 %y = call i1 @llvm.vector.reduce.xor.v8i1(<8 x i1> %x)813 %z = select i1 %y, i32 %a1, i32 %a2814 ret i32 %z815}816 817define i32 @reduce_xor_v1i64(<1 x i64> %a0, i32 %a1, i32 %a2) nounwind {818; CHECK-LABEL: reduce_xor_v1i64:819; CHECK: // %bb.0:820; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0821; CHECK-NEXT: fmov x8, d0822; CHECK-NEXT: cmp x8, #0823; CHECK-NEXT: csel w0, w0, w1, mi824; CHECK-NEXT: ret825 %x = icmp slt <1 x i64> %a0, zeroinitializer826 %y = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> %x)827 %z = select i1 %y, i32 %a1, i32 %a2828 ret i32 %z829}830 831define i32 @reduce_xor_v2i64(<2 x i64> %a0, i32 %a1, i32 %a2) nounwind {832; CHECK-LABEL: reduce_xor_v2i64:833; CHECK: // %bb.0:834; CHECK-NEXT: cmlt v0.2d, v0.2d, #0835; CHECK-NEXT: addp d0, v0.2d836; CHECK-NEXT: fmov w8, s0837; CHECK-NEXT: tst w8, #0x1838; CHECK-NEXT: csel w0, w0, w1, ne839; CHECK-NEXT: ret840 %x = icmp slt <2 x i64> %a0, zeroinitializer841 %y = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> %x)842 %z = select i1 %y, i32 %a1, i32 %a2843 ret i32 %z844}845 846define i32 @reduce_xor_v4i64(<4 x i64> %a0, i32 %a1, i32 %a2) nounwind {847; CHECK-LABEL: reduce_xor_v4i64:848; CHECK: // %bb.0:849; CHECK-NEXT: cmlt v1.2d, v1.2d, #0850; CHECK-NEXT: cmlt v0.2d, v0.2d, #0851; CHECK-NEXT: uzp1 v0.4s, v0.4s, v1.4s852; CHECK-NEXT: addv s0, v0.4s853; CHECK-NEXT: fmov w8, s0854; CHECK-NEXT: tst w8, #0x1855; CHECK-NEXT: csel w0, w0, w1, ne856; CHECK-NEXT: ret857 %x = icmp slt <4 x i64> %a0, zeroinitializer858 %y = call i1 @llvm.vector.reduce.xor.v4i1(<4 x i1> %x)859 %z = select i1 %y, i32 %a1, i32 %a2860 ret i32 %z861}862