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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP --check-prefix=CHECK-NOFP-SD3; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon,+fullfp16 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP --check-prefix=CHECK-FP-SD4; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOFP --check-prefix=CHECK-NOFP-GI5; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon,+fullfp16 -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP --check-prefix=CHECK-FP-GI6 7; CHECK-NOFP-GI: warning: Instruction selection used fallback path for test_v11f168; CHECK-NOFP-GI-NEXT: warning: Instruction selection used fallback path for test_v11f16_ninf9;10; CHECK-FP-GI: warning: Instruction selection used fallback path for test_v11f1611; CHECK-FP-GI-NEXT: warning: Instruction selection used fallback path for test_v11f16_ninf12 13declare half @llvm.vector.reduce.fmin.v1f16(<1 x half> %a)14declare float @llvm.vector.reduce.fmin.v1f32(<1 x float> %a)15declare double @llvm.vector.reduce.fmin.v1f64(<1 x double> %a)16declare fp128 @llvm.vector.reduce.fmin.v1f128(<1 x fp128> %a)17 18declare half @llvm.vector.reduce.fmin.v4f16(<4 x half> %a)19declare half @llvm.vector.reduce.fmin.v8f16(<8 x half> %a)20declare half @llvm.vector.reduce.fmin.v16f16(<16 x half> %a)21declare float @llvm.vector.reduce.fmin.v2f32(<2 x float> %a)22declare float @llvm.vector.reduce.fmin.v4f32(<4 x float> %a)23declare float @llvm.vector.reduce.fmin.v8f32(<8 x float> %a)24declare float @llvm.vector.reduce.fmin.v16f32(<16 x float> %a)25declare double @llvm.vector.reduce.fmin.v2f64(<2 x double> %a)26declare double @llvm.vector.reduce.fmin.v4f64(<4 x double> %a)27 28declare half @llvm.vector.reduce.fmin.v11f16(<11 x half> %a)29declare float @llvm.vector.reduce.fmin.v3f32(<3 x float> %a)30declare fp128 @llvm.vector.reduce.fmin.v2f128(<2 x fp128> %a)31 32define half @test_v1f16(<1 x half> %a) nounwind {33; CHECK-LABEL: test_v1f16:34; CHECK: // %bb.0:35; CHECK-NEXT: ret36 %b = call nnan half @llvm.vector.reduce.fmin.v1f16(<1 x half> %a)37 ret half %b38}39 40define float @test_v1f32(<1 x float> %a) nounwind {41; CHECK-NOFP-SD-LABEL: test_v1f32:42; CHECK-NOFP-SD: // %bb.0:43; CHECK-NOFP-SD-NEXT: // kill: def $d0 killed $d0 def $q044; CHECK-NOFP-SD-NEXT: // kill: def $s0 killed $s0 killed $q045; CHECK-NOFP-SD-NEXT: ret46;47; CHECK-FP-SD-LABEL: test_v1f32:48; CHECK-FP-SD: // %bb.0:49; CHECK-FP-SD-NEXT: // kill: def $d0 killed $d0 def $q050; CHECK-FP-SD-NEXT: // kill: def $s0 killed $s0 killed $q051; CHECK-FP-SD-NEXT: ret52;53; CHECK-NOFP-GI-LABEL: test_v1f32:54; CHECK-NOFP-GI: // %bb.0:55; CHECK-NOFP-GI-NEXT: // kill: def $s0 killed $s0 killed $d056; CHECK-NOFP-GI-NEXT: ret57;58; CHECK-FP-GI-LABEL: test_v1f32:59; CHECK-FP-GI: // %bb.0:60; CHECK-FP-GI-NEXT: // kill: def $s0 killed $s0 killed $d061; CHECK-FP-GI-NEXT: ret62 %b = call nnan float @llvm.vector.reduce.fmin.v1f32(<1 x float> %a)63 ret float %b64}65 66define double @test_v1f64(<1 x double> %a) nounwind {67; CHECK-LABEL: test_v1f64:68; CHECK: // %bb.0:69; CHECK-NEXT: ret70 %b = call nnan double @llvm.vector.reduce.fmin.v1f64(<1 x double> %a)71 ret double %b72}73 74define fp128 @test_v1f128(<1 x fp128> %a) nounwind {75; CHECK-LABEL: test_v1f128:76; CHECK: // %bb.0:77; CHECK-NEXT: ret78 %b = call nnan fp128 @llvm.vector.reduce.fmin.v1f128(<1 x fp128> %a)79 ret fp128 %b80}81 82define half @test_v4f16(<4 x half> %a) nounwind {83; CHECK-NOFP-SD-LABEL: test_v4f16:84; CHECK-NOFP-SD: // %bb.0:85; CHECK-NOFP-SD-NEXT: // kill: def $d0 killed $d0 def $q086; CHECK-NOFP-SD-NEXT: mov h1, v0.h[1]87; CHECK-NOFP-SD-NEXT: fcvt s2, h088; CHECK-NOFP-SD-NEXT: fcvt s1, h189; CHECK-NOFP-SD-NEXT: fminnm s1, s2, s190; CHECK-NOFP-SD-NEXT: mov h2, v0.h[2]91; CHECK-NOFP-SD-NEXT: mov h0, v0.h[3]92; CHECK-NOFP-SD-NEXT: fcvt h1, s193; CHECK-NOFP-SD-NEXT: fcvt s2, h294; CHECK-NOFP-SD-NEXT: fcvt s0, h095; CHECK-NOFP-SD-NEXT: fcvt s1, h196; CHECK-NOFP-SD-NEXT: fminnm s1, s1, s297; CHECK-NOFP-SD-NEXT: fcvt h1, s198; CHECK-NOFP-SD-NEXT: fcvt s1, h199; CHECK-NOFP-SD-NEXT: fminnm s0, s1, s0100; CHECK-NOFP-SD-NEXT: fcvt h0, s0101; CHECK-NOFP-SD-NEXT: ret102;103; CHECK-FP-LABEL: test_v4f16:104; CHECK-FP: // %bb.0:105; CHECK-FP-NEXT: fminnmv h0, v0.4h106; CHECK-FP-NEXT: ret107;108; CHECK-NOFP-GI-LABEL: test_v4f16:109; CHECK-NOFP-GI: // %bb.0:110; CHECK-NOFP-GI-NEXT: fcvtl v0.4s, v0.4h111; CHECK-NOFP-GI-NEXT: fminnmv s0, v0.4s112; CHECK-NOFP-GI-NEXT: fcvt h0, s0113; CHECK-NOFP-GI-NEXT: ret114 %b = call nnan half @llvm.vector.reduce.fmin.v4f16(<4 x half> %a)115 ret half %b116}117 118define half @test_v4f16_ninf(<4 x half> %a) nounwind {119; CHECK-NOFP-SD-LABEL: test_v4f16_ninf:120; CHECK-NOFP-SD: // %bb.0:121; CHECK-NOFP-SD-NEXT: // kill: def $d0 killed $d0 def $q0122; CHECK-NOFP-SD-NEXT: mov h1, v0.h[1]123; CHECK-NOFP-SD-NEXT: fcvt s2, h0124; CHECK-NOFP-SD-NEXT: fcvt s1, h1125; CHECK-NOFP-SD-NEXT: fminnm s1, s2, s1126; CHECK-NOFP-SD-NEXT: mov h2, v0.h[2]127; CHECK-NOFP-SD-NEXT: mov h0, v0.h[3]128; CHECK-NOFP-SD-NEXT: fcvt h1, s1129; CHECK-NOFP-SD-NEXT: fcvt s2, h2130; CHECK-NOFP-SD-NEXT: fcvt s0, h0131; CHECK-NOFP-SD-NEXT: fcvt s1, h1132; CHECK-NOFP-SD-NEXT: fminnm s1, s1, s2133; CHECK-NOFP-SD-NEXT: fcvt h1, s1134; CHECK-NOFP-SD-NEXT: fcvt s1, h1135; CHECK-NOFP-SD-NEXT: fminnm s0, s1, s0136; CHECK-NOFP-SD-NEXT: fcvt h0, s0137; CHECK-NOFP-SD-NEXT: ret138;139; CHECK-FP-LABEL: test_v4f16_ninf:140; CHECK-FP: // %bb.0:141; CHECK-FP-NEXT: fminnmv h0, v0.4h142; CHECK-FP-NEXT: ret143;144; CHECK-NOFP-GI-LABEL: test_v4f16_ninf:145; CHECK-NOFP-GI: // %bb.0:146; CHECK-NOFP-GI-NEXT: fcvtl v0.4s, v0.4h147; CHECK-NOFP-GI-NEXT: fminnmv s0, v0.4s148; CHECK-NOFP-GI-NEXT: fcvt h0, s0149; CHECK-NOFP-GI-NEXT: ret150 %b = call nnan ninf half @llvm.vector.reduce.fmin.v4f16(<4 x half> %a)151 ret half %b152}153 154define half @test_v8f16(<8 x half> %a) nounwind {155; CHECK-NOFP-SD-LABEL: test_v8f16:156; CHECK-NOFP-SD: // %bb.0:157; CHECK-NOFP-SD-NEXT: mov h1, v0.h[1]158; CHECK-NOFP-SD-NEXT: fcvt s2, h0159; CHECK-NOFP-SD-NEXT: fcvt s1, h1160; CHECK-NOFP-SD-NEXT: fminnm s1, s2, s1161; CHECK-NOFP-SD-NEXT: mov h2, v0.h[2]162; CHECK-NOFP-SD-NEXT: fcvt h1, s1163; CHECK-NOFP-SD-NEXT: fcvt s2, h2164; CHECK-NOFP-SD-NEXT: fcvt s1, h1165; CHECK-NOFP-SD-NEXT: fminnm s1, s1, s2166; CHECK-NOFP-SD-NEXT: mov h2, v0.h[3]167; CHECK-NOFP-SD-NEXT: fcvt h1, s1168; CHECK-NOFP-SD-NEXT: fcvt s2, h2169; CHECK-NOFP-SD-NEXT: fcvt s1, h1170; CHECK-NOFP-SD-NEXT: fminnm s1, s1, s2171; CHECK-NOFP-SD-NEXT: mov h2, v0.h[4]172; CHECK-NOFP-SD-NEXT: fcvt h1, s1173; CHECK-NOFP-SD-NEXT: fcvt s2, h2174; CHECK-NOFP-SD-NEXT: fcvt s1, h1175; CHECK-NOFP-SD-NEXT: fminnm s1, s1, s2176; CHECK-NOFP-SD-NEXT: mov h2, v0.h[5]177; CHECK-NOFP-SD-NEXT: fcvt h1, s1178; CHECK-NOFP-SD-NEXT: fcvt s2, h2179; CHECK-NOFP-SD-NEXT: fcvt s1, h1180; CHECK-NOFP-SD-NEXT: fminnm s1, s1, s2181; CHECK-NOFP-SD-NEXT: mov h2, v0.h[6]182; CHECK-NOFP-SD-NEXT: mov h0, v0.h[7]183; CHECK-NOFP-SD-NEXT: fcvt h1, s1184; CHECK-NOFP-SD-NEXT: fcvt s2, h2185; CHECK-NOFP-SD-NEXT: fcvt s0, h0186; CHECK-NOFP-SD-NEXT: fcvt s1, h1187; CHECK-NOFP-SD-NEXT: fminnm s1, s1, s2188; CHECK-NOFP-SD-NEXT: fcvt h1, s1189; CHECK-NOFP-SD-NEXT: fcvt s1, h1190; CHECK-NOFP-SD-NEXT: fminnm s0, s1, s0191; CHECK-NOFP-SD-NEXT: fcvt h0, s0192; CHECK-NOFP-SD-NEXT: ret193;194; CHECK-FP-LABEL: test_v8f16:195; CHECK-FP: // %bb.0:196; CHECK-FP-NEXT: fminnmv h0, v0.8h197; CHECK-FP-NEXT: ret198;199; CHECK-NOFP-GI-LABEL: test_v8f16:200; CHECK-NOFP-GI: // %bb.0:201; CHECK-NOFP-GI-NEXT: fcvtl v1.4s, v0.4h202; CHECK-NOFP-GI-NEXT: fcvtl2 v0.4s, v0.8h203; CHECK-NOFP-GI-NEXT: fminnm v0.4s, v1.4s, v0.4s204; CHECK-NOFP-GI-NEXT: fminnmv s0, v0.4s205; CHECK-NOFP-GI-NEXT: fcvt h0, s0206; CHECK-NOFP-GI-NEXT: ret207 %b = call nnan half @llvm.vector.reduce.fmin.v8f16(<8 x half> %a)208 ret half %b209}210 211define half @test_v16f16(<16 x half> %a) nounwind {212; CHECK-NOFP-SD-LABEL: test_v16f16:213; CHECK-NOFP-SD: // %bb.0:214; CHECK-NOFP-SD-NEXT: mov h2, v1.h[1]215; CHECK-NOFP-SD-NEXT: mov h3, v0.h[1]216; CHECK-NOFP-SD-NEXT: fcvt s4, h1217; CHECK-NOFP-SD-NEXT: fcvt s5, h0218; CHECK-NOFP-SD-NEXT: fcvt s2, h2219; CHECK-NOFP-SD-NEXT: fcvt s3, h3220; CHECK-NOFP-SD-NEXT: fminnm s4, s5, s4221; CHECK-NOFP-SD-NEXT: mov h5, v0.h[2]222; CHECK-NOFP-SD-NEXT: fminnm s2, s3, s2223; CHECK-NOFP-SD-NEXT: mov h3, v1.h[2]224; CHECK-NOFP-SD-NEXT: fcvt h4, s4225; CHECK-NOFP-SD-NEXT: fcvt s5, h5226; CHECK-NOFP-SD-NEXT: fcvt h2, s2227; CHECK-NOFP-SD-NEXT: fcvt s3, h3228; CHECK-NOFP-SD-NEXT: fcvt s4, h4229; CHECK-NOFP-SD-NEXT: fcvt s2, h2230; CHECK-NOFP-SD-NEXT: fminnm s3, s5, s3231; CHECK-NOFP-SD-NEXT: mov h5, v0.h[3]232; CHECK-NOFP-SD-NEXT: fminnm s2, s4, s2233; CHECK-NOFP-SD-NEXT: mov h4, v1.h[3]234; CHECK-NOFP-SD-NEXT: fcvt h3, s3235; CHECK-NOFP-SD-NEXT: fcvt s5, h5236; CHECK-NOFP-SD-NEXT: fcvt h2, s2237; CHECK-NOFP-SD-NEXT: fcvt s4, h4238; CHECK-NOFP-SD-NEXT: fcvt s3, h3239; CHECK-NOFP-SD-NEXT: fcvt s2, h2240; CHECK-NOFP-SD-NEXT: fminnm s4, s5, s4241; CHECK-NOFP-SD-NEXT: mov h5, v0.h[4]242; CHECK-NOFP-SD-NEXT: fminnm s2, s2, s3243; CHECK-NOFP-SD-NEXT: mov h3, v1.h[4]244; CHECK-NOFP-SD-NEXT: fcvt h4, s4245; CHECK-NOFP-SD-NEXT: fcvt s5, h5246; CHECK-NOFP-SD-NEXT: fcvt h2, s2247; CHECK-NOFP-SD-NEXT: fcvt s3, h3248; CHECK-NOFP-SD-NEXT: fcvt s4, h4249; CHECK-NOFP-SD-NEXT: fcvt s2, h2250; CHECK-NOFP-SD-NEXT: fminnm s3, s5, s3251; CHECK-NOFP-SD-NEXT: mov h5, v0.h[5]252; CHECK-NOFP-SD-NEXT: fminnm s2, s2, s4253; CHECK-NOFP-SD-NEXT: mov h4, v1.h[5]254; CHECK-NOFP-SD-NEXT: fcvt h3, s3255; CHECK-NOFP-SD-NEXT: fcvt s5, h5256; CHECK-NOFP-SD-NEXT: fcvt h2, s2257; CHECK-NOFP-SD-NEXT: fcvt s4, h4258; CHECK-NOFP-SD-NEXT: fcvt s3, h3259; CHECK-NOFP-SD-NEXT: fcvt s2, h2260; CHECK-NOFP-SD-NEXT: fminnm s4, s5, s4261; CHECK-NOFP-SD-NEXT: mov h5, v0.h[6]262; CHECK-NOFP-SD-NEXT: mov h0, v0.h[7]263; CHECK-NOFP-SD-NEXT: fminnm s2, s2, s3264; CHECK-NOFP-SD-NEXT: fcvt h3, s4265; CHECK-NOFP-SD-NEXT: mov h4, v1.h[6]266; CHECK-NOFP-SD-NEXT: fcvt s5, h5267; CHECK-NOFP-SD-NEXT: mov h1, v1.h[7]268; CHECK-NOFP-SD-NEXT: fcvt s0, h0269; CHECK-NOFP-SD-NEXT: fcvt h2, s2270; CHECK-NOFP-SD-NEXT: fcvt s3, h3271; CHECK-NOFP-SD-NEXT: fcvt s4, h4272; CHECK-NOFP-SD-NEXT: fcvt s1, h1273; CHECK-NOFP-SD-NEXT: fcvt s2, h2274; CHECK-NOFP-SD-NEXT: fminnm s0, s0, s1275; CHECK-NOFP-SD-NEXT: fminnm s2, s2, s3276; CHECK-NOFP-SD-NEXT: fminnm s3, s5, s4277; CHECK-NOFP-SD-NEXT: fcvt h0, s0278; CHECK-NOFP-SD-NEXT: fcvt h2, s2279; CHECK-NOFP-SD-NEXT: fcvt h3, s3280; CHECK-NOFP-SD-NEXT: fcvt s0, h0281; CHECK-NOFP-SD-NEXT: fcvt s2, h2282; CHECK-NOFP-SD-NEXT: fcvt s3, h3283; CHECK-NOFP-SD-NEXT: fminnm s2, s2, s3284; CHECK-NOFP-SD-NEXT: fcvt h1, s2285; CHECK-NOFP-SD-NEXT: fcvt s1, h1286; CHECK-NOFP-SD-NEXT: fminnm s0, s1, s0287; CHECK-NOFP-SD-NEXT: fcvt h0, s0288; CHECK-NOFP-SD-NEXT: ret289;290; CHECK-FP-LABEL: test_v16f16:291; CHECK-FP: // %bb.0:292; CHECK-FP-NEXT: fminnm v0.8h, v0.8h, v1.8h293; CHECK-FP-NEXT: fminnmv h0, v0.8h294; CHECK-FP-NEXT: ret295;296; CHECK-NOFP-GI-LABEL: test_v16f16:297; CHECK-NOFP-GI: // %bb.0:298; CHECK-NOFP-GI-NEXT: fcvtl v2.4s, v0.4h299; CHECK-NOFP-GI-NEXT: fcvtl2 v0.4s, v0.8h300; CHECK-NOFP-GI-NEXT: fcvtl v3.4s, v1.4h301; CHECK-NOFP-GI-NEXT: fcvtl2 v1.4s, v1.8h302; CHECK-NOFP-GI-NEXT: fminnm v0.4s, v2.4s, v0.4s303; CHECK-NOFP-GI-NEXT: fminnm v1.4s, v3.4s, v1.4s304; CHECK-NOFP-GI-NEXT: fminnm v0.4s, v0.4s, v1.4s305; CHECK-NOFP-GI-NEXT: fminnmv s0, v0.4s306; CHECK-NOFP-GI-NEXT: fcvt h0, s0307; CHECK-NOFP-GI-NEXT: ret308 %b = call nnan half @llvm.vector.reduce.fmin.v16f16(<16 x half> %a)309 ret half %b310}311 312define float @test_v2f32_ninf(<2 x float> %a) nounwind {313; CHECK-LABEL: test_v2f32_ninf:314; CHECK: // %bb.0:315; CHECK-NEXT: fminnmp s0, v0.2s316; CHECK-NEXT: ret317 %b = call float @llvm.vector.reduce.fmin.v2f32(<2 x float> %a)318 ret float %b319}320 321define float @test_v4f32_ninf(<4 x float> %a) nounwind {322; CHECK-LABEL: test_v4f32_ninf:323; CHECK: // %bb.0:324; CHECK-NEXT: fminnmv s0, v0.4s325; CHECK-NEXT: ret326 %b = call nnan ninf float @llvm.vector.reduce.fmin.v4f32(<4 x float> %a)327 ret float %b328}329 330define float @test_v8f32(<8 x float> %a) nounwind {331; CHECK-LABEL: test_v8f32:332; CHECK: // %bb.0:333; CHECK-NEXT: fminnm v0.4s, v0.4s, v1.4s334; CHECK-NEXT: fminnmv s0, v0.4s335; CHECK-NEXT: ret336 %b = call nnan float @llvm.vector.reduce.fmin.v8f32(<8 x float> %a)337 ret float %b338}339 340define float @test_v16f32(<16 x float> %a) nounwind {341; CHECK-NOFP-SD-LABEL: test_v16f32:342; CHECK-NOFP-SD: // %bb.0:343; CHECK-NOFP-SD-NEXT: fminnm v1.4s, v1.4s, v3.4s344; CHECK-NOFP-SD-NEXT: fminnm v0.4s, v0.4s, v2.4s345; CHECK-NOFP-SD-NEXT: fminnm v0.4s, v0.4s, v1.4s346; CHECK-NOFP-SD-NEXT: fminnmv s0, v0.4s347; CHECK-NOFP-SD-NEXT: ret348;349; CHECK-FP-SD-LABEL: test_v16f32:350; CHECK-FP-SD: // %bb.0:351; CHECK-FP-SD-NEXT: fminnm v1.4s, v1.4s, v3.4s352; CHECK-FP-SD-NEXT: fminnm v0.4s, v0.4s, v2.4s353; CHECK-FP-SD-NEXT: fminnm v0.4s, v0.4s, v1.4s354; CHECK-FP-SD-NEXT: fminnmv s0, v0.4s355; CHECK-FP-SD-NEXT: ret356;357; CHECK-NOFP-GI-LABEL: test_v16f32:358; CHECK-NOFP-GI: // %bb.0:359; CHECK-NOFP-GI-NEXT: fminnm v0.4s, v0.4s, v1.4s360; CHECK-NOFP-GI-NEXT: fminnm v1.4s, v2.4s, v3.4s361; CHECK-NOFP-GI-NEXT: fminnm v0.4s, v0.4s, v1.4s362; CHECK-NOFP-GI-NEXT: fminnmv s0, v0.4s363; CHECK-NOFP-GI-NEXT: ret364;365; CHECK-FP-GI-LABEL: test_v16f32:366; CHECK-FP-GI: // %bb.0:367; CHECK-FP-GI-NEXT: fminnm v0.4s, v0.4s, v1.4s368; CHECK-FP-GI-NEXT: fminnm v1.4s, v2.4s, v3.4s369; CHECK-FP-GI-NEXT: fminnm v0.4s, v0.4s, v1.4s370; CHECK-FP-GI-NEXT: fminnmv s0, v0.4s371; CHECK-FP-GI-NEXT: ret372 %b = call nnan float @llvm.vector.reduce.fmin.v16f32(<16 x float> %a)373 ret float %b374}375 376define double @test_v2f64(<2 x double> %a) nounwind {377; CHECK-LABEL: test_v2f64:378; CHECK: // %bb.0:379; CHECK-NEXT: fminnmp d0, v0.2d380; CHECK-NEXT: ret381 %b = call double @llvm.vector.reduce.fmin.v2f64(<2 x double> %a)382 ret double %b383}384 385define double @test_v4f64(<4 x double> %a) nounwind {386; CHECK-LABEL: test_v4f64:387; CHECK: // %bb.0:388; CHECK-NEXT: fminnm v0.2d, v0.2d, v1.2d389; CHECK-NEXT: fminnmp d0, v0.2d390; CHECK-NEXT: ret391 %b = call double @llvm.vector.reduce.fmin.v4f64(<4 x double> %a)392 ret double %b393}394 395define half @test_v11f16(<11 x half> %a) nounwind {396; CHECK-NOFP-LABEL: test_v11f16:397; CHECK-NOFP: // %bb.0:398; CHECK-NOFP-NEXT: ldr h16, [sp, #8]399; CHECK-NOFP-NEXT: ldr h17, [sp]400; CHECK-NOFP-NEXT: fcvt s1, h1401; CHECK-NOFP-NEXT: fcvt s0, h0402; CHECK-NOFP-NEXT: fcvt s2, h2403; CHECK-NOFP-NEXT: fcvt s16, h16404; CHECK-NOFP-NEXT: fcvt s17, h17405; CHECK-NOFP-NEXT: fminnm s1, s1, s16406; CHECK-NOFP-NEXT: fminnm s0, s0, s17407; CHECK-NOFP-NEXT: ldr h16, [sp, #16]408; CHECK-NOFP-NEXT: fcvt s16, h16409; CHECK-NOFP-NEXT: fcvt h1, s1410; CHECK-NOFP-NEXT: fcvt h0, s0411; CHECK-NOFP-NEXT: fcvt s1, h1412; CHECK-NOFP-NEXT: fcvt s0, h0413; CHECK-NOFP-NEXT: fminnm s0, s0, s1414; CHECK-NOFP-NEXT: fminnm s1, s2, s16415; CHECK-NOFP-NEXT: fcvt h0, s0416; CHECK-NOFP-NEXT: fcvt h1, s1417; CHECK-NOFP-NEXT: fcvt s0, h0418; CHECK-NOFP-NEXT: fcvt s1, h1419; CHECK-NOFP-NEXT: fminnm s0, s0, s1420; CHECK-NOFP-NEXT: fcvt s1, h3421; CHECK-NOFP-NEXT: fcvt h0, s0422; CHECK-NOFP-NEXT: fcvt s0, h0423; CHECK-NOFP-NEXT: fminnm s0, s0, s1424; CHECK-NOFP-NEXT: fcvt s1, h4425; CHECK-NOFP-NEXT: fcvt h0, s0426; CHECK-NOFP-NEXT: fcvt s0, h0427; CHECK-NOFP-NEXT: fminnm s0, s0, s1428; CHECK-NOFP-NEXT: fcvt s1, h5429; CHECK-NOFP-NEXT: fcvt h0, s0430; CHECK-NOFP-NEXT: fcvt s0, h0431; CHECK-NOFP-NEXT: fminnm s0, s0, s1432; CHECK-NOFP-NEXT: fcvt s1, h6433; CHECK-NOFP-NEXT: fcvt h0, s0434; CHECK-NOFP-NEXT: fcvt s0, h0435; CHECK-NOFP-NEXT: fminnm s0, s0, s1436; CHECK-NOFP-NEXT: fcvt s1, h7437; CHECK-NOFP-NEXT: fcvt h0, s0438; CHECK-NOFP-NEXT: fcvt s0, h0439; CHECK-NOFP-NEXT: fminnm s0, s0, s1440; CHECK-NOFP-NEXT: fcvt h0, s0441; CHECK-NOFP-NEXT: ret442;443; CHECK-FP-LABEL: test_v11f16:444; CHECK-FP: // %bb.0:445; CHECK-FP-NEXT: // kill: def $h0 killed $h0 def $q0446; CHECK-FP-NEXT: // kill: def $h1 killed $h1 def $q1447; CHECK-FP-NEXT: // kill: def $h2 killed $h2 def $q2448; CHECK-FP-NEXT: // kill: def $h3 killed $h3 def $q3449; CHECK-FP-NEXT: // kill: def $h4 killed $h4 def $q4450; CHECK-FP-NEXT: // kill: def $h5 killed $h5 def $q5451; CHECK-FP-NEXT: mov x8, sp452; CHECK-FP-NEXT: // kill: def $h6 killed $h6 def $q6453; CHECK-FP-NEXT: // kill: def $h7 killed $h7 def $q7454; CHECK-FP-NEXT: mov v0.h[1], v1.h[0]455; CHECK-FP-NEXT: movi v1.8h, #124, lsl #8456; CHECK-FP-NEXT: mov v0.h[2], v2.h[0]457; CHECK-FP-NEXT: ld1 { v1.h }[0], [x8]458; CHECK-FP-NEXT: add x8, sp, #8459; CHECK-FP-NEXT: ld1 { v1.h }[1], [x8]460; CHECK-FP-NEXT: add x8, sp, #16461; CHECK-FP-NEXT: mov v0.h[3], v3.h[0]462; CHECK-FP-NEXT: ld1 { v1.h }[2], [x8]463; CHECK-FP-NEXT: mov v0.h[4], v4.h[0]464; CHECK-FP-NEXT: mov v0.h[5], v5.h[0]465; CHECK-FP-NEXT: mov v0.h[6], v6.h[0]466; CHECK-FP-NEXT: mov v0.h[7], v7.h[0]467; CHECK-FP-NEXT: fminnm v0.8h, v0.8h, v1.8h468; CHECK-FP-NEXT: fminnmv h0, v0.8h469; CHECK-FP-NEXT: ret470 %b = call nnan half @llvm.vector.reduce.fmin.v11f16(<11 x half> %a)471 ret half %b472}473 474define half @test_v11f16_ninf(<11 x half> %a) nounwind {475; CHECK-NOFP-LABEL: test_v11f16_ninf:476; CHECK-NOFP: // %bb.0:477; CHECK-NOFP-NEXT: ldr h16, [sp, #8]478; CHECK-NOFP-NEXT: ldr h17, [sp]479; CHECK-NOFP-NEXT: fcvt s1, h1480; CHECK-NOFP-NEXT: fcvt s0, h0481; CHECK-NOFP-NEXT: fcvt s2, h2482; CHECK-NOFP-NEXT: fcvt s16, h16483; CHECK-NOFP-NEXT: fcvt s17, h17484; CHECK-NOFP-NEXT: fminnm s1, s1, s16485; CHECK-NOFP-NEXT: fminnm s0, s0, s17486; CHECK-NOFP-NEXT: ldr h16, [sp, #16]487; CHECK-NOFP-NEXT: fcvt s16, h16488; CHECK-NOFP-NEXT: fcvt h1, s1489; CHECK-NOFP-NEXT: fcvt h0, s0490; CHECK-NOFP-NEXT: fcvt s1, h1491; CHECK-NOFP-NEXT: fcvt s0, h0492; CHECK-NOFP-NEXT: fminnm s0, s0, s1493; CHECK-NOFP-NEXT: fminnm s1, s2, s16494; CHECK-NOFP-NEXT: fcvt h0, s0495; CHECK-NOFP-NEXT: fcvt h1, s1496; CHECK-NOFP-NEXT: fcvt s0, h0497; CHECK-NOFP-NEXT: fcvt s1, h1498; CHECK-NOFP-NEXT: fminnm s0, s0, s1499; CHECK-NOFP-NEXT: fcvt s1, h3500; CHECK-NOFP-NEXT: fcvt h0, s0501; CHECK-NOFP-NEXT: fcvt s0, h0502; CHECK-NOFP-NEXT: fminnm s0, s0, s1503; CHECK-NOFP-NEXT: fcvt s1, h4504; CHECK-NOFP-NEXT: fcvt h0, s0505; CHECK-NOFP-NEXT: fcvt s0, h0506; CHECK-NOFP-NEXT: fminnm s0, s0, s1507; CHECK-NOFP-NEXT: fcvt s1, h5508; CHECK-NOFP-NEXT: fcvt h0, s0509; CHECK-NOFP-NEXT: fcvt s0, h0510; CHECK-NOFP-NEXT: fminnm s0, s0, s1511; CHECK-NOFP-NEXT: fcvt s1, h6512; CHECK-NOFP-NEXT: fcvt h0, s0513; CHECK-NOFP-NEXT: fcvt s0, h0514; CHECK-NOFP-NEXT: fminnm s0, s0, s1515; CHECK-NOFP-NEXT: fcvt s1, h7516; CHECK-NOFP-NEXT: fcvt h0, s0517; CHECK-NOFP-NEXT: fcvt s0, h0518; CHECK-NOFP-NEXT: fminnm s0, s0, s1519; CHECK-NOFP-NEXT: fcvt h0, s0520; CHECK-NOFP-NEXT: ret521;522; CHECK-FP-LABEL: test_v11f16_ninf:523; CHECK-FP: // %bb.0:524; CHECK-FP-NEXT: // kill: def $h0 killed $h0 def $q0525; CHECK-FP-NEXT: // kill: def $h1 killed $h1 def $q1526; CHECK-FP-NEXT: // kill: def $h2 killed $h2 def $q2527; CHECK-FP-NEXT: // kill: def $h3 killed $h3 def $q3528; CHECK-FP-NEXT: // kill: def $h4 killed $h4 def $q4529; CHECK-FP-NEXT: // kill: def $h5 killed $h5 def $q5530; CHECK-FP-NEXT: mov x8, sp531; CHECK-FP-NEXT: // kill: def $h6 killed $h6 def $q6532; CHECK-FP-NEXT: // kill: def $h7 killed $h7 def $q7533; CHECK-FP-NEXT: mov v0.h[1], v1.h[0]534; CHECK-FP-NEXT: mvni v1.8h, #132, lsl #8535; CHECK-FP-NEXT: ld1 { v1.h }[0], [x8]536; CHECK-FP-NEXT: add x8, sp, #8537; CHECK-FP-NEXT: mov v0.h[2], v2.h[0]538; CHECK-FP-NEXT: ld1 { v1.h }[1], [x8]539; CHECK-FP-NEXT: add x8, sp, #16540; CHECK-FP-NEXT: mov v0.h[3], v3.h[0]541; CHECK-FP-NEXT: ld1 { v1.h }[2], [x8]542; CHECK-FP-NEXT: mov v0.h[4], v4.h[0]543; CHECK-FP-NEXT: mov v0.h[5], v5.h[0]544; CHECK-FP-NEXT: mov v0.h[6], v6.h[0]545; CHECK-FP-NEXT: mov v0.h[7], v7.h[0]546; CHECK-FP-NEXT: fminnm v0.8h, v0.8h, v1.8h547; CHECK-FP-NEXT: fminnmv h0, v0.8h548; CHECK-FP-NEXT: ret549 %b = call nnan ninf half @llvm.vector.reduce.fmin.v11f16(<11 x half> %a)550 ret half %b551}552 553define float @test_v3f32(<3 x float> %a) nounwind {554; CHECK-NOFP-SD-LABEL: test_v3f32:555; CHECK-NOFP-SD: // %bb.0:556; CHECK-NOFP-SD-NEXT: mov w8, #2139095040 // =0x7f800000557; CHECK-NOFP-SD-NEXT: fmov s1, w8558; CHECK-NOFP-SD-NEXT: mov v0.s[3], v1.s[0]559; CHECK-NOFP-SD-NEXT: fminnmv s0, v0.4s560; CHECK-NOFP-SD-NEXT: ret561;562; CHECK-FP-SD-LABEL: test_v3f32:563; CHECK-FP-SD: // %bb.0:564; CHECK-FP-SD-NEXT: mov w8, #2139095040 // =0x7f800000565; CHECK-FP-SD-NEXT: fmov s1, w8566; CHECK-FP-SD-NEXT: mov v0.s[3], v1.s[0]567; CHECK-FP-SD-NEXT: fminnmv s0, v0.4s568; CHECK-FP-SD-NEXT: ret569;570; CHECK-NOFP-GI-LABEL: test_v3f32:571; CHECK-NOFP-GI: // %bb.0:572; CHECK-NOFP-GI-NEXT: mov s1, v0.s[1]573; CHECK-NOFP-GI-NEXT: mov s2, v0.s[2]574; CHECK-NOFP-GI-NEXT: fminnm s0, s0, s1575; CHECK-NOFP-GI-NEXT: fminnm s0, s0, s2576; CHECK-NOFP-GI-NEXT: ret577;578; CHECK-FP-GI-LABEL: test_v3f32:579; CHECK-FP-GI: // %bb.0:580; CHECK-FP-GI-NEXT: mov s1, v0.s[1]581; CHECK-FP-GI-NEXT: mov s2, v0.s[2]582; CHECK-FP-GI-NEXT: fminnm s0, s0, s1583; CHECK-FP-GI-NEXT: fminnm s0, s0, s2584; CHECK-FP-GI-NEXT: ret585 %b = call nnan float @llvm.vector.reduce.fmin.v3f32(<3 x float> %a)586 ret float %b587}588 589define float @test_v3f32_ninf(<3 x float> %a) nounwind {590; CHECK-NOFP-SD-LABEL: test_v3f32_ninf:591; CHECK-NOFP-SD: // %bb.0:592; CHECK-NOFP-SD-NEXT: mov w8, #2139095039 // =0x7f7fffff593; CHECK-NOFP-SD-NEXT: fmov s1, w8594; CHECK-NOFP-SD-NEXT: mov v0.s[3], v1.s[0]595; CHECK-NOFP-SD-NEXT: fminnmv s0, v0.4s596; CHECK-NOFP-SD-NEXT: ret597;598; CHECK-FP-SD-LABEL: test_v3f32_ninf:599; CHECK-FP-SD: // %bb.0:600; CHECK-FP-SD-NEXT: mov w8, #2139095039 // =0x7f7fffff601; CHECK-FP-SD-NEXT: fmov s1, w8602; CHECK-FP-SD-NEXT: mov v0.s[3], v1.s[0]603; CHECK-FP-SD-NEXT: fminnmv s0, v0.4s604; CHECK-FP-SD-NEXT: ret605;606; CHECK-NOFP-GI-LABEL: test_v3f32_ninf:607; CHECK-NOFP-GI: // %bb.0:608; CHECK-NOFP-GI-NEXT: mov s1, v0.s[1]609; CHECK-NOFP-GI-NEXT: mov s2, v0.s[2]610; CHECK-NOFP-GI-NEXT: fminnm s0, s0, s1611; CHECK-NOFP-GI-NEXT: fminnm s0, s0, s2612; CHECK-NOFP-GI-NEXT: ret613;614; CHECK-FP-GI-LABEL: test_v3f32_ninf:615; CHECK-FP-GI: // %bb.0:616; CHECK-FP-GI-NEXT: mov s1, v0.s[1]617; CHECK-FP-GI-NEXT: mov s2, v0.s[2]618; CHECK-FP-GI-NEXT: fminnm s0, s0, s1619; CHECK-FP-GI-NEXT: fminnm s0, s0, s2620; CHECK-FP-GI-NEXT: ret621 %b = call nnan ninf float @llvm.vector.reduce.fmin.v3f32(<3 x float> %a)622 ret float %b623}624 625define fp128 @test_v2f128(<2 x fp128> %a) nounwind {626; CHECK-NOFP-SD-LABEL: test_v2f128:627; CHECK-NOFP-SD: // %bb.0:628; CHECK-NOFP-SD-NEXT: sub sp, sp, #48629; CHECK-NOFP-SD-NEXT: str x30, [sp, #32] // 8-byte Spill630; CHECK-NOFP-SD-NEXT: stp q0, q1, [sp] // 32-byte Folded Spill631; CHECK-NOFP-SD-NEXT: bl __lttf2632; CHECK-NOFP-SD-NEXT: ldr q0, [sp, #16] // 16-byte Reload633; CHECK-NOFP-SD-NEXT: cmp w0, #0634; CHECK-NOFP-SD-NEXT: b.pl .LBB18_2635; CHECK-NOFP-SD-NEXT: // %bb.1:636; CHECK-NOFP-SD-NEXT: ldr q0, [sp] // 16-byte Reload637; CHECK-NOFP-SD-NEXT: .LBB18_2:638; CHECK-NOFP-SD-NEXT: ldr x30, [sp, #32] // 8-byte Reload639; CHECK-NOFP-SD-NEXT: add sp, sp, #48640; CHECK-NOFP-SD-NEXT: ret641;642; CHECK-FP-SD-LABEL: test_v2f128:643; CHECK-FP-SD: // %bb.0:644; CHECK-FP-SD-NEXT: sub sp, sp, #48645; CHECK-FP-SD-NEXT: str x30, [sp, #32] // 8-byte Spill646; CHECK-FP-SD-NEXT: stp q0, q1, [sp] // 32-byte Folded Spill647; CHECK-FP-SD-NEXT: bl __lttf2648; CHECK-FP-SD-NEXT: ldr q0, [sp, #16] // 16-byte Reload649; CHECK-FP-SD-NEXT: cmp w0, #0650; CHECK-FP-SD-NEXT: b.pl .LBB18_2651; CHECK-FP-SD-NEXT: // %bb.1:652; CHECK-FP-SD-NEXT: ldr q0, [sp] // 16-byte Reload653; CHECK-FP-SD-NEXT: .LBB18_2:654; CHECK-FP-SD-NEXT: ldr x30, [sp, #32] // 8-byte Reload655; CHECK-FP-SD-NEXT: add sp, sp, #48656; CHECK-FP-SD-NEXT: ret657;658; CHECK-NOFP-GI-LABEL: test_v2f128:659; CHECK-NOFP-GI: // %bb.0:660; CHECK-NOFP-GI-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill661; CHECK-NOFP-GI-NEXT: bl fminl662; CHECK-NOFP-GI-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload663; CHECK-NOFP-GI-NEXT: ret664;665; CHECK-FP-GI-LABEL: test_v2f128:666; CHECK-FP-GI: // %bb.0:667; CHECK-FP-GI-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill668; CHECK-FP-GI-NEXT: bl fminl669; CHECK-FP-GI-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload670; CHECK-FP-GI-NEXT: ret671 %b = call nnan fp128 @llvm.vector.reduce.fmin.v2f128(<2 x fp128> %a)672 ret fp128 %b673}674