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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-SD-NOFP163; RUN: llc -mtriple=aarch64 -mattr=+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-SD-FP164; RUN: llc -mtriple=aarch64 -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-NOFP165; RUN: llc -mtriple=aarch64 -mattr=+fullfp16 -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-FP166 7define float @mul_HalfS(<2 x float> %bin.rdx) {8; CHECK-SD-LABEL: mul_HalfS:9; CHECK-SD: // %bb.0:10; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q011; CHECK-SD-NEXT: fmul s0, s0, v0.s[1]12; CHECK-SD-NEXT: ret13;14; CHECK-GI-LABEL: mul_HalfS:15; CHECK-GI: // %bb.0:16; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q017; CHECK-GI-NEXT: mov s1, v0.s[1]18; CHECK-GI-NEXT: fmul s0, s0, s119; CHECK-GI-NEXT: ret20 %r = call float @llvm.vector.reduce.fmul.f32.v2f32(float 1.0, <2 x float> %bin.rdx)21 ret float %r22}23 24define half @mul_HalfH(<4 x half> %bin.rdx) {25; CHECK-SD-NOFP16-LABEL: mul_HalfH:26; CHECK-SD-NOFP16: // %bb.0:27; CHECK-SD-NOFP16-NEXT: // kill: def $d0 killed $d0 def $q028; CHECK-SD-NOFP16-NEXT: mov h1, v0.h[1]29; CHECK-SD-NOFP16-NEXT: fcvt s2, h030; CHECK-SD-NOFP16-NEXT: fcvt s1, h131; CHECK-SD-NOFP16-NEXT: fmul s1, s2, s132; CHECK-SD-NOFP16-NEXT: mov h2, v0.h[2]33; CHECK-SD-NOFP16-NEXT: mov h0, v0.h[3]34; CHECK-SD-NOFP16-NEXT: fcvt h1, s135; CHECK-SD-NOFP16-NEXT: fcvt s2, h236; CHECK-SD-NOFP16-NEXT: fcvt s0, h037; CHECK-SD-NOFP16-NEXT: fcvt s1, h138; CHECK-SD-NOFP16-NEXT: fmul s1, s1, s239; CHECK-SD-NOFP16-NEXT: fcvt h1, s140; CHECK-SD-NOFP16-NEXT: fcvt s1, h141; CHECK-SD-NOFP16-NEXT: fmul s0, s1, s042; CHECK-SD-NOFP16-NEXT: fcvt h0, s043; CHECK-SD-NOFP16-NEXT: ret44;45; CHECK-SD-FP16-LABEL: mul_HalfH:46; CHECK-SD-FP16: // %bb.0:47; CHECK-SD-FP16-NEXT: // kill: def $d0 killed $d0 def $q048; CHECK-SD-FP16-NEXT: fmul h1, h0, v0.h[1]49; CHECK-SD-FP16-NEXT: fmul h1, h1, v0.h[2]50; CHECK-SD-FP16-NEXT: fmul h0, h1, v0.h[3]51; CHECK-SD-FP16-NEXT: ret52;53; CHECK-GI-NOFP16-LABEL: mul_HalfH:54; CHECK-GI-NOFP16: // %bb.0:55; CHECK-GI-NOFP16-NEXT: // kill: def $d0 killed $d0 def $q056; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[1]57; CHECK-GI-NOFP16-NEXT: fcvt s2, h058; CHECK-GI-NOFP16-NEXT: fcvt s1, h159; CHECK-GI-NOFP16-NEXT: fmul s1, s2, s160; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[2]61; CHECK-GI-NOFP16-NEXT: mov h0, v0.h[3]62; CHECK-GI-NOFP16-NEXT: fcvt h1, s163; CHECK-GI-NOFP16-NEXT: fcvt s2, h264; CHECK-GI-NOFP16-NEXT: fcvt s0, h065; CHECK-GI-NOFP16-NEXT: fcvt s1, h166; CHECK-GI-NOFP16-NEXT: fmul s1, s1, s267; CHECK-GI-NOFP16-NEXT: fcvt h1, s168; CHECK-GI-NOFP16-NEXT: fcvt s1, h169; CHECK-GI-NOFP16-NEXT: fmul s0, s1, s070; CHECK-GI-NOFP16-NEXT: fcvt h0, s071; CHECK-GI-NOFP16-NEXT: ret72;73; CHECK-GI-FP16-LABEL: mul_HalfH:74; CHECK-GI-FP16: // %bb.0:75; CHECK-GI-FP16-NEXT: // kill: def $d0 killed $d0 def $q076; CHECK-GI-FP16-NEXT: mov h1, v0.h[1]77; CHECK-GI-FP16-NEXT: mov h2, v0.h[2]78; CHECK-GI-FP16-NEXT: fmul h1, h0, h179; CHECK-GI-FP16-NEXT: mov h0, v0.h[3]80; CHECK-GI-FP16-NEXT: fmul h1, h1, h281; CHECK-GI-FP16-NEXT: fmul h0, h1, h082; CHECK-GI-FP16-NEXT: ret83 %r = call half @llvm.vector.reduce.fmul.f16.v4f16(half 1.0, <4 x half> %bin.rdx)84 ret half %r85}86 87 88define half @mul_H(<8 x half> %bin.rdx) {89; CHECK-SD-NOFP16-LABEL: mul_H:90; CHECK-SD-NOFP16: // %bb.0:91; CHECK-SD-NOFP16-NEXT: mov h1, v0.h[1]92; CHECK-SD-NOFP16-NEXT: fcvt s2, h093; CHECK-SD-NOFP16-NEXT: fcvt s1, h194; CHECK-SD-NOFP16-NEXT: fmul s1, s2, s195; CHECK-SD-NOFP16-NEXT: mov h2, v0.h[2]96; CHECK-SD-NOFP16-NEXT: fcvt h1, s197; CHECK-SD-NOFP16-NEXT: fcvt s2, h298; CHECK-SD-NOFP16-NEXT: fcvt s1, h199; CHECK-SD-NOFP16-NEXT: fmul s1, s1, s2100; CHECK-SD-NOFP16-NEXT: mov h2, v0.h[3]101; CHECK-SD-NOFP16-NEXT: fcvt h1, s1102; CHECK-SD-NOFP16-NEXT: fcvt s2, h2103; CHECK-SD-NOFP16-NEXT: fcvt s1, h1104; CHECK-SD-NOFP16-NEXT: fmul s1, s1, s2105; CHECK-SD-NOFP16-NEXT: mov h2, v0.h[4]106; CHECK-SD-NOFP16-NEXT: fcvt h1, s1107; CHECK-SD-NOFP16-NEXT: fcvt s2, h2108; CHECK-SD-NOFP16-NEXT: fcvt s1, h1109; CHECK-SD-NOFP16-NEXT: fmul s1, s1, s2110; CHECK-SD-NOFP16-NEXT: mov h2, v0.h[5]111; CHECK-SD-NOFP16-NEXT: fcvt h1, s1112; CHECK-SD-NOFP16-NEXT: fcvt s2, h2113; CHECK-SD-NOFP16-NEXT: fcvt s1, h1114; CHECK-SD-NOFP16-NEXT: fmul s1, s1, s2115; CHECK-SD-NOFP16-NEXT: mov h2, v0.h[6]116; CHECK-SD-NOFP16-NEXT: mov h0, v0.h[7]117; CHECK-SD-NOFP16-NEXT: fcvt h1, s1118; CHECK-SD-NOFP16-NEXT: fcvt s2, h2119; CHECK-SD-NOFP16-NEXT: fcvt s0, h0120; CHECK-SD-NOFP16-NEXT: fcvt s1, h1121; CHECK-SD-NOFP16-NEXT: fmul s1, s1, s2122; CHECK-SD-NOFP16-NEXT: fcvt h1, s1123; CHECK-SD-NOFP16-NEXT: fcvt s1, h1124; CHECK-SD-NOFP16-NEXT: fmul s0, s1, s0125; CHECK-SD-NOFP16-NEXT: fcvt h0, s0126; CHECK-SD-NOFP16-NEXT: ret127;128; CHECK-SD-FP16-LABEL: mul_H:129; CHECK-SD-FP16: // %bb.0:130; CHECK-SD-FP16-NEXT: fmul h1, h0, v0.h[1]131; CHECK-SD-FP16-NEXT: fmul h1, h1, v0.h[2]132; CHECK-SD-FP16-NEXT: fmul h1, h1, v0.h[3]133; CHECK-SD-FP16-NEXT: fmul h1, h1, v0.h[4]134; CHECK-SD-FP16-NEXT: fmul h1, h1, v0.h[5]135; CHECK-SD-FP16-NEXT: fmul h1, h1, v0.h[6]136; CHECK-SD-FP16-NEXT: fmul h0, h1, v0.h[7]137; CHECK-SD-FP16-NEXT: ret138;139; CHECK-GI-NOFP16-LABEL: mul_H:140; CHECK-GI-NOFP16: // %bb.0:141; CHECK-GI-NOFP16-NEXT: mov h1, v0.h[1]142; CHECK-GI-NOFP16-NEXT: fcvt s2, h0143; CHECK-GI-NOFP16-NEXT: fcvt s1, h1144; CHECK-GI-NOFP16-NEXT: fmul s1, s2, s1145; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[2]146; CHECK-GI-NOFP16-NEXT: fcvt h1, s1147; CHECK-GI-NOFP16-NEXT: fcvt s2, h2148; CHECK-GI-NOFP16-NEXT: fcvt s1, h1149; CHECK-GI-NOFP16-NEXT: fmul s1, s1, s2150; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[3]151; CHECK-GI-NOFP16-NEXT: fcvt h1, s1152; CHECK-GI-NOFP16-NEXT: fcvt s2, h2153; CHECK-GI-NOFP16-NEXT: fcvt s1, h1154; CHECK-GI-NOFP16-NEXT: fmul s1, s1, s2155; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[4]156; CHECK-GI-NOFP16-NEXT: fcvt h1, s1157; CHECK-GI-NOFP16-NEXT: fcvt s2, h2158; CHECK-GI-NOFP16-NEXT: fcvt s1, h1159; CHECK-GI-NOFP16-NEXT: fmul s1, s1, s2160; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[5]161; CHECK-GI-NOFP16-NEXT: fcvt h1, s1162; CHECK-GI-NOFP16-NEXT: fcvt s2, h2163; CHECK-GI-NOFP16-NEXT: fcvt s1, h1164; CHECK-GI-NOFP16-NEXT: fmul s1, s1, s2165; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[6]166; CHECK-GI-NOFP16-NEXT: mov h0, v0.h[7]167; CHECK-GI-NOFP16-NEXT: fcvt h1, s1168; CHECK-GI-NOFP16-NEXT: fcvt s2, h2169; CHECK-GI-NOFP16-NEXT: fcvt s0, h0170; CHECK-GI-NOFP16-NEXT: fcvt s1, h1171; CHECK-GI-NOFP16-NEXT: fmul s1, s1, s2172; CHECK-GI-NOFP16-NEXT: fcvt h1, s1173; CHECK-GI-NOFP16-NEXT: fcvt s1, h1174; CHECK-GI-NOFP16-NEXT: fmul s0, s1, s0175; CHECK-GI-NOFP16-NEXT: fcvt h0, s0176; CHECK-GI-NOFP16-NEXT: ret177;178; CHECK-GI-FP16-LABEL: mul_H:179; CHECK-GI-FP16: // %bb.0:180; CHECK-GI-FP16-NEXT: fmul h1, h0, v0.h[1]181; CHECK-GI-FP16-NEXT: fmul h1, h1, v0.h[2]182; CHECK-GI-FP16-NEXT: fmul h1, h1, v0.h[3]183; CHECK-GI-FP16-NEXT: fmul h1, h1, v0.h[4]184; CHECK-GI-FP16-NEXT: fmul h1, h1, v0.h[5]185; CHECK-GI-FP16-NEXT: fmul h1, h1, v0.h[6]186; CHECK-GI-FP16-NEXT: fmul h0, h1, v0.h[7]187; CHECK-GI-FP16-NEXT: ret188 %r = call half @llvm.vector.reduce.fmul.f16.v8f16(half 1.0, <8 x half> %bin.rdx)189 ret half %r190}191 192define float @mul_S(<4 x float> %bin.rdx) {193; CHECK-LABEL: mul_S:194; CHECK: // %bb.0:195; CHECK-NEXT: fmul s1, s0, v0.s[1]196; CHECK-NEXT: fmul s1, s1, v0.s[2]197; CHECK-NEXT: fmul s0, s1, v0.s[3]198; CHECK-NEXT: ret199 %r = call float @llvm.vector.reduce.fmul.f32.v4f32(float 1.0, <4 x float> %bin.rdx)200 ret float %r201}202 203define double @mul_D(<2 x double> %bin.rdx) {204; CHECK-LABEL: mul_D:205; CHECK: // %bb.0:206; CHECK-NEXT: fmul d0, d0, v0.d[1]207; CHECK-NEXT: ret208 %r = call double @llvm.vector.reduce.fmul.f64.v2f64(double 1.0, <2 x double> %bin.rdx)209 ret double %r210}211 212define half @mul_2H(<16 x half> %bin.rdx) {213; CHECK-SD-NOFP16-LABEL: mul_2H:214; CHECK-SD-NOFP16: // %bb.0:215; CHECK-SD-NOFP16-NEXT: mov h2, v0.h[1]216; CHECK-SD-NOFP16-NEXT: fcvt s3, h0217; CHECK-SD-NOFP16-NEXT: fcvt s2, h2218; CHECK-SD-NOFP16-NEXT: fmul s2, s3, s2219; CHECK-SD-NOFP16-NEXT: mov h3, v0.h[2]220; CHECK-SD-NOFP16-NEXT: fcvt h2, s2221; CHECK-SD-NOFP16-NEXT: fcvt s3, h3222; CHECK-SD-NOFP16-NEXT: fcvt s2, h2223; CHECK-SD-NOFP16-NEXT: fmul s2, s2, s3224; CHECK-SD-NOFP16-NEXT: mov h3, v0.h[3]225; CHECK-SD-NOFP16-NEXT: fcvt h2, s2226; CHECK-SD-NOFP16-NEXT: fcvt s3, h3227; CHECK-SD-NOFP16-NEXT: fcvt s2, h2228; CHECK-SD-NOFP16-NEXT: fmul s2, s2, s3229; CHECK-SD-NOFP16-NEXT: mov h3, v0.h[4]230; CHECK-SD-NOFP16-NEXT: fcvt h2, s2231; CHECK-SD-NOFP16-NEXT: fcvt s3, h3232; CHECK-SD-NOFP16-NEXT: fcvt s2, h2233; CHECK-SD-NOFP16-NEXT: fmul s2, s2, s3234; CHECK-SD-NOFP16-NEXT: mov h3, v0.h[5]235; CHECK-SD-NOFP16-NEXT: fcvt h2, s2236; CHECK-SD-NOFP16-NEXT: fcvt s3, h3237; CHECK-SD-NOFP16-NEXT: fcvt s2, h2238; CHECK-SD-NOFP16-NEXT: fmul s2, s2, s3239; CHECK-SD-NOFP16-NEXT: mov h3, v0.h[6]240; CHECK-SD-NOFP16-NEXT: mov h0, v0.h[7]241; CHECK-SD-NOFP16-NEXT: fcvt h2, s2242; CHECK-SD-NOFP16-NEXT: fcvt s3, h3243; CHECK-SD-NOFP16-NEXT: fcvt s0, h0244; CHECK-SD-NOFP16-NEXT: fcvt s2, h2245; CHECK-SD-NOFP16-NEXT: fmul s2, s2, s3246; CHECK-SD-NOFP16-NEXT: fcvt h2, s2247; CHECK-SD-NOFP16-NEXT: fcvt s2, h2248; CHECK-SD-NOFP16-NEXT: fmul s0, s2, s0249; CHECK-SD-NOFP16-NEXT: fcvt s2, h1250; CHECK-SD-NOFP16-NEXT: fcvt h0, s0251; CHECK-SD-NOFP16-NEXT: fcvt s0, h0252; CHECK-SD-NOFP16-NEXT: fmul s0, s0, s2253; CHECK-SD-NOFP16-NEXT: mov h2, v1.h[1]254; CHECK-SD-NOFP16-NEXT: fcvt h0, s0255; CHECK-SD-NOFP16-NEXT: fcvt s2, h2256; CHECK-SD-NOFP16-NEXT: fcvt s0, h0257; CHECK-SD-NOFP16-NEXT: fmul s0, s0, s2258; CHECK-SD-NOFP16-NEXT: mov h2, v1.h[2]259; CHECK-SD-NOFP16-NEXT: fcvt h0, s0260; CHECK-SD-NOFP16-NEXT: fcvt s2, h2261; CHECK-SD-NOFP16-NEXT: fcvt s0, h0262; CHECK-SD-NOFP16-NEXT: fmul s0, s0, s2263; CHECK-SD-NOFP16-NEXT: mov h2, v1.h[3]264; CHECK-SD-NOFP16-NEXT: fcvt h0, s0265; CHECK-SD-NOFP16-NEXT: fcvt s2, h2266; CHECK-SD-NOFP16-NEXT: fcvt s0, h0267; CHECK-SD-NOFP16-NEXT: fmul s0, s0, s2268; CHECK-SD-NOFP16-NEXT: mov h2, v1.h[4]269; CHECK-SD-NOFP16-NEXT: fcvt h0, s0270; CHECK-SD-NOFP16-NEXT: fcvt s2, h2271; CHECK-SD-NOFP16-NEXT: fcvt s0, h0272; CHECK-SD-NOFP16-NEXT: fmul s0, s0, s2273; CHECK-SD-NOFP16-NEXT: mov h2, v1.h[5]274; CHECK-SD-NOFP16-NEXT: fcvt h0, s0275; CHECK-SD-NOFP16-NEXT: fcvt s2, h2276; CHECK-SD-NOFP16-NEXT: fcvt s0, h0277; CHECK-SD-NOFP16-NEXT: fmul s0, s0, s2278; CHECK-SD-NOFP16-NEXT: mov h2, v1.h[6]279; CHECK-SD-NOFP16-NEXT: mov h1, v1.h[7]280; CHECK-SD-NOFP16-NEXT: fcvt h0, s0281; CHECK-SD-NOFP16-NEXT: fcvt s2, h2282; CHECK-SD-NOFP16-NEXT: fcvt s1, h1283; CHECK-SD-NOFP16-NEXT: fcvt s0, h0284; CHECK-SD-NOFP16-NEXT: fmul s0, s0, s2285; CHECK-SD-NOFP16-NEXT: fcvt h0, s0286; CHECK-SD-NOFP16-NEXT: fcvt s0, h0287; CHECK-SD-NOFP16-NEXT: fmul s0, s0, s1288; CHECK-SD-NOFP16-NEXT: fcvt h0, s0289; CHECK-SD-NOFP16-NEXT: ret290;291; CHECK-SD-FP16-LABEL: mul_2H:292; CHECK-SD-FP16: // %bb.0:293; CHECK-SD-FP16-NEXT: fmul h2, h0, v0.h[1]294; CHECK-SD-FP16-NEXT: fmul h2, h2, v0.h[2]295; CHECK-SD-FP16-NEXT: fmul h2, h2, v0.h[3]296; CHECK-SD-FP16-NEXT: fmul h2, h2, v0.h[4]297; CHECK-SD-FP16-NEXT: fmul h2, h2, v0.h[5]298; CHECK-SD-FP16-NEXT: fmul h2, h2, v0.h[6]299; CHECK-SD-FP16-NEXT: fmul h0, h2, v0.h[7]300; CHECK-SD-FP16-NEXT: fmul h0, h0, h1301; CHECK-SD-FP16-NEXT: fmul h0, h0, v1.h[1]302; CHECK-SD-FP16-NEXT: fmul h0, h0, v1.h[2]303; CHECK-SD-FP16-NEXT: fmul h0, h0, v1.h[3]304; CHECK-SD-FP16-NEXT: fmul h0, h0, v1.h[4]305; CHECK-SD-FP16-NEXT: fmul h0, h0, v1.h[5]306; CHECK-SD-FP16-NEXT: fmul h0, h0, v1.h[6]307; CHECK-SD-FP16-NEXT: fmul h0, h0, v1.h[7]308; CHECK-SD-FP16-NEXT: ret309;310; CHECK-GI-NOFP16-LABEL: mul_2H:311; CHECK-GI-NOFP16: // %bb.0:312; CHECK-GI-NOFP16-NEXT: mov h2, v0.h[1]313; CHECK-GI-NOFP16-NEXT: fcvt s3, h0314; CHECK-GI-NOFP16-NEXT: fcvt s2, h2315; CHECK-GI-NOFP16-NEXT: fmul s2, s3, s2316; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[2]317; CHECK-GI-NOFP16-NEXT: fcvt h2, s2318; CHECK-GI-NOFP16-NEXT: fcvt s3, h3319; CHECK-GI-NOFP16-NEXT: fcvt s2, h2320; CHECK-GI-NOFP16-NEXT: fmul s2, s2, s3321; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[3]322; CHECK-GI-NOFP16-NEXT: fcvt h2, s2323; CHECK-GI-NOFP16-NEXT: fcvt s3, h3324; CHECK-GI-NOFP16-NEXT: fcvt s2, h2325; CHECK-GI-NOFP16-NEXT: fmul s2, s2, s3326; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[4]327; CHECK-GI-NOFP16-NEXT: fcvt h2, s2328; CHECK-GI-NOFP16-NEXT: fcvt s3, h3329; CHECK-GI-NOFP16-NEXT: fcvt s2, h2330; CHECK-GI-NOFP16-NEXT: fmul s2, s2, s3331; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[5]332; CHECK-GI-NOFP16-NEXT: fcvt h2, s2333; CHECK-GI-NOFP16-NEXT: fcvt s3, h3334; CHECK-GI-NOFP16-NEXT: fcvt s2, h2335; CHECK-GI-NOFP16-NEXT: fmul s2, s2, s3336; CHECK-GI-NOFP16-NEXT: mov h3, v0.h[6]337; CHECK-GI-NOFP16-NEXT: mov h0, v0.h[7]338; CHECK-GI-NOFP16-NEXT: fcvt h2, s2339; CHECK-GI-NOFP16-NEXT: fcvt s3, h3340; CHECK-GI-NOFP16-NEXT: fcvt s0, h0341; CHECK-GI-NOFP16-NEXT: fcvt s2, h2342; CHECK-GI-NOFP16-NEXT: fmul s2, s2, s3343; CHECK-GI-NOFP16-NEXT: fcvt h2, s2344; CHECK-GI-NOFP16-NEXT: fcvt s2, h2345; CHECK-GI-NOFP16-NEXT: fmul s0, s2, s0346; CHECK-GI-NOFP16-NEXT: fcvt s2, h1347; CHECK-GI-NOFP16-NEXT: fcvt h0, s0348; CHECK-GI-NOFP16-NEXT: fcvt s0, h0349; CHECK-GI-NOFP16-NEXT: fmul s0, s0, s2350; CHECK-GI-NOFP16-NEXT: mov h2, v1.h[1]351; CHECK-GI-NOFP16-NEXT: fcvt h0, s0352; CHECK-GI-NOFP16-NEXT: fcvt s2, h2353; CHECK-GI-NOFP16-NEXT: fcvt s0, h0354; CHECK-GI-NOFP16-NEXT: fmul s0, s0, s2355; CHECK-GI-NOFP16-NEXT: mov h2, v1.h[2]356; CHECK-GI-NOFP16-NEXT: fcvt h0, s0357; CHECK-GI-NOFP16-NEXT: fcvt s2, h2358; CHECK-GI-NOFP16-NEXT: fcvt s0, h0359; CHECK-GI-NOFP16-NEXT: fmul s0, s0, s2360; CHECK-GI-NOFP16-NEXT: mov h2, v1.h[3]361; CHECK-GI-NOFP16-NEXT: fcvt h0, s0362; CHECK-GI-NOFP16-NEXT: fcvt s2, h2363; CHECK-GI-NOFP16-NEXT: fcvt s0, h0364; CHECK-GI-NOFP16-NEXT: fmul s0, s0, s2365; CHECK-GI-NOFP16-NEXT: mov h2, v1.h[4]366; CHECK-GI-NOFP16-NEXT: fcvt h0, s0367; CHECK-GI-NOFP16-NEXT: fcvt s2, h2368; CHECK-GI-NOFP16-NEXT: fcvt s0, h0369; CHECK-GI-NOFP16-NEXT: fmul s0, s0, s2370; CHECK-GI-NOFP16-NEXT: mov h2, v1.h[5]371; CHECK-GI-NOFP16-NEXT: fcvt h0, s0372; CHECK-GI-NOFP16-NEXT: fcvt s2, h2373; CHECK-GI-NOFP16-NEXT: fcvt s0, h0374; CHECK-GI-NOFP16-NEXT: fmul s0, s0, s2375; CHECK-GI-NOFP16-NEXT: mov h2, v1.h[6]376; CHECK-GI-NOFP16-NEXT: mov h1, v1.h[7]377; CHECK-GI-NOFP16-NEXT: fcvt h0, s0378; CHECK-GI-NOFP16-NEXT: fcvt s2, h2379; CHECK-GI-NOFP16-NEXT: fcvt s1, h1380; CHECK-GI-NOFP16-NEXT: fcvt s0, h0381; CHECK-GI-NOFP16-NEXT: fmul s0, s0, s2382; CHECK-GI-NOFP16-NEXT: fcvt h0, s0383; CHECK-GI-NOFP16-NEXT: fcvt s0, h0384; CHECK-GI-NOFP16-NEXT: fmul s0, s0, s1385; CHECK-GI-NOFP16-NEXT: fcvt h0, s0386; CHECK-GI-NOFP16-NEXT: ret387;388; CHECK-GI-FP16-LABEL: mul_2H:389; CHECK-GI-FP16: // %bb.0:390; CHECK-GI-FP16-NEXT: fmul h2, h0, v0.h[1]391; CHECK-GI-FP16-NEXT: fmul h2, h2, v0.h[2]392; CHECK-GI-FP16-NEXT: fmul h2, h2, v0.h[3]393; CHECK-GI-FP16-NEXT: fmul h2, h2, v0.h[4]394; CHECK-GI-FP16-NEXT: fmul h2, h2, v0.h[5]395; CHECK-GI-FP16-NEXT: fmul h2, h2, v0.h[6]396; CHECK-GI-FP16-NEXT: fmul h0, h2, v0.h[7]397; CHECK-GI-FP16-NEXT: fmul h0, h0, h1398; CHECK-GI-FP16-NEXT: fmul h0, h0, v1.h[1]399; CHECK-GI-FP16-NEXT: fmul h0, h0, v1.h[2]400; CHECK-GI-FP16-NEXT: fmul h0, h0, v1.h[3]401; CHECK-GI-FP16-NEXT: fmul h0, h0, v1.h[4]402; CHECK-GI-FP16-NEXT: fmul h0, h0, v1.h[5]403; CHECK-GI-FP16-NEXT: fmul h0, h0, v1.h[6]404; CHECK-GI-FP16-NEXT: fmul h0, h0, v1.h[7]405; CHECK-GI-FP16-NEXT: ret406 %r = call half @llvm.vector.reduce.fmul.f16.v16f16(half 1.0, <16 x half> %bin.rdx)407 ret half %r408}409 410define float @mul_2S(<8 x float> %bin.rdx) {411; CHECK-LABEL: mul_2S:412; CHECK: // %bb.0:413; CHECK-NEXT: fmul s2, s0, v0.s[1]414; CHECK-NEXT: fmul s2, s2, v0.s[2]415; CHECK-NEXT: fmul s0, s2, v0.s[3]416; CHECK-NEXT: fmul s0, s0, s1417; CHECK-NEXT: fmul s0, s0, v1.s[1]418; CHECK-NEXT: fmul s0, s0, v1.s[2]419; CHECK-NEXT: fmul s0, s0, v1.s[3]420; CHECK-NEXT: ret421 %r = call float @llvm.vector.reduce.fmul.f32.v8f32(float 1.0, <8 x float> %bin.rdx)422 ret float %r423}424 425define double @mul_2D(<4 x double> %bin.rdx) {426; CHECK-LABEL: mul_2D:427; CHECK: // %bb.0:428; CHECK-NEXT: fmul d0, d0, v0.d[1]429; CHECK-NEXT: fmul d0, d0, d1430; CHECK-NEXT: fmul d0, d0, v1.d[1]431; CHECK-NEXT: ret432 %r = call double @llvm.vector.reduce.fmul.f64.v4f64(double 1.0, <4 x double> %bin.rdx)433 ret double %r434}435 436; Added at least one test where the start value is not 1.0.437define float @mul_S_init_42(<4 x float> %bin.rdx) {438; CHECK-LABEL: mul_S_init_42:439; CHECK: // %bb.0:440; CHECK-NEXT: mov w8, #1109917696 // =0x42280000441; CHECK-NEXT: fmov s1, w8442; CHECK-NEXT: fmul s1, s1, s0443; CHECK-NEXT: fmul s1, s1, v0.s[1]444; CHECK-NEXT: fmul s1, s1, v0.s[2]445; CHECK-NEXT: fmul s0, s1, v0.s[3]446; CHECK-NEXT: ret447 %r = call float @llvm.vector.reduce.fmul.f32.v4f32(float 42.0, <4 x float> %bin.rdx)448 ret float %r449}450 451; Function Attrs: nounwind readnone452declare half @llvm.vector.reduce.fmul.f16.v4f16(half, <4 x half>)453declare half @llvm.vector.reduce.fmul.f16.v8f16(half, <8 x half>)454declare half @llvm.vector.reduce.fmul.f16.v16f16(half, <16 x half>)455declare float @llvm.vector.reduce.fmul.f32.v2f32(float, <2 x float>)456declare float @llvm.vector.reduce.fmul.f32.v4f32(float, <4 x float>)457declare float @llvm.vector.reduce.fmul.f32.v8f32(float, <8 x float>)458declare double @llvm.vector.reduce.fmul.f64.v2f64(double, <2 x double>)459declare double @llvm.vector.reduce.fmul.f64.v4f64(double, <4 x double>)460