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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-SD-NOFP163; RUN: llc -mtriple=aarch64 -mattr=+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-SD-FP164; RUN: llc -mtriple=aarch64 -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-NOFP165; RUN: llc -mtriple=aarch64 -mattr=+fullfp16 -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-FP166 7define float @mul_HalfS(<2 x float> %bin.rdx) {8; CHECK-SD-LABEL: mul_HalfS:9; CHECK-SD: // %bb.0:10; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q011; CHECK-SD-NEXT: fmul s0, s0, v0.s[1]12; CHECK-SD-NEXT: ret13;14; CHECK-GI-LABEL: mul_HalfS:15; CHECK-GI: // %bb.0:16; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q017; CHECK-GI-NEXT: mov s1, v0.s[1]18; CHECK-GI-NEXT: fmul s0, s0, s119; CHECK-GI-NEXT: ret20 %r = call fast float @llvm.vector.reduce.fmul.f32.v2f32(float 1.0, <2 x float> %bin.rdx)21 ret float %r22}23 24define half @mul_HalfH(<4 x half> %bin.rdx) {25; CHECK-SD-NOFP16-LABEL: mul_HalfH:26; CHECK-SD-NOFP16: // %bb.0:27; CHECK-SD-NOFP16-NEXT: // kill: def $d0 killed $d0 def $q028; CHECK-SD-NOFP16-NEXT: mov h1, v0.h[1]29; CHECK-SD-NOFP16-NEXT: mov h2, v0.h[3]30; CHECK-SD-NOFP16-NEXT: mov h3, v0.h[2]31; CHECK-SD-NOFP16-NEXT: fcvt s0, h032; CHECK-SD-NOFP16-NEXT: fcvt s1, h133; CHECK-SD-NOFP16-NEXT: fcvt s3, h334; CHECK-SD-NOFP16-NEXT: fcvt s2, h235; CHECK-SD-NOFP16-NEXT: fmul s0, s0, s136; CHECK-SD-NOFP16-NEXT: fmul s1, s3, s237; CHECK-SD-NOFP16-NEXT: fmul s0, s0, s138; CHECK-SD-NOFP16-NEXT: fcvt h0, s039; CHECK-SD-NOFP16-NEXT: ret40;41; CHECK-SD-FP16-LABEL: mul_HalfH:42; CHECK-SD-FP16: // %bb.0:43; CHECK-SD-FP16-NEXT: // kill: def $d0 killed $d0 def $q044; CHECK-SD-FP16-NEXT: fmul h1, h0, v0.h[1]45; CHECK-SD-FP16-NEXT: fmul h1, h1, v0.h[2]46; CHECK-SD-FP16-NEXT: fmul h0, h1, v0.h[3]47; CHECK-SD-FP16-NEXT: ret48;49; CHECK-GI-NOFP16-LABEL: mul_HalfH:50; CHECK-GI-NOFP16: // %bb.0:51; CHECK-GI-NOFP16-NEXT: fcvtl v0.4s, v0.4h52; CHECK-GI-NOFP16-NEXT: mov d1, v0.d[1]53; CHECK-GI-NOFP16-NEXT: fmul v0.2s, v0.2s, v1.2s54; CHECK-GI-NOFP16-NEXT: mov s1, v0.s[1]55; CHECK-GI-NOFP16-NEXT: fmul s0, s0, s156; CHECK-GI-NOFP16-NEXT: fcvt h0, s057; CHECK-GI-NOFP16-NEXT: ret58;59; CHECK-GI-FP16-LABEL: mul_HalfH:60; CHECK-GI-FP16: // %bb.0:61; CHECK-GI-FP16-NEXT: // kill: def $d0 killed $d0 def $q062; CHECK-GI-FP16-NEXT: mov h1, v0.h[1]63; CHECK-GI-FP16-NEXT: mov h2, v0.h[2]64; CHECK-GI-FP16-NEXT: mov h3, v0.h[3]65; CHECK-GI-FP16-NEXT: fmul h0, h0, h166; CHECK-GI-FP16-NEXT: fmul h1, h2, h367; CHECK-GI-FP16-NEXT: fmul h0, h0, h168; CHECK-GI-FP16-NEXT: ret69 %r = call fast half @llvm.vector.reduce.fmul.f16.v4f16(half 1.0, <4 x half> %bin.rdx)70 ret half %r71}72 73 74define half @mul_H(<8 x half> %bin.rdx) {75; CHECK-SD-NOFP16-LABEL: mul_H:76; CHECK-SD-NOFP16: // %bb.0:77; CHECK-SD-NOFP16-NEXT: mov h1, v0.h[2]78; CHECK-SD-NOFP16-NEXT: mov h2, v0.h[1]79; CHECK-SD-NOFP16-NEXT: mov h3, v0.h[5]80; CHECK-SD-NOFP16-NEXT: mov h4, v0.h[4]81; CHECK-SD-NOFP16-NEXT: mov h5, v0.h[3]82; CHECK-SD-NOFP16-NEXT: mov h6, v0.h[6]83; CHECK-SD-NOFP16-NEXT: fcvt s7, h084; CHECK-SD-NOFP16-NEXT: mov h0, v0.h[7]85; CHECK-SD-NOFP16-NEXT: fcvt s2, h286; CHECK-SD-NOFP16-NEXT: fcvt s1, h187; CHECK-SD-NOFP16-NEXT: fcvt s3, h388; CHECK-SD-NOFP16-NEXT: fcvt s5, h589; CHECK-SD-NOFP16-NEXT: fcvt s4, h490; CHECK-SD-NOFP16-NEXT: fcvt s0, h091; CHECK-SD-NOFP16-NEXT: fmul s2, s7, s292; CHECK-SD-NOFP16-NEXT: fmul s1, s1, s593; CHECK-SD-NOFP16-NEXT: fmul s3, s4, s394; CHECK-SD-NOFP16-NEXT: fcvt s4, h695; CHECK-SD-NOFP16-NEXT: fmul s1, s2, s196; CHECK-SD-NOFP16-NEXT: fmul s2, s3, s497; CHECK-SD-NOFP16-NEXT: fmul s1, s1, s298; CHECK-SD-NOFP16-NEXT: fmul s0, s1, s099; CHECK-SD-NOFP16-NEXT: fcvt h0, s0100; CHECK-SD-NOFP16-NEXT: ret101;102; CHECK-SD-FP16-LABEL: mul_H:103; CHECK-SD-FP16: // %bb.0:104; CHECK-SD-FP16-NEXT: ext v1.16b, v0.16b, v0.16b, #8105; CHECK-SD-FP16-NEXT: fmul v0.4h, v0.4h, v1.4h106; CHECK-SD-FP16-NEXT: fmul h1, h0, v0.h[1]107; CHECK-SD-FP16-NEXT: fmul h1, h1, v0.h[2]108; CHECK-SD-FP16-NEXT: fmul h0, h1, v0.h[3]109; CHECK-SD-FP16-NEXT: ret110;111; CHECK-GI-NOFP16-LABEL: mul_H:112; CHECK-GI-NOFP16: // %bb.0:113; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v0.4h114; CHECK-GI-NOFP16-NEXT: fcvtl2 v0.4s, v0.8h115; CHECK-GI-NOFP16-NEXT: fmul v0.4s, v1.4s, v0.4s116; CHECK-GI-NOFP16-NEXT: mov d1, v0.d[1]117; CHECK-GI-NOFP16-NEXT: fmul v0.2s, v0.2s, v1.2s118; CHECK-GI-NOFP16-NEXT: mov s1, v0.s[1]119; CHECK-GI-NOFP16-NEXT: fmul s0, s0, s1120; CHECK-GI-NOFP16-NEXT: fcvt h0, s0121; CHECK-GI-NOFP16-NEXT: ret122;123; CHECK-GI-FP16-LABEL: mul_H:124; CHECK-GI-FP16: // %bb.0:125; CHECK-GI-FP16-NEXT: mov d1, v0.d[1]126; CHECK-GI-FP16-NEXT: fmul v0.4h, v0.4h, v1.4h127; CHECK-GI-FP16-NEXT: mov h1, v0.h[1]128; CHECK-GI-FP16-NEXT: mov h2, v0.h[2]129; CHECK-GI-FP16-NEXT: mov h3, v0.h[3]130; CHECK-GI-FP16-NEXT: fmul h0, h0, h1131; CHECK-GI-FP16-NEXT: fmul h1, h2, h3132; CHECK-GI-FP16-NEXT: fmul h0, h0, h1133; CHECK-GI-FP16-NEXT: ret134 %r = call fast half @llvm.vector.reduce.fmul.f16.v8f16(half 1.0, <8 x half> %bin.rdx)135 ret half %r136}137 138define float @mul_S(<4 x float> %bin.rdx) {139; CHECK-SD-LABEL: mul_S:140; CHECK-SD: // %bb.0:141; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8142; CHECK-SD-NEXT: fmul v0.2s, v0.2s, v1.2s143; CHECK-SD-NEXT: fmul s0, s0, v0.s[1]144; CHECK-SD-NEXT: ret145;146; CHECK-GI-LABEL: mul_S:147; CHECK-GI: // %bb.0:148; CHECK-GI-NEXT: mov d1, v0.d[1]149; CHECK-GI-NEXT: fmul v0.2s, v0.2s, v1.2s150; CHECK-GI-NEXT: mov s1, v0.s[1]151; CHECK-GI-NEXT: fmul s0, s0, s1152; CHECK-GI-NEXT: ret153 %r = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float 1.0, <4 x float> %bin.rdx)154 ret float %r155}156 157define double @mul_D(<2 x double> %bin.rdx) {158; CHECK-LABEL: mul_D:159; CHECK: // %bb.0:160; CHECK-NEXT: fmul d0, d0, v0.d[1]161; CHECK-NEXT: ret162 %r = call fast double @llvm.vector.reduce.fmul.f64.v2f64(double 1.0, <2 x double> %bin.rdx)163 ret double %r164}165 166define half @mul_2H(<16 x half> %bin.rdx) {167; CHECK-SD-NOFP16-LABEL: mul_2H:168; CHECK-SD-NOFP16: // %bb.0:169; CHECK-SD-NOFP16-NEXT: fcvtl v2.4s, v1.4h170; CHECK-SD-NOFP16-NEXT: fcvtl v3.4s, v0.4h171; CHECK-SD-NOFP16-NEXT: fcvtl2 v1.4s, v1.8h172; CHECK-SD-NOFP16-NEXT: fcvtl2 v0.4s, v0.8h173; CHECK-SD-NOFP16-NEXT: fmul v2.4s, v3.4s, v2.4s174; CHECK-SD-NOFP16-NEXT: fmul v0.4s, v0.4s, v1.4s175; CHECK-SD-NOFP16-NEXT: fcvtn v1.4h, v2.4s176; CHECK-SD-NOFP16-NEXT: fcvtn2 v1.8h, v0.4s177; CHECK-SD-NOFP16-NEXT: mov h0, v1.h[1]178; CHECK-SD-NOFP16-NEXT: mov h2, v1.h[2]179; CHECK-SD-NOFP16-NEXT: mov h3, v1.h[3]180; CHECK-SD-NOFP16-NEXT: mov h4, v1.h[4]181; CHECK-SD-NOFP16-NEXT: mov h5, v1.h[5]182; CHECK-SD-NOFP16-NEXT: fcvt s6, h1183; CHECK-SD-NOFP16-NEXT: mov h7, v1.h[6]184; CHECK-SD-NOFP16-NEXT: mov h1, v1.h[7]185; CHECK-SD-NOFP16-NEXT: fcvt s0, h0186; CHECK-SD-NOFP16-NEXT: fcvt s2, h2187; CHECK-SD-NOFP16-NEXT: fcvt s3, h3188; CHECK-SD-NOFP16-NEXT: fcvt s4, h4189; CHECK-SD-NOFP16-NEXT: fcvt s5, h5190; CHECK-SD-NOFP16-NEXT: fcvt s1, h1191; CHECK-SD-NOFP16-NEXT: fmul s0, s6, s0192; CHECK-SD-NOFP16-NEXT: fmul s2, s2, s3193; CHECK-SD-NOFP16-NEXT: fmul s3, s4, s5194; CHECK-SD-NOFP16-NEXT: fcvt s4, h7195; CHECK-SD-NOFP16-NEXT: fmul s0, s0, s2196; CHECK-SD-NOFP16-NEXT: fmul s2, s3, s4197; CHECK-SD-NOFP16-NEXT: fmul s0, s0, s2198; CHECK-SD-NOFP16-NEXT: fmul s0, s0, s1199; CHECK-SD-NOFP16-NEXT: fcvt h0, s0200; CHECK-SD-NOFP16-NEXT: ret201;202; CHECK-SD-FP16-LABEL: mul_2H:203; CHECK-SD-FP16: // %bb.0:204; CHECK-SD-FP16-NEXT: fmul v0.8h, v0.8h, v1.8h205; CHECK-SD-FP16-NEXT: ext v1.16b, v0.16b, v0.16b, #8206; CHECK-SD-FP16-NEXT: fmul v0.4h, v0.4h, v1.4h207; CHECK-SD-FP16-NEXT: fmul h1, h0, v0.h[1]208; CHECK-SD-FP16-NEXT: fmul h1, h1, v0.h[2]209; CHECK-SD-FP16-NEXT: fmul h0, h1, v0.h[3]210; CHECK-SD-FP16-NEXT: ret211;212; CHECK-GI-NOFP16-LABEL: mul_2H:213; CHECK-GI-NOFP16: // %bb.0:214; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v0.4h215; CHECK-GI-NOFP16-NEXT: fcvtl2 v0.4s, v0.8h216; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v1.4h217; CHECK-GI-NOFP16-NEXT: fcvtl2 v1.4s, v1.8h218; CHECK-GI-NOFP16-NEXT: fmul v0.4s, v2.4s, v0.4s219; CHECK-GI-NOFP16-NEXT: fmul v1.4s, v3.4s, v1.4s220; CHECK-GI-NOFP16-NEXT: fmul v0.4s, v0.4s, v1.4s221; CHECK-GI-NOFP16-NEXT: mov d1, v0.d[1]222; CHECK-GI-NOFP16-NEXT: fmul v0.2s, v0.2s, v1.2s223; CHECK-GI-NOFP16-NEXT: mov s1, v0.s[1]224; CHECK-GI-NOFP16-NEXT: fmul s0, s0, s1225; CHECK-GI-NOFP16-NEXT: fcvt h0, s0226; CHECK-GI-NOFP16-NEXT: ret227;228; CHECK-GI-FP16-LABEL: mul_2H:229; CHECK-GI-FP16: // %bb.0:230; CHECK-GI-FP16-NEXT: fmul v0.8h, v0.8h, v1.8h231; CHECK-GI-FP16-NEXT: mov d1, v0.d[1]232; CHECK-GI-FP16-NEXT: fmul v0.4h, v0.4h, v1.4h233; CHECK-GI-FP16-NEXT: mov h1, v0.h[1]234; CHECK-GI-FP16-NEXT: mov h2, v0.h[2]235; CHECK-GI-FP16-NEXT: mov h3, v0.h[3]236; CHECK-GI-FP16-NEXT: fmul h0, h0, h1237; CHECK-GI-FP16-NEXT: fmul h1, h2, h3238; CHECK-GI-FP16-NEXT: fmul h0, h0, h1239; CHECK-GI-FP16-NEXT: ret240 %r = call fast half @llvm.vector.reduce.fmul.f16.v16f16(half 1.0, <16 x half> %bin.rdx)241 ret half %r242}243 244define float @mul_2S(<8 x float> %bin.rdx) {245; CHECK-SD-LABEL: mul_2S:246; CHECK-SD: // %bb.0:247; CHECK-SD-NEXT: fmul v0.4s, v0.4s, v1.4s248; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8249; CHECK-SD-NEXT: fmul v0.2s, v0.2s, v1.2s250; CHECK-SD-NEXT: fmul s0, s0, v0.s[1]251; CHECK-SD-NEXT: ret252;253; CHECK-GI-LABEL: mul_2S:254; CHECK-GI: // %bb.0:255; CHECK-GI-NEXT: fmul v0.4s, v0.4s, v1.4s256; CHECK-GI-NEXT: mov d1, v0.d[1]257; CHECK-GI-NEXT: fmul v0.2s, v0.2s, v1.2s258; CHECK-GI-NEXT: mov s1, v0.s[1]259; CHECK-GI-NEXT: fmul s0, s0, s1260; CHECK-GI-NEXT: ret261 %r = call fast float @llvm.vector.reduce.fmul.f32.v8f32(float 1.0, <8 x float> %bin.rdx)262 ret float %r263}264 265define double @mul_2D(<4 x double> %bin.rdx) {266; CHECK-LABEL: mul_2D:267; CHECK: // %bb.0:268; CHECK-NEXT: fmul v0.2d, v0.2d, v1.2d269; CHECK-NEXT: fmul d0, d0, v0.d[1]270; CHECK-NEXT: ret271 %r = call fast double @llvm.vector.reduce.fmul.f64.v4f64(double 1.0, <4 x double> %bin.rdx)272 ret double %r273}274 275; added at least one test where the start value is not 1.0.276define float @mul_S_init_42(<4 x float> %bin.rdx) {277; CHECK-SD-LABEL: mul_S_init_42:278; CHECK-SD: // %bb.0:279; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8280; CHECK-SD-NEXT: mov w8, #1109917696 // =0x42280000281; CHECK-SD-NEXT: fmul v0.2s, v0.2s, v1.2s282; CHECK-SD-NEXT: fmov s1, w8283; CHECK-SD-NEXT: fmul s0, s0, v0.s[1]284; CHECK-SD-NEXT: fmul s0, s0, s1285; CHECK-SD-NEXT: ret286;287; CHECK-GI-LABEL: mul_S_init_42:288; CHECK-GI: // %bb.0:289; CHECK-GI-NEXT: mov d1, v0.d[1]290; CHECK-GI-NEXT: mov w8, #1109917696 // =0x42280000291; CHECK-GI-NEXT: fmul v0.2s, v0.2s, v1.2s292; CHECK-GI-NEXT: mov s1, v0.s[1]293; CHECK-GI-NEXT: fmul s0, s0, s1294; CHECK-GI-NEXT: fmov s1, w8295; CHECK-GI-NEXT: fmul s0, s0, s1296; CHECK-GI-NEXT: ret297 %r = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float 42.0, <4 x float> %bin.rdx)298 ret float %r299}300 301 302define half @fmul_reduct_reassoc_v8f16(<8 x half> %a, <8 x half> %b) {303; CHECK-SD-NOFP16-LABEL: fmul_reduct_reassoc_v8f16:304; CHECK-SD-NOFP16: // %bb.0:305; CHECK-SD-NOFP16-NEXT: fcvtl v2.4s, v1.4h306; CHECK-SD-NOFP16-NEXT: fcvtl v3.4s, v0.4h307; CHECK-SD-NOFP16-NEXT: fcvtl2 v1.4s, v1.8h308; CHECK-SD-NOFP16-NEXT: fcvtl2 v0.4s, v0.8h309; CHECK-SD-NOFP16-NEXT: fmul v2.4s, v3.4s, v2.4s310; CHECK-SD-NOFP16-NEXT: fmul v0.4s, v0.4s, v1.4s311; CHECK-SD-NOFP16-NEXT: fcvtn v1.4h, v2.4s312; CHECK-SD-NOFP16-NEXT: fcvtn2 v1.8h, v0.4s313; CHECK-SD-NOFP16-NEXT: mov h0, v1.h[1]314; CHECK-SD-NOFP16-NEXT: mov h2, v1.h[2]315; CHECK-SD-NOFP16-NEXT: mov h3, v1.h[3]316; CHECK-SD-NOFP16-NEXT: mov h4, v1.h[4]317; CHECK-SD-NOFP16-NEXT: mov h5, v1.h[5]318; CHECK-SD-NOFP16-NEXT: fcvt s6, h1319; CHECK-SD-NOFP16-NEXT: mov h7, v1.h[6]320; CHECK-SD-NOFP16-NEXT: mov h1, v1.h[7]321; CHECK-SD-NOFP16-NEXT: fcvt s0, h0322; CHECK-SD-NOFP16-NEXT: fcvt s2, h2323; CHECK-SD-NOFP16-NEXT: fcvt s3, h3324; CHECK-SD-NOFP16-NEXT: fcvt s4, h4325; CHECK-SD-NOFP16-NEXT: fcvt s5, h5326; CHECK-SD-NOFP16-NEXT: fcvt s1, h1327; CHECK-SD-NOFP16-NEXT: fmul s0, s6, s0328; CHECK-SD-NOFP16-NEXT: fmul s2, s2, s3329; CHECK-SD-NOFP16-NEXT: fmul s3, s4, s5330; CHECK-SD-NOFP16-NEXT: fcvt s4, h7331; CHECK-SD-NOFP16-NEXT: fmul s0, s0, s2332; CHECK-SD-NOFP16-NEXT: fmul s2, s3, s4333; CHECK-SD-NOFP16-NEXT: fmul s0, s0, s2334; CHECK-SD-NOFP16-NEXT: fmul s0, s0, s1335; CHECK-SD-NOFP16-NEXT: fcvt h0, s0336; CHECK-SD-NOFP16-NEXT: ret337;338; CHECK-SD-FP16-LABEL: fmul_reduct_reassoc_v8f16:339; CHECK-SD-FP16: // %bb.0:340; CHECK-SD-FP16-NEXT: fmul v0.8h, v0.8h, v1.8h341; CHECK-SD-FP16-NEXT: ext v1.16b, v0.16b, v0.16b, #8342; CHECK-SD-FP16-NEXT: fmul v0.4h, v0.4h, v1.4h343; CHECK-SD-FP16-NEXT: fmul h1, h0, v0.h[1]344; CHECK-SD-FP16-NEXT: fmul h1, h1, v0.h[2]345; CHECK-SD-FP16-NEXT: fmul h0, h1, v0.h[3]346; CHECK-SD-FP16-NEXT: ret347;348; CHECK-GI-NOFP16-LABEL: fmul_reduct_reassoc_v8f16:349; CHECK-GI-NOFP16: // %bb.0:350; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v0.4h351; CHECK-GI-NOFP16-NEXT: fcvtl2 v0.4s, v0.8h352; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v1.4h353; CHECK-GI-NOFP16-NEXT: fcvtl2 v1.4s, v1.8h354; CHECK-GI-NOFP16-NEXT: fmul v0.4s, v2.4s, v0.4s355; CHECK-GI-NOFP16-NEXT: fmul v1.4s, v3.4s, v1.4s356; CHECK-GI-NOFP16-NEXT: mov d2, v0.d[1]357; CHECK-GI-NOFP16-NEXT: mov d3, v1.d[1]358; CHECK-GI-NOFP16-NEXT: fmul v0.2s, v0.2s, v2.2s359; CHECK-GI-NOFP16-NEXT: fmul v1.2s, v1.2s, v3.2s360; CHECK-GI-NOFP16-NEXT: mov s2, v0.s[1]361; CHECK-GI-NOFP16-NEXT: mov s3, v1.s[1]362; CHECK-GI-NOFP16-NEXT: fmul s0, s0, s2363; CHECK-GI-NOFP16-NEXT: fmul s1, s1, s3364; CHECK-GI-NOFP16-NEXT: fcvt h0, s0365; CHECK-GI-NOFP16-NEXT: fcvt h1, s1366; CHECK-GI-NOFP16-NEXT: fcvt s0, h0367; CHECK-GI-NOFP16-NEXT: fcvt s1, h1368; CHECK-GI-NOFP16-NEXT: fmul s0, s0, s1369; CHECK-GI-NOFP16-NEXT: fcvt h0, s0370; CHECK-GI-NOFP16-NEXT: ret371;372; CHECK-GI-FP16-LABEL: fmul_reduct_reassoc_v8f16:373; CHECK-GI-FP16: // %bb.0:374; CHECK-GI-FP16-NEXT: mov d2, v0.d[1]375; CHECK-GI-FP16-NEXT: mov d3, v1.d[1]376; CHECK-GI-FP16-NEXT: fmul v0.4h, v0.4h, v2.4h377; CHECK-GI-FP16-NEXT: fmul v1.4h, v1.4h, v3.4h378; CHECK-GI-FP16-NEXT: mov h2, v0.h[1]379; CHECK-GI-FP16-NEXT: mov h3, v0.h[2]380; CHECK-GI-FP16-NEXT: mov h4, v0.h[3]381; CHECK-GI-FP16-NEXT: mov h5, v1.h[1]382; CHECK-GI-FP16-NEXT: mov h6, v1.h[2]383; CHECK-GI-FP16-NEXT: mov h7, v1.h[3]384; CHECK-GI-FP16-NEXT: fmul h0, h0, h2385; CHECK-GI-FP16-NEXT: fmul h2, h3, h4386; CHECK-GI-FP16-NEXT: fmul h1, h1, h5387; CHECK-GI-FP16-NEXT: fmul h3, h6, h7388; CHECK-GI-FP16-NEXT: fmul h0, h0, h2389; CHECK-GI-FP16-NEXT: fmul h1, h1, h3390; CHECK-GI-FP16-NEXT: fmul h0, h0, h1391; CHECK-GI-FP16-NEXT: ret392 %r1 = call fast half @llvm.vector.reduce.fmul.f16.v8f16(half 1.0, <8 x half> %a)393 %r2 = call fast half @llvm.vector.reduce.fmul.f16.v8f16(half 1.0, <8 x half> %b)394 %r = fmul fast half %r1, %r2395 ret half %r396}397 398define float @fmul_reduct_reassoc_v8f32(<8 x float> %a, <8 x float> %b) {399; CHECK-SD-LABEL: fmul_reduct_reassoc_v8f32:400; CHECK-SD: // %bb.0:401; CHECK-SD-NEXT: fmul v2.4s, v2.4s, v3.4s402; CHECK-SD-NEXT: fmul v0.4s, v0.4s, v1.4s403; CHECK-SD-NEXT: fmul v0.4s, v0.4s, v2.4s404; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8405; CHECK-SD-NEXT: fmul v0.2s, v0.2s, v1.2s406; CHECK-SD-NEXT: fmul s0, s0, v0.s[1]407; CHECK-SD-NEXT: ret408;409; CHECK-GI-LABEL: fmul_reduct_reassoc_v8f32:410; CHECK-GI: // %bb.0:411; CHECK-GI-NEXT: fmul v0.4s, v0.4s, v1.4s412; CHECK-GI-NEXT: fmul v1.4s, v2.4s, v3.4s413; CHECK-GI-NEXT: mov d2, v0.d[1]414; CHECK-GI-NEXT: mov d3, v1.d[1]415; CHECK-GI-NEXT: fmul v0.2s, v0.2s, v2.2s416; CHECK-GI-NEXT: fmul v1.2s, v1.2s, v3.2s417; CHECK-GI-NEXT: mov s2, v0.s[1]418; CHECK-GI-NEXT: mov s3, v1.s[1]419; CHECK-GI-NEXT: fmul s0, s0, s2420; CHECK-GI-NEXT: fmul s1, s1, s3421; CHECK-GI-NEXT: fmul s0, s0, s1422; CHECK-GI-NEXT: ret423 %r1 = call fast float @llvm.vector.reduce.fmul.f32.v8f32(float 1.0, <8 x float> %a)424 %r2 = call fast float @llvm.vector.reduce.fmul.f32.v8f32(float 1.0, <8 x float> %b)425 %r = fmul fast float %r1, %r2426 ret float %r427}428 429define float @fmul_reduct_reassoc_v4f32(<4 x float> %a, <4 x float> %b) {430; CHECK-SD-LABEL: fmul_reduct_reassoc_v4f32:431; CHECK-SD: // %bb.0:432; CHECK-SD-NEXT: fmul v0.4s, v0.4s, v1.4s433; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8434; CHECK-SD-NEXT: fmul v0.2s, v0.2s, v1.2s435; CHECK-SD-NEXT: fmul s0, s0, v0.s[1]436; CHECK-SD-NEXT: ret437;438; CHECK-GI-LABEL: fmul_reduct_reassoc_v4f32:439; CHECK-GI: // %bb.0:440; CHECK-GI-NEXT: mov d2, v0.d[1]441; CHECK-GI-NEXT: mov d3, v1.d[1]442; CHECK-GI-NEXT: fmul v0.2s, v0.2s, v2.2s443; CHECK-GI-NEXT: fmul v1.2s, v1.2s, v3.2s444; CHECK-GI-NEXT: mov s2, v0.s[1]445; CHECK-GI-NEXT: mov s3, v1.s[1]446; CHECK-GI-NEXT: fmul s0, s0, s2447; CHECK-GI-NEXT: fmul s1, s1, s3448; CHECK-GI-NEXT: fmul s0, s0, s1449; CHECK-GI-NEXT: ret450 %r1 = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float 1.0, <4 x float> %a)451 %r2 = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float 1.0, <4 x float> %b)452 %r = fmul fast float %r1, %r2453 ret float %r454}455 456define float @fmul_reduct_reassoc_v4f32_init(float %i, <4 x float> %a, <4 x float> %b) {457; CHECK-SD-LABEL: fmul_reduct_reassoc_v4f32_init:458; CHECK-SD: // %bb.0:459; CHECK-SD-NEXT: ext v3.16b, v1.16b, v1.16b, #8460; CHECK-SD-NEXT: fmul v1.2s, v1.2s, v3.2s461; CHECK-SD-NEXT: ext v3.16b, v2.16b, v2.16b, #8462; CHECK-SD-NEXT: fmul s1, s1, v1.s[1]463; CHECK-SD-NEXT: fmul v2.2s, v2.2s, v3.2s464; CHECK-SD-NEXT: fmul s0, s0, s1465; CHECK-SD-NEXT: fmul s1, s2, v2.s[1]466; CHECK-SD-NEXT: fmul s0, s0, s1467; CHECK-SD-NEXT: ret468;469; CHECK-GI-LABEL: fmul_reduct_reassoc_v4f32_init:470; CHECK-GI: // %bb.0:471; CHECK-GI-NEXT: mov d3, v1.d[1]472; CHECK-GI-NEXT: fmul v1.2s, v1.2s, v3.2s473; CHECK-GI-NEXT: mov d3, v2.d[1]474; CHECK-GI-NEXT: mov s4, v1.s[1]475; CHECK-GI-NEXT: fmul v2.2s, v2.2s, v3.2s476; CHECK-GI-NEXT: fmul s1, s1, s4477; CHECK-GI-NEXT: mov s3, v2.s[1]478; CHECK-GI-NEXT: fmul s0, s0, s1479; CHECK-GI-NEXT: fmul s1, s2, s3480; CHECK-GI-NEXT: fmul s0, s0, s1481; CHECK-GI-NEXT: ret482 %r1 = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float %i, <4 x float> %a)483 %r2 = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float 1.0, <4 x float> %b)484 %r = fmul fast float %r1, %r2485 ret float %r486}487 488define float @fmul_reduct_reassoc_v4v8f32(<4 x float> %a, <8 x float> %b) {489; CHECK-SD-LABEL: fmul_reduct_reassoc_v4v8f32:490; CHECK-SD: // %bb.0:491; CHECK-SD-NEXT: fmul v1.4s, v1.4s, v2.4s492; CHECK-SD-NEXT: fmul v0.4s, v0.4s, v1.4s493; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8494; CHECK-SD-NEXT: fmul v0.2s, v0.2s, v1.2s495; CHECK-SD-NEXT: fmul s0, s0, v0.s[1]496; CHECK-SD-NEXT: ret497;498; CHECK-GI-LABEL: fmul_reduct_reassoc_v4v8f32:499; CHECK-GI: // %bb.0:500; CHECK-GI-NEXT: fmul v1.4s, v1.4s, v2.4s501; CHECK-GI-NEXT: mov d2, v0.d[1]502; CHECK-GI-NEXT: mov d3, v1.d[1]503; CHECK-GI-NEXT: fmul v0.2s, v0.2s, v2.2s504; CHECK-GI-NEXT: fmul v1.2s, v1.2s, v3.2s505; CHECK-GI-NEXT: mov s2, v0.s[1]506; CHECK-GI-NEXT: mov s3, v1.s[1]507; CHECK-GI-NEXT: fmul s0, s0, s2508; CHECK-GI-NEXT: fmul s1, s1, s3509; CHECK-GI-NEXT: fmul s0, s0, s1510; CHECK-GI-NEXT: ret511 %r1 = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float 1.0, <4 x float> %a)512 %r2 = call fast float @llvm.vector.reduce.fmul.f32.v8f32(float 1.0, <8 x float> %b)513 %r = fmul fast float %r1, %r2514 ret float %r515}516 517define double @fmul_reduct_reassoc_v4f64(<4 x double> %a, <4 x double> %b) {518; CHECK-SD-LABEL: fmul_reduct_reassoc_v4f64:519; CHECK-SD: // %bb.0:520; CHECK-SD-NEXT: fmul v2.2d, v2.2d, v3.2d521; CHECK-SD-NEXT: fmul v0.2d, v0.2d, v1.2d522; CHECK-SD-NEXT: fmul v0.2d, v0.2d, v2.2d523; CHECK-SD-NEXT: fmul d0, d0, v0.d[1]524; CHECK-SD-NEXT: ret525;526; CHECK-GI-LABEL: fmul_reduct_reassoc_v4f64:527; CHECK-GI: // %bb.0:528; CHECK-GI-NEXT: fmul v0.2d, v0.2d, v1.2d529; CHECK-GI-NEXT: fmul v1.2d, v2.2d, v3.2d530; CHECK-GI-NEXT: fmul d0, d0, v0.d[1]531; CHECK-GI-NEXT: fmul d1, d1, v1.d[1]532; CHECK-GI-NEXT: fmul d0, d0, d1533; CHECK-GI-NEXT: ret534 %r1 = call fast double @llvm.vector.reduce.fmul.f64.v4f64(double 1.0, <4 x double> %a)535 %r2 = call fast double @llvm.vector.reduce.fmul.f64.v4f64(double 1.0, <4 x double> %b)536 %r = fmul fast double %r1, %r2537 ret double %r538}539 540define float @fmul_reduct_reassoc_v4f32_extrause(<4 x float> %a, <4 x float> %b) {541; CHECK-SD-LABEL: fmul_reduct_reassoc_v4f32_extrause:542; CHECK-SD: // %bb.0:543; CHECK-SD-NEXT: ext v2.16b, v0.16b, v0.16b, #8544; CHECK-SD-NEXT: ext v3.16b, v1.16b, v1.16b, #8545; CHECK-SD-NEXT: fmul v0.2s, v0.2s, v2.2s546; CHECK-SD-NEXT: fmul v1.2s, v1.2s, v3.2s547; CHECK-SD-NEXT: fmul s0, s0, v0.s[1]548; CHECK-SD-NEXT: fmul s1, s1, v1.s[1]549; CHECK-SD-NEXT: fmul s1, s0, s1550; CHECK-SD-NEXT: fmul s0, s1, s0551; CHECK-SD-NEXT: ret552;553; CHECK-GI-LABEL: fmul_reduct_reassoc_v4f32_extrause:554; CHECK-GI: // %bb.0:555; CHECK-GI-NEXT: mov d2, v0.d[1]556; CHECK-GI-NEXT: mov d3, v1.d[1]557; CHECK-GI-NEXT: fmul v0.2s, v0.2s, v2.2s558; CHECK-GI-NEXT: fmul v1.2s, v1.2s, v3.2s559; CHECK-GI-NEXT: mov s2, v0.s[1]560; CHECK-GI-NEXT: mov s3, v1.s[1]561; CHECK-GI-NEXT: fmul s0, s0, s2562; CHECK-GI-NEXT: fmul s1, s1, s3563; CHECK-GI-NEXT: fmul s1, s0, s1564; CHECK-GI-NEXT: fmul s0, s1, s0565; CHECK-GI-NEXT: ret566 %r1 = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float 1.0, <4 x float> %a)567 %r2 = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float 1.0, <4 x float> %b)568 %r = fmul fast float %r1, %r2569 %p = fmul float %r, %r1570 ret float %p571}572 573; Function Attrs: nounwind readnone574declare half @llvm.vector.reduce.fmul.f16.v4f16(half, <4 x half>)575declare half @llvm.vector.reduce.fmul.f16.v8f16(half, <8 x half>)576declare half @llvm.vector.reduce.fmul.f16.v16f16(half, <16 x half>)577declare float @llvm.vector.reduce.fmul.f32.v2f32(float, <2 x float>)578declare float @llvm.vector.reduce.fmul.f32.v4f32(float, <4 x float>)579declare float @llvm.vector.reduce.fmul.f32.v8f32(float, <8 x float>)580declare double @llvm.vector.reduce.fmul.f64.v2f64(double, <2 x double>)581declare double @llvm.vector.reduce.fmul.f64.v4f64(double, <4 x double>)582